Never stop thinking.
Microcontrollers
Data Sheet, V1.2, May 2002
TC1775
32-Bit Single-Chip Microcontroller
Edition 2002-05
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2002.
All Rights Reserved.
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Microcontrollers
Data Sheet, V1.2, May 2002
Never stop thinking.
TC1775
32-Bit Single-Chip Microcontroller
TC1775 Data Sheet
Preliminary
Revision History: 2002-05 V1.2
Previous Versions: V1.1, 2001-08; V1.0, 2001-08;
Page Subjects (major changes since last revision)
Changes from V1.1, 2001-08 to V1.2, 2002-05
– Status of data sheet changed from “Advance Information” into “Preliminary”
36 ADC features: example of 10-bit ADC conversion time added
54 Note below Figure 16 added
59 Column “Jitter” in Table 8 removed; the jitter is now defined in “PLL
Parameters” on Page 82 and Figure 31; 2nd footnote for Table 8 added
60 Note on bottom extended “… specified by the crystal suppliers:”
66 Section “Package Parameters” added
68, 69, 70 Definition and values for pull-up/pull-down currents changed
71 Curves for pull-up/pull-down characteristics added
73 Formulas for conversion time tC corrected; fANA min./max. specification
added
73 Definition of IAOV and kA improved
76 Note 1) for IOZ added
77 IDD max corrected; IDD active for VDDSB added; note for IID and ISL added
78 tRFAnom (typ.) added
80 Figure 29 corrected
81 Figure 30 corrected
82, 83 PLL specification and parameters completed
84, 87, 89,
92, 94, 95
Several AC timing parameter values added or corrected: t10, t11, t15, t20,
t21, t25, t45, t46, t47, t55, t61, t62
95 Definition of t61 and t62 changed
several Formal changes
Changes from V1.0, 2001-08 to V1.1, 2001-08
84 Reference for t31 and t32 to Page 90 added
89 t50 and t51 changed into TBD; note changed into “Will be guaranteed …”
90 t31 and t32 (Data setup/hold to CLKIN in burst mode timing) changed;
note 1) added
95 t61 and t62 changed into TBD; note changed into “Will be guaranteed …”
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Data Sheet 1 V1.2, 2002-05
Preliminary
TC177532-Bit Single-Chip Microcontroller
TriCore Family
• High Performance 32-bit TriCore CPU with 4-Stage Pipeline
– 25 ns Instruction Cycle Time at 40 MHz CPU Clock
• Dual Issue super-scalar implementation
– Instruction triple issue
• Circular Buffer and bit-reverse addressing modes for DSP algorithms
• Flexible multi-master interrupt system
• Very fast interrupt response time
• Hardware controlled context switch for task switch and interrupts
• 72 Kbytes of on-chip SRAM for data and time critical code
• Independent Peripheral Control Processor (PCP) for low level driver support with
20 Kbytes code/parameter memory
• Built-in calibration support
• On-chip Flexible Peripheral Interface Bus (FPI Bus) for interconnections of functional
units
• Flexible External Bus Interface Unit (EBU) used for
– Communication with external data memories and peripheral units
– Instruction fetches from external Burst Flash program memories
• On-Chip Peripheral Units
– General Purpose Timer Array (GPTA) with a powerful set of digital signal filtering
and timer functionality to realize autonomous and complex I/O management
– Multifunctional General Purpose Timer Unit (GPTU) with three 32-bit timer/counters
– Two Asynchronous/Synchronous Serial Channels (ASC0, ASC1) with baud rate
generator, parity, framing and overrun error detection
– Two High Speed Synchronous Serial Channels (SSC0, SSC1) with programmable
data length and shift direction
– TwinCAN module with two interconnected CAN nodes for high efficiency data
handling via FIFO buffering and gateway data transfer
– Serial Data Link module (SDLM) compliant to SAE Class B J1850 specification
– Two Analog-to-Digital Converter Units (ADC0, ADC1) with 8-bit, 10-bit, or 12-bit
resolution and 16 analog inputs each
– Watchdog Timer and System Timer
– Real Time Clock
• Eleven 16-bit digital I/O ports and two 16-bit analog ports
• On-chip Debug Support
• Power Management System
• Clock Generation Unit with PLL
• Ambient temperature under bias: -40 °C to +125 °C
• P-BGA-329 package
TC1775
Data Sheet 2 V1.2, 2002-05
Preliminary
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies: the derivative itself, i.e. its function set,
the temperature range, and the package and the type of delivery.
The TC1775 is available with the following ordering code:
Type Ordering Code Package Description
SAK-TC1775-L40E Q67121-C2285-A701 P-BGA-329 32-Bit Single-Chip
Microcontroller
40 MHz
-40 °C to +125 °C
TC1775
Data Sheet 3 V1.2, 2002-05
Preliminary
Block Diagram
Figure 1 TC1775 Block Diagram
MCB04671
J1850
Twin
CAN
SSC0SSC1ASC0ASC1ADC0ADC1GPTA
433216
EBU
(External
Bus
Unit)
Port 4
12 16
Port 0
16 16
Port 1
16 16
Port 2
16 16 Addr.
[15:0]
Addr./
Data
[15:0]
Addr./
Data
(31:16]
Port 13
Port 10
16
16
Port 9
16
Port 8 Port 7 Port 6
16 16 2
GPTU
8
Port 11
16
16
Port 12
16
5
2
5
2
PCP
Core
OCDS
Interrupt
4 K Data-SRAM
FPI Interface
2
STM
BCU RTC
PLL
FPI Bus
CLKOUT
CLKIN
XTAL4
XTAL3
f
RTC
= 32 kHz
XTAL2
XTAL1
Control
f
CPUmax
=
40 MHz
Port 5
16
16
16
Cerberus
& JTAG
SCU
(PW R)
Power-
Watchdog-
Reset
5
JTAG IO
BRKOUT
BRKIN
Control 9
DMU
(Data Memory Unit)
32 KB SRAM +
8 KB Stand-by SRAM
(Overlay Functionality)
TriCore
CPU
Trace &
OCDS Interrupt
V
SS
V
DD
128 64
OCDSE
PMU
(Program Memory Unit)
8 KB Boot ROM
32 KB Scratch Pad RAM
1 KB Instruction Cache
FPI Bus
32
32
16 16 16 16 16 16
EBU
Control
10
Address
[25:16]
6
Port 3
4
16 K Code-SRAM
TC1775
Data Sheet 4 V1.2, 2002-05
Preliminary
Logic Symbol
Figure 2 TC1775 Logic Symbol
MCA04679
TC 1775
Port 0
16-Bit
Port 1
16-Bit
Port 2
16-Bit
Port 3
16-Bit
Port 4
16-Bit
Port 5
16-Bit
Port 6
16-Bit
Port 7
16-Bit
Port 8
16-Bit
Port 9
16-Bit
Port 10
16-Bit
Port 11
16-Bit
Port 12
16-Bit
Port 13
16-Bit
V
AREF0
V
AGND0
V
DDA0
V
SSA0
V
AREF1
V
AGND1
V
DDA1
V
SSA1
Alternate Functions
External
Bus Interface
TRACE
ADC0
ADC1
GPTA
ADC0/1
J1850 / ASC0/1
GPTU /
SSC0/1 / CAN
ADC0
Analog
Power Supply
ADC1
Analog
Power Supply
V
SSM
V
DDM
V
SSSC
V
DDSC
ADC0 / ADC1
Analog
Power Supply
V
SS
V
DDSB
V
DDSRAM
V
DDP813
V
DDP05
V
DD
10
5
6
2
29
Digital Circuitry
Power Supply
BRKOUT
BRKIN
OCDSE
TMS
TDO
TDI
TCK
TRST
JTAG / OCDS
V
SSPLL
V
DDPLL
V
SSOSC
V
DDOSC
XTAL4
XTAL3
XTAL2
XTAL1
Oscillators / PLL
3
CLKSEL
BYPASS
CFG
NMI
PORST
HDRST
CLKOUT
CLKIN
TESTMODE
4
General Control
3
N.C.1 7
N.C.2
TC1775
Data Sheet 5 V1.2, 2002-05
Preliminary
Pin Configuration
Figure 3 TC1775 Pinning: P-BGA-329 Package (top view)
MCP04680
AN
3AN
6AN
9
1234567
AN
11 AN
15
89
P12.
13
10 11
P12.
9P12.
5
12 13
P12.
1P13
15
14 15
P13.
11 P13.
8
16 17
P13.
4P13.
2
18 19
P11.
15 P11.
12
20 21
P11.
8P11.
5
22 23
P11.
4
V
SSA0
V
SSM
V
SSSC
V
DDSC
A
AN
16
BAN
17 AN
0AN
4AN
7AN
10 AN
13 P12.
15 P12.
12 P12.
7P12.
6P12.
2P13.
13 P13.
9P13.
6P13.
3P13.
0P11.
13 P11.
9P11.
6P11.
3
V
DDSB
AN
19
C
V
DDM
AN
20 AN
1AN
5AN
8AN
14 P12.
14 P12.
11 P12.
8P12.
4P12.
3N.C.
2P13.
14 P13.
10 P13.
7P13.
1P11.
14 P11.
10 P11.
0P11.
1
A
B
C
AN
23
DAN
24 AN
18 AN
2
AN
21
V
SS
AN
12
V
DD
P813
V
DDA0
N.C.
1P12.
10 P12.
0P13.
12
V
DD
V
DD
P813
P13.
5
V
SS
P11.
11 P11.
7N.C.
2P10.
13 P10.
14 D
AN
26
EAN
27 AN
22
AN
25
AN
29
FAN
30 AN
28
V
SS
V
AREF0
V
AGND0
V
AGND1
V
SSA1
V
AREF1
AN
31
G
V
DDA1
HP1.0 P1.1
V
DD
P05
P1.2
JP1.4 P1.5 P1.3
P1.6
KP1.7 N.C.
2
V
DD
P1.8
LP1.9 P1.10 N.C.
2
P1.12
MP1.13 P1.11
V
DD
P05
P0.0
NP1.14 P1.15 P0.1
P0.4
PP0.3 P0.2
V
DD
P0.6 P0.5 P0.7
CLK
OUT
R
P0.9 P0.8
CLK
IN
T
V
DD
P05
P0.13
UP0.11 P0.10 P0.12
V
DD
P0.15
VP0.14 P4.0
P4.2
WP4.1 P4.3 P4.6
P4.5
YP4.4 P4.7 P4.15 P2.2
V
SS
P2.12
V
DD
P05
P3.3
V
DD
P3.9
V
DD
P05
P5.3 N.C.
1P5.8 N.C.
2P5.15
V
DD
OCD
SE NMI PO
RST
CFG
1
TRST
CFG
0
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
E
P10.
15 P10.
12 P10.
10 P10.
11
V
DD
P10.
9P10.
7P10.
8
P10.
3P10.
4P10.
6
P10.
5
P10.
0P10.
1P10.
2
V
DD
P813
P9.14 P9.12 P9.13 P9.15
V
DD
P9.9 P9.10 P9.11
P9.6 P9.5 P9.7P9.8
V
DD
P813
P9.2 P9.4 P9.3
P9.1 P9.0 P8.15P8.14
V
DD
P8.13 P8.12 P8.11
P8.10 P8.9 P8.7P8.8
V
DD
P813
P8.6 P8.5 P8.4
P8.3 P8.2 P8.0P8.1
V
SS
CLK
SEL0 CLK
SEL2 CLK
SEL1
CFG
2BY
PASS CFG
3
HD
RST
AA P4.9 P4.8 P4.10 P2.1 P2.5 P2.8 P2.14 P3.1 P3.5 P3.8 P3.12 P3.13 P5.1 P5.4 P5.7 P5.10 P5.13 TDO XTAL
4
V
SS
OSC
V
DD
PLL
V
SS
PLL
AA
AB P4.14P4.11 P2.0 P2.4 P2.7 P2.10 P2.13 P3.0 P3.4 P3.7 P3.11 P3.15 P5.0 P5.5 P5.11 P5.14
N.C.
1
V
DD
SRAM
TCK TMS XTAL
3
N.C.
2TEST
MODE AB
P4.12 P4.13
AC N.C.
2P2.3 P2.6 P2.9 P2.11 P2.15 P3.2 P3.6 P3.10 P3.14 P5.2 P5.6 P5.9 P5.12
V
DD
SRAM
BRK
OUT TDI BRK
IN
V
DD
OSC
XTAL
2XTAL
1AC
1 2 3 4 5 6 7 8 9 1011121314151617181920212223
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
P11.
2
V
DD
P813
TC1775
Data Sheet 6 V1.2, 2002-05
Preliminary
Table 1 Pin Definitions and Functions
Symbol Pin In
Out
Functions
P0
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
N1
N4
P3
P2
P1
R3
R2
R4
T3
T2
U3
U2
U4
U1
V2
V1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 0
Port 0 serves as 16-bit general purpose I/O port or as lower
external address/data bus AD[15:0] (multiplexed bus mode)
or data bus D[15:0] (demultiplexed bus mode) for the EBU.
Port 0 is used as data input by an external bus master when
accessing modules on the internal FPI Bus.
AD0 / D0 Address/data bus line 0 / Data bus line 0
AD1 / D1 Address/data bus line 1 / Data bus line 1
AD2 / D2 Address/data bus line 2 / Data bus line 2
AD3 / D3 Address/data bus line 3 / Data bus line 3
AD4 / D4 Address/data bus line 4 / Data bus line 4
AD5 / D5 Address/data bus line 5 / Data bus line 5
AD6 / D6 Address/data bus line 6 / Data bus line 6
AD7 / D7 Address/data bus line 7 / Data bus line 7
AD8 / D8 Address/data bus line 8 / Data bus line 8
AD9 / D9 Address/data bus line 9 / Data bus line 9
AD10 / D10 Address/data bus line 10 / Data bus line 10
AD11 / D11 Address/data bus line 11 / Data bus line 11
AD12 / D12 Address/data bus line 12 / Data bus line 12
AD13 / D13 Address/data bus line 13 / Data bus line 13
AD14 / D14 Address/data bus line 14 / Data bus line 14
AD15 / D15 Address/data bus line 15 / Data bus line 15
TC1775
Data Sheet 7 V1.2, 2002-05
Preliminary
P1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P1.8
P1.9
P1.10
P1.11
P1.12
P1.13
P1.14
P1.15
H2
H3
J1
J4
J2
J3
K1
K2
L1
L2
L3
M3
M1
M2
N2
N3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 1
Port 1 serves as 16-bit general purpose I/O port or as upper
external address/data bus AD[31:16] (multiplexed bus mode)
or data bus D[31:16] (demultiplexed bus mode) for the EBU.
Port 1 is used as data input by an external bus master when
accessing modules on the internal FPI Bus.
AD16 / D16 Address/data bus line 16 / Data bus line 16
AD17 / D17 Address/data bus line 17/ Data bus line 17
AD18 / D18 Address/data bus line 18 / Data bus line 18
AD19 / D19 Address/data bus line 19 / Data bus line 19
AD20 / D20 Address/data bus line 20 / Data bus line 20
AD21 / D21 Address/data bus line 21 / Data bus line 21
AD22 / D22 Address/data bus line 22 / Data bus line 22
AD23 / D23 Address/data bus line 23 / Data bus line 23
AD24 / D24 Address/data bus line 24 / Data bus line 24
AD25 / D25 Address/data bus line 25 / Data bus line 25
AD26 / D26 Address/data bus line 26 / Data bus line 26
AD27 / D27 Address/data bus line 27 / Data bus line 27
AD28 / D28 Address/data bus line 28 / Data bus line 28
AD29 / D29 Address/data bus line 29 / Data bus line 29
AD30 / D30 Address/data bus line 30 / Data bus line 30
AD31 / D31 Address/data bus line 31 / Data bus line 31
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 8 V1.2, 2002-05
Preliminary
P2
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
AB3
AA4
Y5
AC4
AB4
AA5
AC5
AB5
AA6
AC6
AB6
AC7
Y7
AB7
AA7
AC8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 2
Port 2 serves as 16-bit general purpose I/O port or as lower
external address bus for the EBU. When used as address
bus, it outputs the addresses A[15:0] of an external access in
demultiplexed bus mode.
Port 2 is used as address input by an external bus master
when accessing modules on the internal FPI Bus.
A0 Address bus line 0
A1 Address bus line 1
A2 Address bus line 2
A3 Address bus line 3
A4 Address bus line 4
A5 Address bus line 5
A6 Address bus line 6
A7 Address bus line 7
A8 Address bus line 8
A9 Address bus line 9
A10 Address bus line 10
A11 Address bus line 11
A12 Address bus line 12
A13 Address bus line 13
A14 Address bus line 14
A15 Address bus line 15
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 9 V1.2, 2002-05
Preliminary
P3
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.101)
P3.111)
P3.121)
P3.131)
P3.141)
P3.151)
AB8
AA8
AC9
Y9
AB9
AA9
AC10
AB10
AA10
Y11
AC11
AB11
AA11
AA12
AC12
AB12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
Port 3
Port 3 serves as 16-bit general purpose I/O port or as upper
external address bus for the EBU. When used as address
bus, it outputs the addresses A[25:16] of an external access
in demultiplexed bus mode.
P3[9:0] is used as address input by an external bus master
when accessing modules on the internal FPI Bus.
Port 3 also provides chip select output lines CS0 - CS3,
CSEMU, and CSOVL.
A16 Address bus line 16
A17 Address bus line 17
A18 Address bus line 18
A19 Address bus line 19
A20 Address bus line 20
A21 Address bus line 21
A22 Address bus line 22
A23 Address bus line 23
A24 Address bus line 24
A25 Address bus line 25
CS3 Chip select output line 3
CS2 Chip select output line 2
CS1 Chip select output line 1
CS0 Chip select output line 0
CSEMU Chip select output for emulator region
CSOVL Chip select output for emulator overlay memory
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 10 V1.2, 2002-05
Preliminary
P4
P4.01)
P4.11)
P4.22)
P4.31)
P4.41)
P4.51)
P4.61)
P4.71)
P4.81)
P4.91)
P4.101)
P4.111)
P4.121)
P4.131)
P4.141)
P4.151)
V3
W2
W1
W3
Y2
Y1
W4
Y3
AA2
AA1
AA3
AB1
AC1
AC2
AB2
Y4
I/O
I/O
I/O
O
O
I/O
I/O
I/O
I/O
I
O
I
I
I/O
O
O
I/O
Port 4
Port 4 is used as general purpose I/O port but also serves as
control bus for the EBU control lines.
RD Read control line
RD/WR Write control line
ALE Address latch enable output
ADV Address valid output
BC0 Byte control line 0
BC1 Byte control line 1
BC2 Byte control line 2
BC3 Byte control line 3
WAIT/IND Wait input / End of burst input
BAA Burst address advance output
CSFPI Chip select FPI input
HOLD Hold request input
HLDA Hold acknowledge input/output
BREQ Bus request output
CODE Code fetch status output
SVM Supervisor mode input/output
The CODE signal has the same timing as the CSx signals
which are located at Port 3.
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 11 V1.2, 2002-05
Preliminary
P5
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.8
P5.9
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15
AB13
AA13
AC13
Y13
AA14
AB14
AC14
AA15
Y15
AC15
AA16
AB16
AC16
AA17
AB17
Y17
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Port 5
Port 5 serves as 16-bit general purpose I/O port or as CPU
or PCP trace output port for the OCDS logic.
TRACE0 CPU or PCP trace output 0
TRACE1 CPU or PCP trace output 1
TRACE2 CPU or PCP trace output 2
TRACE3 CPU or PCP trace output 3
TRACE4 CPU or PCP trace output 4
TRACE5 CPU or PCP trace output 5
TRACE6 CPU or PCP trace output 6
TRACE7 CPU or PCP trace output 7
TRACE8 CPU or PCP trace output 8
TRACE9 CPU or PCP trace output 9
TRACE10 CPU or PCP trace output 10
TRACE11 CPU or PCP trace output 11
TRACE12 CPU or PCP trace output 12
TRACE13 CPU or PCP trace output 13
TRACE14 CPU or PCP trace output 14
TRACE15 CPU or PCP trace output 15
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 12 V1.2, 2002-05
Preliminary
P6
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P6.8
P6.9
P6.10
P6.11
P6.12
P6.13
P6.14
P6.15
B3
C4
D5
A4
B4
C5
A5
B5
C6
A6
B6
A7
D7
B7
C7
A8
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Port 6
Port 6 provides the analog input lines for the AD Converter 0
(ADC0).
AN0 Analog input 0 / VAREF[1] input for ADC0
AN1 Analog input 1 / VAREF[2] input for ADC0
AN2 Analog input 2 / VAREF[3] input for ADC0
AN3 Analog input 3
AN4 Analog input 4
AN5 Analog input 5
AN6 Analog input 6
AN7 Analog input 7
AN8 Analog input 8
AN9 Analog input 9
AN10 Analog input 10
AN11 Analog input 11
AN12 Analog input 12
AN13 Analog input 13
AN14 Analog input 14
AN15 Analog input 15
P7
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P7.8
P7.9
P7.10
P7.11
P7.12
P7.13
P7.14
P7.15
B1
B2
D4
C1
C2
D3
E4
D1
D2
E3
E1
E2
F3
F1
F2
G1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Port 7
Port 7 provides the analog input lines for the AD Converter 1
(ADC1).
AN16 Analog input 16 / VAREF[1] input for ADC1
AN17 Analog input 17 / VAREF[2] input for ADC1
AN18 Analog input 18 / VAREF[3] input for ADC1
AN19 Analog input 19
AN20 Analog input 20
AN21 Analog input 21
AN22 Analog input 22
AN23 Analog input 23
AN24 Analog input 24
AN25 Analog input 25
AN26 Analog input 26
AN27 Analog input 27
AN28 Analog input 28
AN29 Analog input 29
AN30 Analog input 30
AN31 Analog input 31
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 13 V1.2, 2002-05
Preliminary
P8
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
P8.8
P8.9
P8.10
P8.11
P8.12
P8.13
P8.14
P8.15
U23
U20
U22
U21
T23
T22
T21
R23
R20
R22
R21
P23
P22
P21
N20
N23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 8
Port 8 is a 16-bit bidirectional general purpose I/O port which
also serves as input or output for the GPTA.
IN0 / OUT0 line of GPTA
IN1 / OUT1 line of GPTA
IN2 / OUT2 line of GPTA
IN3 / OUT3 line of GPTA
IN4 / OUT4 line of GPTA
IN5 / OUT5 line of GPTA
IN6 / OUT6 line of GPTA
IN7 / OUT7 line of GPTA
IN8 / OUT8 line of GPTA
IN9 / OUT9 line of GPTA
IN10 / OUT10 line of GPTA
IN11 / OUT11 line of GPTA
IN12 / OUT12 line of GPTA
IN13 / OUT13 line of GPTA
IN14 / OUT14 line of GPTA
IN15 / OUT15 line of GPTA
P9
P9.0
P9.1
P9.2
P9.3
P9.4
P9.5
P9.6
P9.7
P9.8
P9.9
P9.10
P9.11
P9.12
P9.13
P9.14
P9.15
N22
N21
M21
M23
M22
L22
L21
L23
L20
K21
K22
K23
J21
J22
J20
J23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 9
Port 9 is a 16-bit bidirectional general purpose I/O port which
also serves as input or output for the GPTA.
IN16 / OUT16 line of GPTA
IN17 / OUT17 line of GPTA
IN18 / OUT18 line of GPTA
IN19 / OUT19 line of GPTA
IN20 / OUT20 line of GPTA
IN21 / OUT21 line of GPTA
IN22 / OUT22 line of GPTA
IN23 / OUT23 line of GPTA
IN24 / OUT24 line of GPTA
IN25 / OUT25 line of GPTA
IN26 / OUT26 line of GPTA
IN27 / OUT27 line of GPTA
IN28 / OUT28 line of GPTA
IN29 / OUT29 line of GPTA
IN30 / OUT30 line of GPTA
IN31 / OUT31 line of GPTA
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 14 V1.2, 2002-05
Preliminary
P10
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P10.8
P10.9
P10.10
P10.11
P10.12
P10.13
P10.14
P10.15
H21
H22
H23
G21
G22
G20
G23
F22
F23
F21
E22
E23
E21
D22
D23
E20
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 10
Port 10 is a 16-bit bidirectional general purpose I/O port
which also serves as input or output for the GPTA.
IN32 / OUT32 line of GPTA
IN33 / OUT33 line of GPTA
IN34 / OUT34 line of GPTA
IN35 / OUT35 line of GPTA
IN36 / OUT36 line of GPTA
IN37 / OUT37 line of GPTA
IN38 / OUT38 line of GPTA
IN39 / OUT39 line of GPTA
IN40 / OUT40 line of GPTA
IN41 / OUT41 line of GPTA
IN42 / OUT42 line of GPTA
IN43 / OUT43 line of GPTA
IN44 / OUT44 line of GPTA
IN45 / OUT45 line of GPTA
IN46 / OUT46 line of GPTA
IN47 / OUT47 line of GPTA
P11
P11.0
P11.1
P11.2
P11.3
P11.4
P11.5
P11.6
P11.7
P11.8
P11.9
P11.10
P11.11
P11.12
P11.13
P11.14
P11.15
C22
C23
C21
B23
A23
A22
B22
D20
A21
B21
C20
D19
A20
B20
C19
A19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 11
Port 11 is a 16-bit bidirectional general purpose I/O port
which also serves as input or output for the GPTA.
IN48 / OUT48 line of GPTA
IN49 / OUT49 line of GPTA
IN50 / OUT50 line of GPTA
IN51 / OUT51 line of GPTA
IN52 / OUT52 line of GPTA
IN53 / OUT53 line of GPTA
IN54 / OUT54 line of GPTA
IN55 / OUT55 line of GPTA
IN56 / OUT56 line of GPTA
IN57 / OUT57 line of GPTA
IN58 / OUT58 line of GPTA
IN59 / OUT59 line of GPTA
IN60 / OUT60 line of GPTA
IN61 / OUT61 line of GPTA
IN62 / OUT62 line of GPTA
IN63 / OUT63 line of GPTA
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 15 V1.2, 2002-05
Preliminary
P12
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7
P12.8
P12.9
P12.10
P12.11
P12.12
P12.13
P12.14
P12.15
D13
A13
B13
C13
C12
A12
B12
B11
C11
A11
D11
C10
B10
A10
C9
B9
I/O
O
O
O
O
O
O
I
I
I
I
I
O
I/O
O
I/O
O
Port 12
Port 12 is a 16-bit bidirectional general purpose I/O port or
serves as ADC control port and SDLM/ASC I/O port.
AD0EMUX0 ADC0 external multiplexer control 0
AD0EMUX1 ADC0 external multiplexer control 1
AD0EMUX2 ADC0 external multiplexer control 2
AD1EMUX0 ADC1 external multiplexer control 0
AD1EMUX1 ADC1 external multiplexer control 1
AD1EMUX2 ADC1 external multiplexer control 2
AD1EXTIN0 ADC1 external trigger input 0
AD1EXTIN1 ADC1 external trigger input 1
AD0EXTIN0 ADC0 external trigger input 0
AD0EXTIN1 ADC0 external trigger input 1
RXJ1850 SDLM receiver input
TXJ1850 SDLM transmitter output
RXD0A ASC0 receiver input/output A
TXD0A ASC0 transmitter output A
RXD1A ASC1 receiver input/output A
TXD1A ASC1 transmitter output A
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 16 V1.2, 2002-05
Preliminary
P13
P13.0
P13.1
P13.2
P13.3
P13.4
P13.5
P13.6
P13.7
P13.8
P13.9
P13.10
P13.11
P13.12
P13.13
P13.14
P13.15
B19
C18
A18
B18
A17
D17
B17
C17
A16
B16
C16
A15
D15
B15
C15
A14
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I
O
Port 13
Port 13 is a 16-bit bidirectional general purpose I/O port that
is also used as input/output for the serial interfaces (ASC,
SSC, CAN) and timers (GPTU).
GPT0 GPTU I/O line 0
GPT1 GPTU I/O line 1
GPT2 GPTU I/O line 2
RXD0B ASC0 receiver input/output B
GPT3 GPTU I/O line 3
TXD0B ASC0 transmitter output B
GPT4 GPTU I/O line 4
RXD1B ASC1 receiver input/output B
GPT5 GPTU I/O line 5
TXD1B ASC1 transmitter output B
GPT6 GPTU I/O line 6
SCLK0 SSC0 clock input/output
GPT7 GPTU I/O line 7
MRST0 SSC0 master receive / slave transmit
input/output
MTSR0 SSC0 master transmit / slave receive
output/input
SCLK1 SSC1 clock input/output
MRST1 SSC1 master receive / slave transmit
input/output
MTSR1 SSC1 master transmit / slave receive
output/input
RXDCAN0 CAN receiver input 0
TXDCAN0 CAN transmitter output 0
RXDCAN1 CAN receiver input 1
TXDCAN1 CAN transmitter output 1
CLKSEL0
CLKSEL1
CLKSEL2
V21
V23
V22
I
I
I
PLL Clock Selection Inputs
These pins are sampled during power-on reset
(PORST = low); they determine the division rate in the
feedback path of the PLL (N-Factor). The latched values of
these input pins are available in the PLL Clock Control
Register PLL_CLC.
The combination BYPASS = 1 and CLKSEL[2:0] = 000B
during power-on reset is reserved.
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 17 V1.2, 2002-05
Preliminary
BYPASS W22 I PLL Bypass Control Input
BYPASS is used for direct drive mode operation of the clock
circuitry. This pin is sampled during power-on reset
(PORST = low). Its level is latched into the PLL Clock
Control Register PLL_CLC. The combination BYPASS = 1
and CLKSEL[2:0] = 000B during power-on reset is reserved.
CFG0
CFG1
CFG2
CFG3
Y23
Y22
W21
W23
I
I
I
I
Operation Configuration Inputs
The configuration inputs define the boot options of the
TC1775 after a hardware reset operation.
TRST3) AA19 I JTAG Module Reset/Enable Input
A low level at this pin resets and disables the JTAG module.
A high level enables the JTAG module.
TCK3) AB19 I JTAG Module Clock Input
TDI4) AC19 I JTAG Module Serial Data Input
TDO AA18 O JTAG Module Serial Data Output
TMS4) AB20 I JTAG Module State Machine Control Input
OCDSE4) Y19 I OCDS Enable Input
A low level on this pin during power-on reset (PORST =low)
enables the on-chip debug support (OCDS). In addition, the
level of this pin during power-on reset determines the boot
configuration.
BRKIN4) AC20 I OCDS Break Input
A low level on this pin causes a break in the chip’s execution
when the OCDS is enabled. In addition, the level of this pin
during power-on reset determines the boot configuration.
BRKOUT AC18 O OCDS Break Output
A low level on this pin indicates that a programmable OCDS
event has occurred.
NMI4) Y20 I Non-Maskable Interrupt Input
A high-to-low transition on this pin causes a NMI-Trap
request to the CPU.
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 18 V1.2, 2002-05
Preliminary
HDRST4) W20 I/O Hardware Reset Input/Reset Indication Output
Assertion of this bidirectional open-drain pin causes a
synchronous reset of the chip through external circuitry. This
pin must be driven for a minimum duration.
The internal reset circuitry drives this pin in response to a
power-on, hardware, watchdog and power-down wake-up
reset for a specific period of time. For a software reset,
activation of this pin is programmable.
PORST5) Y21 I Power-on Reset Input
A low level on PORST causes an asynchronous reset of the
entire chip. PORST is a fully asynchronous level sensitive
signal.
CLKIN T1 I EBU Clock Input
CLKIN must be connected externally with CLKOUT. For fine-
tuning of the external bus interface timing, this external
connection can be an external delay circuit.
CLKOUT R1 O Clock Output
TEST
MODE4) AB23 I Test Mode Select Input
For normal operation of the TC1775, this pin should be
connected to VDDP05.
XTAL1
XTAL2
AC23
AC22
I
O
Oscillator/PLL/Clock Generator Input/Output Pins
XTAL1 is the input to the main oscillator amplifier and input
to the internal clock generator. XTAL2 is the output of the
main oscillator amplifier circuit. For clocking the device from
an external source, XTAL1 is driven with the clock signal
while XTAL2 is left unconnected. For crystal oscillator
operation XTAL1 and XTAL2 are connected to the crystal
with the appropriate recommended oscillator circuitry.
XTAL3
XTAL4
AB21
AA20
I
O
Real Time Clock Oscillator Input/Output
XTAL3 and XTAL4 are the input and the output of the 32 kHz
oscillator that is used for the Real Time Clock.
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 19 V1.2, 2002-05
Preliminary
VDDOSC AC21 – Main Oscillator Power Supply (2.5 V)6)7)
VSSOSC AA21 – Main Oscillator Ground
VDDPLL AA22 – PLL Power Supply (2.5 V)6)7)
VSSPLL AA23 – PLL Ground
VSS F4, Y6,
V20,
D18,
K10
to
K14,
L10
to
L14,
M10
to
M14,
N10
to
N14,
P10
to
P14
–Ground
VDD K4, P4
V4, D6
Y10
D14
Y18
F20
K20
P20
–Core Power Supply (2.5 V)6)7)
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 20 V1.2, 2002-05
Preliminary
VDDP05 H4
M4
T4
Y8
Y12
–Ports 0 to 5 Power Supply (2.5 V)6)7)
VDDP813 D8
D12
D16
H20
M20
T20
–Port 8-13 and Dedicated Pins Power Supply (3.3 to 5 V)8)
VDDSRAM AC17,
AB18
–SRAM (RAMs of DMU, PMU, and PCP) Power Supply
(2.5 V)7)
VDDSB B14 – Stand-by Power Supply of 8 Kbyte SBSRAM (2.5 V)7)
VDDSC A1 – ADC Short Circuit/Broken Wire Logic Power Supply
(5 V)8)
VSSSC A2 – ADC Short Circuit/Broken Wire Logic Ground
VDDM C3 – ADC Analog Part Power Supply (5 V)8)
VSSM A3 – ADC Analog Part Ground
VDDA0 D9 – ADC0 Analog Part Power Supply (2.5 V)6)7)
VSSA0 A9 – ADC0 Analog Part Ground for VDDA0
VDDA1 H1 – ADC1 Analog Part Power Supply (2.5 V)6)7)
VSSA1 G3 – ADC1 Analog Part Ground for VDDA1
VAREF0 C8 – ADC0 Reference Voltage8)
VAGND0 B8 – ADC0 Reference Ground
VAREF1 G2 – ADC1 Reference Voltage8)
VAGND1 G4 – ADC1 Reference Ground
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 21 V1.2, 2002-05
Preliminary
N.C.1 AB15,
D10,
Y14
–Not Connected 1
These pins must not be connected.
N.C.2 AB22,
C14,
K3,
AC3,
L4,
D21,
Y16
–Not Connected 2
For compatibility reasons, these pins should not be
connected. Any connection to 5 V does not harm the device.
1) After reset, an internal pull-up device is enabled for this pin.
2) After reset, an internal pull-down device is enabled for this pin.
3) These pins have an internal pull-down device connected.
4) These pins have an internal pull-up device connected.
5) The TC1775 BA11 step has an internal pull-up device connected to this pin.
6) The voltage on power supply pins marked with 8) has to be raised earlier or at least at the same time as on
power supply pins marked with 6) (details see power supply section on Page 62).
7)