General Description
The MAX1065/MAX1066 14-bit, low-power successive
approximation analog-to-digital converters (ADCs) fea-
ture automatic power-down, a factory-trimmed internal
clock, and a high-speed, 14-bit-wide (MAX1065) or
byte-wide (MAX1066) parallel interface. The devices
operate from a single 4.75V to 5.25V analog supply and
a 2.7V to 5.25V digital supply.
The MAX1065/MAX1066 use an internal 4.096V refer-
ence or an external reference. The MAX1065/MAX1066
consume only 1.8mA at a sampling rate of 165ksps with
external reference and 2.7mA with internal reference.
AutoShutdown™ reduces supply current to 0.1mA at
10ksps.
The MAX1065/MAX1066 are ideal for high-performance,
battery-powered, data-acquisition applications.
Excellent dynamic performance and low-power con-
sumption in a small package make the MAX1065/
MAX1066 the best choice for circuits with demanding
power consumption and space requirements.
The 14-bit-wide MAX1065 is available in a 28-pin TSSOP
package, and the byte-wide MAX1066 is available in a
20-pin TSSOP package. Both devices are available in
either the 0°C to +70°C commercial, or the -40°C to
+85°C extended temperature range.
Applications
Features
o14-Bit-Wide (MAX1065) and Byte-Wide (MAX1066)
Parallel Interface
oHigh Speed: 165ksps Sample Rate
oAccurate: ±1LSB DNL (max), ±1LSB INL (max)
o4.096V, 35ppm/°C Internal Reference
oExternal Reference Range 3.8V to 5.25V
oSingle 4.75V to 5.25V Analog Supply Voltage
o2.7V to 5.25V Digital Supply Voltage
oLow Supply Current
1.8mA (External Reference)
2.7mA (Internal Reference)
0.1mA AutoShutdown Mode (10ksps, External
Reference)
oSmall Footprint
28-Pin TSSOP Package (14-Bit Wide)
20-Pin TSSOP Package (Byte Wide)
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
ANALOG INPUT
D0–D13
EOC
REFADJ
REF
DGNDAGND
RESET
CS
R/C
AIN
AVDD DVDD
MAX1065
0.1μF 0.1μF
5V ANALOG 5V DIGITAL
0.1μF1μF
μP DATA
BUS
Typical Operating Circuit
19-2466; Rev 1; 6/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Pin Configurations appear at end of data sheet.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
PART
TEMP RANGE
PIN-
PACKAGE
INL
MAX1065ACUI 0°C to 70°C
28 TSSOP
±1
MAX1065BCUI 0°C to 70°C
28 TSSOP
±2
MAX1065CCUI 0°C to 70°C
28 TSSOP
±3
MAX1065AEUI
-40°C to +85°C 28 TSSOP
±1
MAX1065BEUI
-40°C to +85°C 28 TSSOP
±2
MAX1065CEUI
-40°C to +85°C 28 TSSOP
±3
MAX1066ACUP
0°C to 70°C
20 TSSOP
±1
MAX1066BCUP
0°C to 70°C
20 TSSOP
±2
MAX1066CCUP
0°C to 70°C
20 TSSOP
±3
MAX1066AEUP
-40°C to +85°C 20 TSSOP
±1
MAX1066BEUP
-40°C to +85°C 20 TSSOP
±2
MAX1066CEUP
-40°C to +85°C 20 TSSOP
±3
Temperature
Sensor/Monitor
Industrial Process
Control
I/O Boards
Data-Acquisition
Systems
Cable/Harness Tester
Accelerometer
Measurements
Digital Signal Processing
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1µF, CREFADJ = 0.1µF, TA= TMIN to TMAX, unless otherwise noted.
Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AIN, REF, REFADJ to AGND....................-0.3V to (AVDD + 0.3V)
CS, HBEN, R/C, RESET to DGND ............................-0.3V to +6V
Digital Output (D13–D0, EOC)
to DGND ..................................................-0.3V to (DVDD + 0.3V)
Maximum Continuous Current Into Any Pin ........................50mA
Continuous Power Dissipation (TA= +70°C)
20-Pin TSSOP (derate 10.9mW/°C above +70°C) .......879mW
28-Pin TSSOP (derate 12.8mW/°C above +70°C) .....1026mW
Operating Temperature Ranges
MAX106_ _CU_...................................................0°C to +70°C
MAX106_ _EU_ ................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution N 14 Bits
MAX106_A ±1
MAX106_B ±2
Relative Accuracy (Note 1) INL
MAX106_C ±3
LSB
Differential Nonlinearity DNL No missing codes over temperature ±1 LSB
Transition Noise RMS noise, includes quantization
noise 0.32 LSBRMS
Offset Error 0.2 1 mV
Gain Error (Note 2) ±0.002 ±0.02 %FSR
Offset Drift 0.6 ppm/°C
Gain Drift 0.2 ppm/°C
DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 1kHz, VIN = 4.096VP-P, 165ksps)
Signal-to-Noise Plus Distortion SINAD 81 84 dB
Signal-to-Noise Ratio SNR 82 84 dB
Total Harmonic Distortion THD -99 -86 dB
Spurious-Free Dynamic Range SFDR 87 102 dB
Full-Power Bandwidth -3dB point 4 MHz
Full-Linear Bandwidth SINAD > 81dB 20 kHz
CONVERSION RATE
Sample Rate fSAMPLE 165 ksps
Aperture Delay 40 ns
Aperture Jitter 100 ps
ANALOG INPUT
Input Range VAIN 0V
REF V
Input Capacitance CAIN 40 pF
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1µF, CREFADJ = 0.1µF, TA= TMIN to TMAX, unless otherwise noted.
Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INTERNAL REFERENCE
REF Output Voltage VREF 4.056 4.096 4.136 V
REF Output Tempco TCREF ±35 ppm/°C
REF Short-Circuit Current IREFSC ±10 mA
Capacitive Bypass at REFADJ CREFADJ 0.1 µF
Capacitive Bypass at REF CREF F
REFADJ Input Leakage Current IREFADJ 20 µA
EXTERNAL REFERENCE
REFADJ Buffer Disable
Threshold To power-down the internal reference AVDD -
0.4
AVDD -
0.1 V
REF Input Voltage Range Internal reference disabled (Note 3) 3.8 AVDD -
0.2 V
VREF = 4.096V, fSAMPLE = 165ksps 14 25
REF Input Current IREF Shutdown mode ±0.1 µA
DIGITAL INPUTS/OUTPUTS (CS, R/C, EOC, D0–D13, RESET, HBEN)
Input High Voltage VIH 0.7 x
DVDD
Input Low Voltage VIL 0.3 x
DVDD
V
Input Leakage Current IIN VIH = 0 or DVDD ±0.1 ±1 µA
Input Hysteresis VHYST 0.1 V
Input Capacitance CIN 15 pF
Output High Voltage VOH ISOURCE = 0.5mA, DVDD = 2.7V to
5.25V, AVDD = 5.25V
DVDD -
0.4 V
Output Low Voltage VOL ISINK = 1.6mA, DVDD = 2.7V to 5.25V,
AVDD = 5.25V 0.4 V
Three-State Leakage Current IOZ D0–D13 ±0.1 ±10 µA
Three-State Output
Capacitance COZ 15 pF
POWER REQUIREMENTS
Analog Supply Voltage AVDD 4.75 5.25 V
Digital Supply Voltage DVDD 2.7 AVDD V
165ksps 3.2 3.6
100ksps 2.6
10ksps 1.9
Internal reference
1ksps 1.8
165ksps 2.4 2.8
100ksps 1.8
10ksps 0.8
Analog Supply Current IAVDD
External reference
1ksps 0.2
mA
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1µF, CREFADJ = 0.1µF, TA= TMIN to TMAX, unless otherwise noted.
Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
165ksps 0.5 0.7
100ksps 0.3
10ksps 0.03
Digital Supply Current IDVDD D0–D13 = all zeros
1ksps 0.003
mA
IAVDD 0.05 5 mA
Full power-down IDVDD 0.5 6 µA
IAVDD 1.0 1.2 mA
Shutdown Supply Current
(Note 4) ISHDN REF and REF
buffer enabled
(standby mode) IDVDD 0.5 5 µA
Power-Supply Rejection Ratio
(Note 5) PSRR AVDD = 5V, ±5%, full-scale input 68 dB
TIMING CHARACTERISTICS (Figures 1 and 2)
(AVDD = 4.75V to 5.25V, DVDD = 2.7V to AVDD, external reference = 4.096V, CREF = 1µF, CREFADJ = 0.1µF, CD13–D0, CEOC = 20pF,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Acquisition Time tACQ 1.1
Conversion Time tCONV 4.7 µs
CS Pulse Width High tCSH (Note 6) 40 ns
VDVDD = 4.75V to 5.25V 40
CS Pulse Width Low tCSL (Note 6) VDVDD = 2.7V to 4.74V 60 ns
R/C to CS Fall Setup Time tDS 0ns
VDVDD = 4.75V to 5.25V 40
R/C to CS Fall Hold Time tDH VDVDD = 2.7V to 5.25V 60 ns
VDVDD = 4.75V to 5.25V 40
CS to Output Data Valid tDO VDVDD = 2.7V to 4.74V 80 ns
VDVDD = 4.75V to 5.25V 40
HBEN Transition To
Output Data Valid
(MAX1066 only)
tDO1
VDVDD = 2.7V to 4.74V 80
ns
EOC Fall To CS Fall tDV 0ns
VDVDD = 4.75V to 5.25V 40
CS Rise To EOC Rise tEOC VDVDD = 2.7V to 4.74V 80 ns
VDVDD = 4.75V to 5.25V 40
Bus Relinquish Time
(Note 6) tBR VDVDD = 2.7V to 4.74V 80 ns
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 2: Offset nulled.
Note 3: Guaranteed by design, not production tested.
Note 4: Maximum specification is limited by automated test equipment.
Note 5: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply.
Note 6: To ensure best performance, finish reading the data and wait tBR before starting a new acquisition.
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
_______________________________________________________________________________________
5
DNL vs. OUTPUT CODE
MAX1065/MAX1066 toc01
OUTPUT CODE
DNL (LSB)
1228881924096
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 16384
INL vs. OUTPUT CODE
MAX1065/MAX1066 toc02
OUTPUT CODE
INL (LSB)
1228881924096
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
-2.0
0 16384
IAVDD + IDVDD SUPPLY CURRENT
vs. SAMPLE RATE
MAX1065/MAX1066 toc03
CONVERSION RATE (ksps)
SUPPLY CURRENT (mA)
1001010.1
0.001
0.01
0.1
1
10
0.0001
0.01 1000
IAVDD + IDVDD SUPPLY CURRENT
vs. TEMPERATURE
MAX1065/MAX1066 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
806040200-20
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
-40
SAMPLE RATE = 165ksps
IAVDD + IDVDD SHUTDOWN CURRENT
vs. TEMPERATURE
MAX1065/MAX1066 toc05
TEMPERATURE (°C)
SHUTDOWN CURRENT (μA)
806040200-20
5.0
0
-40
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
INTERNAL REFERENCE
vs. TEMPERATURE
MAX1065/MAX1066 toc06
TEMPERATURE (°C)
INTERNAL REFERENCE (V)
806040200-20
4.136
4.056
-40
4.066
4.076
4.086
4.096
4.106
4.116
4.126
OFFSET ERROR vs. TEMPERATURE
MAX1065/MAX1066 toc07
TEMPERATURE (°C)
OFFSET ERROR (μV)
806040200-20
1000
0
-40
-800
-600
-400
-200
0
200
400
600
800
GAIN ERROR vs. TEMPERATURE
MAX1065/MAX1066 toc08
TEMPERATURE (°C)
GAIN ERROR (%FSR)
806040200-20
0.020
-0.020
-40
-0.015
-0.010
-0.005
0
0.005
0.010
0.015
SINAD vs. FREQUENCY
MAX1065/MAX1066 toc09
FREQUENCY (kHz)
SINAD (dB)
101
10
20
30
40
50
60
70
80
90
100
0
0.1 100
SAMPLE RATE = 165ksps
Typical Operating Characteristics
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1µF, CREFADJ = 0.1µF, TA = +25°C, unless otherwise noted.)
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1µF, CREFADJ = 0.1µF, TA = +25°C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
MAX1065/MAX1066 toc10
FREQUENCY (kHz)
THD (dB)
101
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
0.1 100
SAMPLE RATE = 165ksps
SPURIOUS-FREE DYNAMIC RANGE
vs. FREQUENCY
MAX1065/MAX1066 toc11
FREQUENCY (kHz)
SFDR (dB)
101.0
10
20
30
40
50
60
70
80
90
100
110
0
0.1 100
SAMPLE RATE = 165ksps
FFT AT 1kHz
MAX1065/MAX1066 toc12
FREQUENCY (kHz)
MAGNITUDE (dB)
604020
-120
-100
-80
-60
-40
-20
0
-140
080
SAMPLE RATE = 165ksps
Pin Description
PIN NAME
MAX1065
MAX1066 MAX1065 MAX1066
FUNCTION
11D6
D4/D12
Three-State Digital Data Output
22D7
D5/D13
Three-State Digital Data Output. D13 is the MSB.
3 3 D8 D6/0 Three-State Digital Data Output
4 4 D9 D7/0 Three-State Digital Data Output
5 D10 Three-State Digital Data Output
6 D11 Three-State Digital Data Output
7 D12 Three-State Digital Data Output
8 D13 Three-State Digital Data Output (MSB)
95 R/C
Read/Convert Input. Power up and put the MAX1065/MAX1066 in acquisition
mode by holding R/C low during the first falling edge of CS. During the
second falling edge of CS the level on R/C determines whether the reference
and reference buffer power down or remain on after conversion. Set R/C high
during the second falling edge of CS to power down the reference and buffer,
or set R/C low to leave the reference and buffer powered up. Set R/C high
during the third falling edge of CS to put valid data on the bus.
10 6 EOC End Of Conversion. EOC drives low when conversion is complete.
11 7 AVDD Analog Supply Input. Bypass with a 0.1µF capacitor to AGND.
12 8 AGND Analog Ground. Primary analog ground (star ground).
13 9 AIN Analog Input
14 10 AGND Analog Ground. Connect Pin 14 to Pin 12 (MAX1065). Connect Pin 10 to Pin 8
(MAX1066).
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
_______________________________________________________________________________________ 7
Pin Description (continued)
PIN NAME
MAX1066 MAX1065 MAX1066
FUNCTION
15 11 REFADJ
Reference Buffer Output. Bypass REFADJ with a 0.1µF capacitor to AGND for
internal reference mode. Connect REFADJ to AVDD to select external
reference mode.
16 12 REF Reference Input/Output. Bypass REF with a 1µF capacitor to AGND for internal
reference mode. External reference input when in external reference mode.
17 RESET Reset Input. Logic high resets the device.
13 HBEN
High Byte-Enable Input. Used to multiplex the 14-bit conversion result.
1: Most significant byte available on the data bus.
0: Least significant byte available on the data bus.
18 14 CS
Convert Start. The first falling edge of CS powers up the device and enables
acquire mode when R/C is low. The second falling edge of CS starts
conversion. The third falling edge of CS loads the result onto the bus when R/C
is high.
19 15 DGND Digital Ground
20 16 DVDD Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.
21 17 N.C. D0/D8 No Connection. Do Not Connect (MAX1065).
Three-State Digital Data Output (MAX1066).
22 18 N.C. D1/D9 No Connection. Do Not Connect (MAX1065).
Three-State Digital Data Output (MAX1066).
23 19 D0
D2/D10
Three-State Digital Data Output
24 20 D1
D3/D11
Three-State Digital Data Output
25 D2 Three-State Digital Data Output
26 D3 Three-State Digital Data Output
27 D4 Three-State Digital Data Output
28 D5 Three-State Digital Data Output
REFERENCE
OUTPUT
REGISTERS
CLOCK
SUCCESSIVE-
APPROXIMATION
REGISTER AND
CONTROL LOGIC
CAPACITIVE
DAC MAX1065
MAX1066
14 OR 8* 14 OR 8*
REFADJ
REF
DGNDAGND
RESET**
AIN
AVDD DVDD
R/C
CS EOC
HBEN*
AGND
D0–D13
OR
D0/D8D5/D13*
*BYTE WIDE (MAX1066 ONLY)
**16-BIT WIDE (MAX1065 ONLY)
5kΩ
Functional Diagram
MAX1065/MAX1066
Detailed Description
Converter Operation
The MAX1065/MAX1066 use a successive-approximation
(SAR) conversion technique with an inherent track-and-
hold (T/H) stage to convert an analog input into a 14-bit
digital output. Parallel outputs provide a high-speed inter-
face to most microprocessors (µPs). The
Functional
Diagram
shows a simplified internal architecture of the
MAX1065/MAX1066. Figure 3 shows a typical application
circuit for the MAX1066.
Analog Input
The equivalent input circuit is shown in Figure 4. A
switched capacitor digital-to-analog converter (DAC)
provides an inherent track-and-hold function. The sin-
gle-ended input is connected between AIN and AGND.
Input Bandwidth
The ADC’s input-tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use antialias filtering.
Internal protection diodes, which clamp the analog
input to AVDD and/or AGND, allow the input to swing
from AGND - 0.3V to AVDD + 0.3V, without damaging
the device.
If the analog input exceeds 300mV beyond the sup-
plies, limit the input current to 10mA.
Track and Hold (T/H)
In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive DAC samples the analog input.
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
8 _______________________________________________________________________________________
CS
R/C REF POWER-
DOWN BIT
EOC
D0–D13
HBEN*
DATA VALID
D7/D13–D0/D8* HIGH/LOW
BYTE VALID
tACQ
tCONV
tCSH
tCSL
tDH
tDO
tDO1
tEOC
*HBEN AND BYTE-WIDE DATA BUS AVAILABLE ON MAX1066 ONLY.
tDS tDV
HI–Z HI-Z
HIGH/LOW
BYTE VALID
tBR
tBR
Figure 2. MAX1065/MAX1066 Timing Diagram
DGND
1mA CLOAD = 20pF
D0–D13 D0–D13
CLOAD = 20pF
1mA
DGND
DVDD
a) HIGH-Z TO VOH,
VOL TO VOH, AND
VOH TO HIGH-Z
b) HIGH-Z TO VOL,
VOH TO VOL, AND
VOL TO HIGH-Z
Figure 1. Load Circuits for D0–D13 Enable Time, CS to D0–D13
Delay Time and Bus Relinquish Time
During the acquisition, the analog input (AIN) charges
capacitor CDAC. The acquisition ends on the second
falling edge of CS. At this instant, the T/H switches
open. The retained charge on CDAC represents a
sample of the input.
In hold mode, the capacitive DAC adjusts during the
remainder of the conversion time to restore node ZERO
to zero within the limits of 14-bit resolution. At the end of
the conversion, force CS low to put valid data on the bus.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is
high, the acquisition time lengthens and more time
must be allowed between conversions. The acquisition
time (tACQ) is the maximum time the device takes to
acquire the signal. Use the following formula to calcu-
late acquisition time:
tACQ = 11(RS+ RIN) x 35pF
where RIN = 800Ω, RS= the input signal’s source
impedance, and tACQ is never less than 1.1µs. A
source impedance less than 1kΩdoes not significantly
affect the ADC’s performance.
To improve the input-signal bandwidth under AC condi-
tions, drive AIN with a wideband buffer (>4MHz) that can
drive the ADC’s input capacitance and settle quickly.
Power-Down Modes
Select standby mode or shutdown mode with the R/C
bit during the second falling edge of CS (see
Selecting
Standby or Shutdown Mode
section). The MAX1065/
MAX1066 automatically enter either standby mode, ref-
erence and buffer on, or shutdown, reference and
buffer off, after each conversion depending on the sta-
tus of R/Cduring the second falling edge of CS.
Internal Clock
The MAX1065/MAX1066 generate an internal conver-
sion clock. This frees the microprocessor from the bur-
den of running the SAR conversion clock. Total
conversion time after entering hold mode (second
falling edge of CS) to end-of-conversion (EOC) falling is
4.7µs (max).
Applications Information
Starting a Conversion
CS and R/Ccontrol acquisition and conversion in the
MAX1065/MAX1066 (Figure 2). The first falling edge of
CS powers up the device and puts it into acquisition
mode if R/Cis low. The convert start is ignored if R/Cis
high. When powering up from shutdown, the MAX1065/
MAX1066 needs at least 10ms (CREFADJ = 0.1µF, CREF
= 1µF) for the internal reference to wake up and settle
before starting the conversion. The ADC may wake up
from shutdown to an unknown state. Put the ADC in a
known state by completing one “dummy” conversion.
The MAX1065/ MAX1066 will be in a known state, ready
for actual data acquisition, after the completion of the
dummy conversion. A dummy conversion consists of one
full conversion cycle.
The MAX1065 provides an alternative reset function to
reset the device (see
RESET
section).
Selecting Standby or Shutdown Mode
The MAX1065/MAX1066 have a selectable standby or
low-power shutdown mode. In standby mode, the
ADC’s internal reference and reference buffer do not
power down between conversions, eliminating the need
to wait for the reference to power up before performing
the next conversion. Shutdown mode powers down the
reference and reference buffer after completing a con-
version. Supply current is greatly reduced when in
shutdown mode. The reference and reference buffer
require a minimum of 10ms (CREFADJ = 0.1µF, CREF =
1µF) to power up and settle from shutdown.
The state of R/Cat the second falling edge of CS
selects which power-down mode the MAX1065/
MAX1066 enters upon conversion completion. Holding
R/Clow causes the MAX1065/MAX1066 to enter stand-
by mode. The reference and buffer are left on after the
conversion completes. R/Chigh causes the
MAX1065/MAX1066 to enter shutdown mode and shut
down the reference and buffer after conversion
(Figures 5 and 6).
When using an external reference, set the REF power-
down bit high for lowest current operation.
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
_______________________________________________________________________________________ 9
ANALOG INPUT
D0–D7 OR
D8–D13
EOC
REFADJ
REF
DGNDAGND
HBEN
CS
R/C
AIN
AVDD DVDD
MAX1066
0.1μF 0.1μF
5V ANALOG 5V DIGITAL
0.1μF1μF
μP DATA
BUS
HIGH
BYTE
LOW
BYTE
Figure 3. Typical Application Circuit for MAX1066
MAX1065/MAX1066
Standby Mode
While in standby mode, the supply current is reduced
to less than 1mA (typ). The next falling edge of CS with
R/Clow causes the MAX1065/MAX1066 to exit standby
mode and begin acquisition. The reference and refer-
ence buffer remain active to allow quick turn-on time.
Standby mode allows significant power savings while
running at the maximum sample rate.
Shutdown Mode
In shutdown mode, the reference and reference buffer
are shut down between conversions. Shutdown mode
reduces supply current to 0.5µA (typ) immediately after
the conversion. The falling edge of CS with R/Clow
causes the reference and buffer to wake up and enter
acquisition mode. To achieve 14-bit accuracy, allow
10ms (CREFADJ = 0.1µF, CREF =F) for the internal
reference to wake up. Increase wakeup time propor-
tionally when using larger values of CREFADJ and CREF.
Internal and External Reference
Internal Reference
The internal reference of the MAX1065/MAX1066 is
internally buffered to provide 4.096V (typ) output at
REF. Bypass REF to AGND and REFADJ to AGND with
1µF and 0.1µF respectively. Fine adjustments can be
made to the internal reference voltage by sinking or
sourcing current at REFADJ. The input impedance at
REFADJ is nominally 5kΩ. The internal reference volt-
age is adjustable to ±1.5% with the circuit of Figure 7.
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the MAX1065/
MAX1066’s internal buffer amplifier. When connecting
an external reference to REFADJ, the input impedance
is typically 5kΩ. Using the buffered REFADJ input
makes buffering the external reference unnecessary;
however, the internal buffer output must be bypassed
at REF with a 1µF capacitor.
Connect REFADJ to AVDD to disable the internal buffer.
Directly drive REF using an external reference. During
conversion, the external reference must be able to
drive 100µA of DC load current and have an output
impedance of 10Ωor less. REFADJ’s impedance is typ-
ically 5kΩ. The DC input impedance of REF is 40kΩ
minimum.
For optimal performance, buffer the reference through
an op amp and bypass REF with a 1µF capacitor.
Consider the MAX1065/MAX1066’s equivalent input
noise (80µVRMS) when choosing a reference.
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
10 ______________________________________________________________________________________
AUTO-ZERO
RAIL
CAPACITIVE DAC
CDAC = 32pF
REF
AGND
TRACK
HOLD
HOLD TRACK
ZERO
RIN
800Ω
AIN
CSWITCH
3pF
Figure 4. Equivalent Input Circuit
CS
R/C
EOC
REF
AND
BUFFER
REF POWER-
DOWN BIT
ACQUISITION CONVERSION DATA
OUT
Figure 5. Selecting Standby Mode
CS
EOC
REF
AND
BUFFER
REF POWER-
DOWN BIT
ACQUISITION CONVERSION DATA
OUT
R/C
Figure 6. Selecting Shutdown Mode
Reading the Conversion Result
EOC is provided to flag the microprocessor when a con-
version is complete. The falling edge of EOC signals
that the data is valid and ready to be output to the bus.
D0–D13 are the parallel outputs of the MAX1065/
MAX1066. These three-state outputs allow for direct
connection to a microcontroller I/O bus. The outputs
remain high-impedance during acquisition and conver-
sion. Data is loaded onto the bus with the third falling
edge of CS with R/Chigh after tDOns. Bringing CS high
forces the output bus back to high-impedance. The
MAX1065/MAX1066 then waits for the next falling edge
of CS to start the next conversion cycle (Figure 2).
The MAX1065 loads the conversion result onto a 14-bit-
wide data bus while the MAX1066 has a byte-wide out-
put format. HBEN toggles the output between the
most/least significant byte. The least significant byte is
loaded onto the output bus when HBEN is low and the
most significant byte is on the bus when HBEN is high
(Figure 2).
RESET
Toggle RESET with CS high. The next falling edge of
CS will begin acquisition. This reset is an alternative to
the dummy conversion explained in the
Starting a
Conversion
section.
Transfer Function
Figure 8 shows the MAX1065/MAX1066 output transfer
function. The output is coded in standard binary.
Input Buffer
Most applications require an input buffer amplifier to
achieve 14-bit accuracy. If the input signal is multiplexed,
the input channel should be switched immediately after
acquisition, rather than near the end of or after a conver-
sion. This allows more time for the input buffer amplifier to
respond to a large step-change in input signal. The input
amplifier must have a high enough slew rate to complete
the required output voltage change before the beginning
of the acquisition time. At the beginning of acquisition, the
internal sampling capacitor array connects to AIN (the
amplifier output) causing some output disturbance.
Ensure that the sampled voltage has settled to within the
required limits before the end of the acquisition time. If
the frequency of interest is low, AIN can be bypassed
with a large enough capacitor to charge the internal sam-
pling capacitor with very little ripple. However, for AC use,
AIN must be driven by a wideband buffer (at least
10MHz), which must be stable with the ADC’s capacitive
load (in parallel with any AIN bypass capacitor used) and
also settle quickly. An example of this circuit using the
MAX4434 is given in Figure 9.
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
______________________________________________________________________________________ 11
5V
68kΩ
100kΩ
150kΩ0.22μF
REFADJ
MAX1065
MAX1066
Figure 7. MAX1065/MAX1066 Reference Adjust Circuit
ANALOG
INPUT
10Ω
40pF
AIN
MAX1065/
MAX1066
MAX4434
Figure 9. MAX1065/MAX1066 Fast Settling Input Buffer
OUTPUT CODE
FULL-SCALE
TRANSITION
11...111
123
0FS
FS - 3/2LSB
FS = VREF
INPUT VOLTAGE (LSB)
1LSB = VREF
16384
11...110
11...101
00...011
00...010
00...001
00...000
Figure 8. MAX1065/MAX1066 Transfer Function
MAX1065/MAX1066
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Do not
run analog and digital lines parallel to each other, and do
not lay out digital signal paths underneath the ADC pack-
age. Use separate analog and digital ground planes with
only one point connecting the two ground systems (ana-
log and digital) as close to the device as possible.
Route digital signals far away from sensitive analog and
reference inputs. If digital lines must cross analog lines,
do so at right angles to minimize coupling digital noise
onto the analog lines. If the analog and digital sections
share the same supply, then isolate the digital and ana-
log supply by connecting them with a low-value (10Ω)
resistor or ferrite bead.
The ADC is sensitive to high-frequency noise on the AVDD
supply. Bypass AVDD to AGND with a 0.1µF capacitor in
parallel with a 1µF to 10µF low-ESR capacitor and the
smallest capacitor closest to the device. Keep capacitor
leads short to minimize stray inductance.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1065/MAX1066
are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of 1LSB guarantees no missing
codes and a monotonic transfer function.
Aperture Jitter and Delay
Aperture jitter is the sample-to-sample variation in the
time between samples. Aperture delay is the time
between the rising edge of the sampling clock and the
instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s res-
olution (N-bits):
SNR = (6.02 x N + 1.76)dB
where N = 14 bits.
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V1 is the fundamental amplitude and V2through
V5are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest fre-
quency component.
Chip Information
TRANSISTOR COUNT: 15,140
PROCESS: BiCMOS
THD
VVVV
V
+++
20
22324252
1
log
ENOB SINAD
=176
602
.
.
SINAD dB Signal
Noise Distortion
RMS
RMS
( ) log ()
+
20
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
12 ______________________________________________________________________________________
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
______________________________________________________________________________________ 13
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D5
D4
D3
D2
D1
D0
REFADJ
N.C.
N.C.
DVDD
DGND
CS
RESET
REF
AGND
AIN
AGND
AVDD
EOC
R/C
D13
D12
D11
D10
D9
D8
D7
D6
TSSOP
TOP VIEW
MAX1065
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
D3/D11
D2/D10
D1/D9
D0/D8D7/0
D6/0
D5/D13
D4/D12
DVDD
DGND
CS
HBENAGND
AVDD
EOC
R/C
12
11
9
10
REF
REFADJAGND
AIN
MAX1066
TSSOP
Pin Configurations
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
28 SSOP U28-1 21-0066
20 SSOP U20-2 21-0066
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 4/02 Initial release
1 6/09 Modified specifications to include reference buffer 3, 4