74ABT240CMSA - Fairchild Semiconductor

March 1994

Revised November 1999

74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs

74ABT240

Octal Buf f e r/L ine Driv e r wit h 3- S TATE Ou tputs

General Description

The ABT240 is an inverting octal buffer and line driver

designed to be employed as a memory address driver,

clock drive r and bu s oriented transmitter or receive r which

provide s imp rov ed PC boa rd density.

Features

■Output sink capability of 64 mA, source capability of

32 mA

■Guaranteed latchup protec tion

■High impedance glitch free bus loading during entire

power up and power down cycle

■Nondestructive hot insertion capability

Ordering Code:

Device a ls o av ailable in Tape and R eel. Specify by appending s uffix let te r “X” to the or dering code.

Connection Diagram Pin Descriptions

Truth Tables

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immateria l

Z = High Impedance

Order Number Package Number Package Description

74ABT240CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

74ABT240CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ABT240CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

74ABT240CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names Description

OE1, OE23-STATE Output

Enable Inputs

I0–I7Inputs

O0–O7Outputs

Inputs Outputs

(Pins 12, 14, 16, 18)

OE1In

LL H

LH L

HX Z

Inputs Outputs

(Pins 3, 5, 7, 9)

OE2In

LL H

LH L

HX Z

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74ABT240

Absolute Maximum Ratings(No te 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation

under th es e conditi ons is not im plied.

Note 2: Eith er v oltage lim it or c urrent limit is sufficien t to prot ect inputs .

DC Electrical Characteristics

Note 3: Guaranteed, but not tested.

Note 4: For 8 bits toggling, ICCD < 0.8 mA/ M H z .

Storage Temperature −65°C to +150°C

Junction Temperature under Bias −55°C to +150°C

VCC Pin Potential to Ground Pin −0.5V to +7.0V

Input Voltage (Note 2) −0.5V to +7.0V

Input Curr en t (Note 2) −30 mA to +5.0 mA

Voltage Applied to Any Output

in the Disab led or

Power-Off State −0.5V to 5.5V

in the HIGH State −0.5V to VCC

Current Applied to Output

in LOW State (Max) twice the rated IOL (mA)

DC Latchup Source Current

(Across Comm Operating Range) −150 mA

Over Voltage Latchup (I/O) 10V

Free Air Ambient Temperature −40°C to +85°C

Supply Voltage +4.5V to +5.5V

Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns

Enable Input 20 mV/ns

Symbol Parameter Min Typ Max Units VCC Conditions

VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized LOW Signal

VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

VOH Output HIGH Voltage 2.5 V Min IOH = −3 mA

2.0 V Min IOH = −32 mA

VOL Output LOW Voltage 0.55 V Min IOL = 64 mA

IIH Input HIGH Current 1 µAMax

VIN = 2.7V (Note 3)

IN = VCC

IBVI Input HIGH Current Breakdown Test 7 µAMaxV

IN = 7.0V

IIL Input LOW Current −1µAMax

VIN = 0.5V (Note 3)

−1V

IN = 0.0V

VID Input Leakage Test 4.75 V 0.0 IID = 1.9 µA

All Other Pins Grounded

IOZH Output Leakage Current 10 µA0 − 5.5V VOUT = 2.7V; OEn = 2.0V

IOZL Output Leakage Current −10 µA0 − 5.5V VOUT = 0.5V; OEn = 2.0V

IOS Output Short-Circuit Current −100 −275 mA Max VOUT = 0.0V

ICEX Output HIGH Leakage Current 50 µAMaxV

OUT = VCC

IZZ Bus Drainage Test 100 µA0.0V

OUT = 5.5V; All Others GND

ICCH Power Supply Current 50 µA Max All Outputs HIGH

ICCL Power Supply Current 30 mA Max All Outputs LOW

ICCZ Power Supply Current 50 µAMax

OEn = VCC;

All Others at VCC or Ground

ICCT Additional ICC/Input Outputs Enabled 1.5 mA

Max

VI = VCC − 2.1V

Outputs 3-STATE 1.5 mA Enable Input VI = VCC − 2.1V

Outputs 3-STATE 50 µA Data Input VI = VCC − 2.1V

All Others at VCC or Ground

ICCD Dynamic ICC No Load mA/

Max

Outputs Open

(Note 3) 0.1 MHz OEn = GND, (Note 4)

One Bit Toggling, 50% Duty Cycle

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74ABT240

AC Electrical Characteristics

Capacitance

Note 5: COUT is meas ured at freq uency f = 1 MHz, per MIL-STD-883, Method 3012.

TA = +25°CT

A = −55°C to +125°CT

A = −40°C to +85°C

VCC = +5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V

Symbol Parameter CL = 50 pF CL = 50 pF CL = 50 pF Units

Min Typ Max Min Max Min Max

tPLH Propagation Delay 1.0 4.8 0.8 5.5 1.0 4.8 ns

tPHL Data to Outputs 1.6 4.8 1.0 5.5 1.6 4.8

tPZH Output Enable 1.1 6.2 0.8 7.5 1.1 6.2 ns

tPZL Time 1.1 6.2 0.8 7.7 1.1 6.2

tPHZ Output Disable 1.8 6.4 1.0 7.5 1.8 6.4 ns

tPLZ Time 1.6 5.8 1.0 7.2 1.6 5.8

Symbol Parameter Typ Units Conditions

TA = 25°C

CIN Input Capacitance 5.0 pF VCC = 0V

COUT (Note 5) Output Capacitance 9.0 pF VCC = 5.0V

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74ABT240

AC Loading

*Inclu des jig an d probe capacitan c e

Standard AC Test Load Test Input Signal Levels

Test Input Signal Requirements

AC W aveforms

Propagation Delay,

Pulse Width Waveforms

3-STAT E Output HIGH

and LOW Enable and Disable Times

Propagation Delay Waveforms for

Inverting and Non-Inverting Functions

Setup Time, Hold Time

and Recovery Time Waveforms

Amplitude Rep. Rate tWtrtf

3.0V 1 MHz 500 ns 2.5 ns 2.5 ns

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74ABT240

Physical Dim ensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

Package Number M20B

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74ABT240

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Sma ll Outline Package (SOP ), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74ABT240

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

Package Number MSA20

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74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syste ms are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a lif e supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa ilure of the lif e su pp ort

device or system, or to affect its safety or effectiveness.