PowerSSO-16
Features
Max transient supply voltage VCC 40 V
Operating voltage range VCC 4 to 28 V
Typ. on-state resistance (per Ch) RON 100 mΩ
Current limitation (typ) ILIMH 15 A
Stand-by current (max) ISTBY 0.5 µA
Minimum cranking supply Voltage (VCC decreasing) VUSD_cranking 2.85 V
• AEC-Q100 qualified
• Extreme low voltage operation for deep cold cranking applications (compliant
with LV124, revision 2013)
• General
– Quad channel smart high-side driver with CurrentSense analog feedback
– Very low standby current
– Compatible with 3 V and 5 V CMOS outputs
• CurrentSense diagnostic functions
– Analog feedback of load current with high precision proportional current
mirror
– Overload and short to ground (power limitation) indication
– Thermal shutdown indication
– OFF-state open-load detection
– Output short to VCC detection
– Sense enable/disable
• Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Configurable latch-off on overtemperature or power limitation
– Loss of ground and loss of VCC
– Reverse battery with external components
– Electrostatic discharge protection
Applications
• Automotive resistive, inductive and capacitive loads
• Protected supply for ADAS systems: radars and sensors
• Automotive lamps
Product status
VNQ7E100AJ
Product summary
Order code VNQ7E100AJTR
Package PowerSSO-16
Packing Tape and reel
Quad channel high-side driver with CurrentSense analog feedback for automotive
applications
VNQ7E100AJ
Datasheet
DS12570 - Rev 3 - February 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
Description
The device is a quad channel high-side driver manufactured using ST proprietary
VIPower® M0-7 technology and housed in a PowerSSO-16 package. The device is
designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-
compatible interface, providing protection and diagnostics.
The device integrates advanced protective functions such as load current limitation,
overload active management by power limitation and overtemperature shutdown with
configurable latch-off.
A FaultRST pin unlatches the output in case of fault or disables the latch-off
functionality.
A multiplexed current sense pin delivers high precision proportional load current
sense in addition to the detection of overload and short circuit to ground, short to VCC
and off-state openload.
A sense enable pin allows OFF-state diagnosis to be disabled during the module low-
power mode as well as external sense resistor sharing among similar devices.
VNQ7E100AJ
DS12570 - Rev 3 page 2/45
1Block diagram and pin description
Figure 1. Block diagram
VCC
V
0
MUX
0
V
T
V
0
SEL0
SEn
1
1
2
INPUT3
2
3
SEL1
Sense
Current
Limitation
Current
– OUT
CC
Clamp
Gate Driver
Power Limitation
Overtemperature
Short to VCC
Open-Load in OFF
Channel 0
Control & Diagnostic
Channel 1
Channel 2
Channel 3
shut-down
Undervoltage
Internal supply
– GND
Clamp
CC
FaultRST
INPUT
INPUT
INPUT
GND SENSEH
Fault
CS
OUTPUT
OUTPUT
OUTPUT
OUTPUT
CH 1
CH 2
CH 3
CH 0
GADG1003171112PS
Table 1. Pin functions
Name Function
VCC Battery connection.
OUTPUT0,1,2,3 Power output.
GND Ground connection. Must be reverse battery protected by an external diode / resistor network.
INPUT0,1,2,3 Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. They control output
switch state.
CS Analog current sense output pin delivers a current proportional to the load current.
SEn Active high, compatible with 3 V and 5 V CMOS outputs input pin; it enables the CS diagnostic pin.
SEL0,1 Active high, compatible with 3 V and 5 V CMOS outputs input pin; They address the CS multiplexer.
FaultRST Active low, compatible with 3 V and 5 V CMOS outputs input pin; it unlatches the output in case of fault; If
kept low, sets the outputs in auto-restart mode.
VNQ7E100AJ
Block diagram and pin description
DS12570 - Rev 3 page 3/45
Figure 2. Configuration diagram (top view)
1
2
3
4
5
6INPUT2
INPUT0
SEL1
7
8
INPUT1
INPUT3
16
15
14
13
12
11
OUTPUT1
N.C.
10
9
SEL0
OUTPUT2
OUTPUT3
SEn
CS
FaultRST
OUTPUT0
TAB = VCC
PowerSSO-16
GAPGCFT00632
N.C.
GND
Table 2. Suggested connections for unused and not connected pins
Connection / pin CS N.C. Output Input SEn, SELx, FaultRST
Floating Not allowed X (1) X X X
To ground Through 1 kΩ resistor X Not allowed Through 15 kΩ resistor Through 15 kΩ resistor
1. X: do not care.
VNQ7E100AJ
Block diagram and pin description
DS12570 - Rev 3 page 4/45
2Electrical specification
Figure 3. Current and voltage conventions
VIN
OUTPUT0,1,2,3
CS
FaultRST
SEn
SEL0,1
INPUT0,1,2,3
IIN
ISEL
ISEn
IFR
IGND
VSENSE
VOUT
VCC
VFn
IS
IOUT
ISENSE
VCC
VSEL
VSEn
VFR
GADG0704171646PS
Note: VFn = VOUTn - VCC during reverse battery condition.
2.1 Absolute maximum ratings
Stressing the device above the rating listed in Table 3. Absolute maximum ratings may cause permanent damage
to the device. These are stress ratings only and operation of the device at these or any other conditions above
those indicated in the operating sections of this specification is not implied. Exposure to the conditions in the table
below for extended periods may affect device reliability.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage 38
V
-VCC Reverse DC supply voltage 0.3
VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40 V; RL = 4 Ω) 40 V
VCCJS Maximum jump start voltage for single pulse short circuit protection 28 V
-IGND DC reverse ground pin current 200 mA
IOUT OUTPUT0,1,2,3 DC output current Internally limited
A
-IOUT Reverse DC output current 7.5
IIN INPUT0,1,2,3 DC input current
-1 to 10 mA
ISEn SEn DC input current
ISEL SEL0,1 DC input current
IFR FaultRST DC input current -1 to 1.5 mA
ISENSE
CS pin DC output current
(VGND = VCC and VSENSE < 0 V) 10
mA
CS pin DC output current in reverse (VCC < 0 V) -20
VNQ7E100AJ
Electrical specification
DS12570 - Rev 3 page 5/45
Symbol Parameter Value Unit
EMAX
Maximum switching energy (single pulse)
(TDEMAG = 0.4 ms; Tjstart = 150°C) 10 mJ
VESD
JEDEC standard (Electrostatic discharge) JEDEC 22A-114F
INPUT0,1,2,3 4000
V
CS, SEn 2000
SEL0,1, FaultRST 4000
OUTPUT0,1,2,3 4000
VCC 4000
VESD Charge device model (CDM-AEC-Q100-011) 750 V
TjJunction operating temperature -40 to 150
°C
Tstg Storage temperature -55 to 150
2.2 Thermal data
Table 4. Thermal data
Symbol Parameter Typ. value Unit
Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8) (1)(2) 7.7
°C/W
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-5) (1)(3) 60.3
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-7) (1)(2) 27.1
Rthj-top Thermal resistance junction-top (JEDEC JESD 51-7)(1)(2) 13.5
1. One channel ON.
2. Device mounted on four-layers 2s2p PCB.
3. Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace.
VNQ7E100AJ
Thermal data
DS12570 - Rev 3 page 6/45
2.3 Main electrical characteristics
7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
Table 5. Electrical characteristics during cranking
Symbol Parameter Test conditions Min. Typ. Max. Unit
VUSD_Cranking
Minimum cranking supply
voltage (VCC decreasing) 2.85 V
RON On-state resistance (1) IOUT = 0.2 A; VCC = 2.85 V; VCC
decreasing 300 mΩ
TTSD (2) Shutdown temperature (VCC
decreasing) VCC =2.85 V 140 °C
1. For each channel.
2. Parameter guaranteed by design and characterization; not subject to production test.
Table 6. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC Operating supply voltage 4 13 28
V
VUSD Undervoltage shutdown 2.85
VUSDReset Undervoltage shutdown reset 5
VUSDhyst Undervoltage shutdown
hysteresis 0.3
RON On-state resistance (1)
IOUT = 1 A; Tj = 25°C 100
mΩ
IOUT = 1 A; Tj = 150°C 210
IOUT = 1 A; VCC = 4 V; Tj = 25°C (2) 160
Vclamp Clamp voltage
IS = 20 mA; 25°C < Tj < 150°C 41 46 52
V
IS = 20 mA; Tj = -40°C 38
ISTBY
Supply current in Standby at
VCC = 13 V (3)
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 25°C
0.5 µA
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 85°C (4)
0.5 µA
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 125°C
3 µA
tD_STBY Standby mode blanking time
VCC = 13 V
VIN = VOUT = VFR = VSEL0,1 = 0 V;
VSEn = 5 V to 0 V
60 300 550 µs
IS(ON) Supply current VCC = 13 V; VSEn = VFR = VSEL0,1 = 0 V;
VIN0,1,2,3 = 5 V; IOUT0,1,2,3 = 0 A 10 16 mA
IGND(ON)
Control stage current
consumption in ON state. All
channels active.
VCC = 13 V; VSEn = 5 V;
VFR = VSEL0,1 = 0 V; VIN0,1,2,3 = 5 V;
IOUT0,1,2,3 = 1 A
20 mA
VNQ7E100AJ
Main electrical characteristics
DS12570 - Rev 3 page 7/45
Symbol Parameter Test conditions Min. Typ. Max. Unit
IL(off)
Off-state output current at
VCC = 13 V (1)
VIN = VOUT = 0 V; VCC = 13 V; Tj = 25°C 0 0.01 0.5
µA
VIN = VOUT = 0 V; VCC = 13 V; Tj = 125°C 0 3
VF
Output - VCC diode voltage at
Tj = 150°C IOUT = -1 A; Tj = 150°C 0.7 V
1. For each channel.
2. Parameter guaranteed only at Vcc = 4 V and Tj = 25 °C
3. PowerMOS leakage included.
4. Parameter specified by design; not subject to production test.
Table 7. Switching
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) (1) Turn-on delay time at
Tj = 25°C
RL = 13 Ω
10 50 120
µs
td(off) (1) Turn-off delay time at
Tj = 25°C 10 35 100
(dVOUT/dt)on (1) Turn-on voltage slope at
Tj = 25°C
RL = 13 Ω
0.1 0.3 0.7
V/µs
(dVOUT/dt)off (1) Turn-off voltage slope at
Tj = 25°C 0.1 0.4 0.7
WON
Switching energy losses at
turn-on (twon)RL = 13 Ω — 0.15 0.5 (2) mJ
WOFF
Switching energy losses at
turn-off (twoff)RL = 13 Ω — 0.1 0.5(2) mJ
tSKEW (1) Differential Pulse skew
(tPHL - tPLH)RL = 13 Ω -65 -15 35 µs
1. See Figure 6. Switching times and Pulse skew.
2. Parameter guaranteed by design and characterization, not subject to production test
Table 8. Logic Inputs
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
INPUT0,1,2,3 characteristics
VIL Input low level voltage 0.9 V
IIL Low level input current VIN = 0.9 V 1 µA
VIH Input high level voltage 2.1 V
IIH High level input current VIN = 2.1 V 10 µA
VI(hyst) Input hysteresis voltage 0.2 V
VICL Input clamp voltage
IIN = 1 mA 5.3 7.2
V
IIN = -1 mA -0.7
FaultRST characteristics
VFRL Input low level voltage 0.9 V
VNQ7E100AJ
Main electrical characteristics
DS12570 - Rev 3 page 8/45
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
IFRL Low level input current VIN = 0.9 V 1 µA
VFRH Input high level voltage 2.1 V
IFRH High level input current VIN = 2.1 V 10 µA
VFR(hyst) Input hysteresis voltage 0.2 V
VFRCL Input clamp voltage
IIN = 1 mA 5.3 7.5
V
IIN = -1 mA -0.7
SEL0,1 characteristics (7 V < VCC < 18 V)
VSELL Input low level voltage 0.9 V
ISELL Low level input current VIN = 0.9 V 1 µA
VSELH Input high level voltage 2.1 V
ISELH High level input current VIN = 2.1 V 10 µA
VSEL(hyst) Input hysteresis voltage 0.2 V
VSELCL Input clamp voltage
IIN = 1 mA 5.3 7.2
V
IIN = -1 mA -0.7
SEn characteristics (7 V < VCC < 18 V)
VSEnL Input low level voltage 0.9 V
ISEnL Low level input current VIN = 0.9 V 1 µA
VSEnH Input high level voltage 2.1 V
ISEnH High level input current VIN = 2.1 V 10 µA
VSEn(hyst) Input hysteresis voltage 0.2 V
VSEnCL Input clamp voltage
IIN = 1 mA 5.3 7.2
V
IIN = -1 mA -0.7
Table 9. Protections
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
ILIMH DC short circuit current
VCC = 13 V 11 15 22
A
4 V < VCC < 18 V (1) 22
ILIML Short circuit current during
thermal cycling VCC = 13 V; TR < Tj < TTSD 6
TTSD Shutdown temperature 150 175 200
°C
TRReset temperature(1) TRS + 1 TRS + 7
TRS Thermal reset of fault
diagnostic indication VFR = 0 V; VSEn = 5 V; 135
THYST
Thermal hysteresis (TTSD -
TR)(1) 7
ΔTJ_SD Dynamic temperature Tj = -40°C; VCC = 13 V 60 K
VNQ7E100AJ
Main electrical characteristics
DS12570 - Rev 3 page 9/45
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
tLATCH_RST Fault reset time for output
unlatch(1)
VFR = 5 V to 0 V; VSEn = 5 V
• E.g. Ch0
VIN0 = 5 V; VSEL0,1 = 0 V
3 10 20 µs
VDEMAG Turn-off output voltage clamp
IOUT= 1 A; L = 6 mH; Tj = -40°C VCC - 38 V
IOUT= 1 A; L = 6 mH; Tj = 25°C to 150°C VCC - 41 VCC - 46 VCC - 52 V
1. Parameter guaranteed by design and characterization; not subject to production test.
Table 10. CurrentSense
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSENSE_CL Current sense clamp voltage
VSEn = 0 V; ISENSE = 1 mA -17 -12
V
VSEn = 0 V; ISENSE = -1 mA 7
Current Sense characteristics
K0IOUT/ISENSE
IOUT = 0.025 A; VSENSE = 0.5 V;
VSEn = 5 V -30% 710 +30%
dK0/K0 (1) (2) Current sense ratio drift IOUT = 0.025 A; VSENSE = 0.5 V;
VSEn = 5 V -20 +20 %
K1IOUT/ISENSE IOUT = 0.15 A; VSENSE = 4 V; VSEn = 5 V -15% 710 +15%
dK1/K1 (1) (2) Current sense ratio drift IOUT = 0.15 A; VSENSE = 4 V; VSEn = 5 V -10 +10 %
K2IOUT/ISENSE IOUT = 0.7 A; VSENSE = 4 V; VSEn = 5 V -7% 710 +7%
dK2/K2 (1) (2) Current sense ratio drift IOUT = 0.7 A; VSENSE = 4 V; VSEn = 5 V -6 +6 %
K3IOUT/ISENSE IOUT = 2 A; VSENSE = 4 V; VSEn = 5 V -7% 710 +7%
dK3/K3 (1) (2) Current sense ratio drift IOUT = 2 A; VSENSE = 4 V; VSEn = 5 V -6 +6 %
ISENSE_OL CS current for OL detection IOUT = 0.01 A; VSENSE = 4 V; VSEn = 5 V 24 µA
ISENSE0 Current sense leakage
current
Current sense disabled: VSEn = 0 V; 0 0.5
µA
Current sense disabled:
-1 V < VSENSE < 5 V(1) -0.5 0.5
Current sense enabled: VSEn = 5 V All
channels ON; IOUTX = 0 A;
ChX diagnostic selected:
• E.g. Ch0:
VIN0,1,2,3 = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; IOUT0 = 0 A;
IOUT1,2,3 = 1 A
0 10
Current sense enabled: VSEn = 5 V; ChX
OFF;
ChX diagnostic selected:
• E.g. Ch0:
VIN0 = 0 V; VIN1,2,3 = 5 V; VSEL0 = 0
V; VSEL1 = 0 V; IOUT1,2,3 = 1 A
0 2
VNQ7E100AJ
Main electrical characteristics
DS12570 - Rev 3 page 10/45
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
VOUT_MSD (1) Output Voltage for Current
sense shutdown
VSEn = 5 V; RSENSE = 2.7 kΩ
• E.g. Ch0:
VIN0 = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; IOUT0 = 1 A
5 V
VSENSE_SAT CS saturation voltage
VCC = 7 V; RSENSE = 2.7 kΩ; VSEn = 5 V;
VIN0 = 5 V; VSEL0,1 = 0 V; IOUT0 = 2 A;
Tj = -40 °C
4.8 V
ISENSE_SAT (1) CS saturation current VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V;
VSEn = 5 V; VSEL0,1 = 0 V; Tj = 150 °C 4 mA
IOUT_SAT (1) Output saturation current VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V;
VSEn = 5 V; VSEL0,1 = 0 V; Tj = 150 °C 3.1 A
OFF-state diagnostic
VOL OFF-state open-load voltage
detection threshold
VSEn = 5 V; ChX OFF; ChX diagnostic
selected
• E.g: Ch0
VIN0 = 0 V; VSEL0,1 = 0 V
2 3 4 V
IL(off2) (3) OFF-state output sink current
VIN = 0 V; VOUT = VOL;
Tj = -40°C to 125°C -100 -15 µA
tDSTKON
OFF-state diagnostic delay
time from falling edge of
INPUT (see
Figure 8. TDSKON )
VSEn = 5 V; ChX ON to OFF transition;
ChX diagnostic selected:
• E.g: Ch0
VIN0 = 5 V to 0 V; VSEL0,1 = 0 V;
VOUT0 = 4 V; IOUT0 = 0 A
100 350 700 µs
tD_OL_V
Settling time for valid OFF-
state open-load diagnostic
indication from rising edge of
SEn
VIN0,1,2,3 = 0 V; VFR = 0 V; VSEL0,1 = 0 V;
VOUT0 = 4 V; VSEn = 0 V to 5 V 60 µs
tD_VOL
OFF-state diagnostic delay
time from rising edge of VOUT
VSEn = 5 V; ChX OFF;
ChX diagnostic selected:
• E.g: Ch0
VIN0 = 0 V; VSEL0,1 = 0 V;
VOUT0 = 0 V to 4 V
5 30 µs
Fault diagnostic feedback (see Table 11. Truth table)
VSENSEH Current sense output voltage
in fault condition
VCC = 13 V; RSENSE = 1 kΩ
• E.g: Ch0 in open load
VIN0 = 0 V; VSEn = 5 V;
VSEL0,1 = 0 V; IOUT0 = 0 A;
VOUT0 = 4 V
5 6.6 V
ISENSEH Current sense output current
in fault condition VCC = 13 V; VSENSE = 5 V 7 20 30 mA
Current sense timings (current sense mode - see Figure 7. Current sense timings (current sense mode))(4)
tDSENSE1H Current sense settling time
from rising edge of SEn
VIN = 5 V; VSEn = 0 V to 5 V;
RSENSE = 1 kΩ; RL = 6.5 Ω 60 µs
tDSENSE1L Current sense disable delay
time from falling edge of SEn
VSEn = 5 V to 0 V; RSENSE = 1 kΩ;
RL = 6.5 Ω 5 20 µs
VNQ7E100AJ
Main electrical characteristics
DS12570 - Rev 3 page 11/45
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
tDSENSE2H Current sense settling time
from rising edge of INPUT
VIN = 0 V to 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 6.5 Ω 100 250 µs
ΔtDSENSE2H
Current sense settling time
from rising edge of IOUT
(dynamic response to a step
change of IOUT)
VIN = 5 V; VSEn = 5 V; RSENSE = 1 kΩ;
ISENSE = 90 % of ISENSEMAX; RL = 6.5 Ω 100 µs
tDSENSE2L
Current sense turn-off delay
time from falling edge of
INPUT
VIN = 5 V to 0 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 6.5 Ω 50 250 µs
Current sense timings (Multiplexer transition times) (4)
tD_XtoY
Current sense transition delay
from ChX to ChY
VIN0 = 5 V; VIN1 = 5 V; VSEn = 5 V; VSEL1
= 0 V; VSEL0 = 0 V to 5 V; IOUT0 = 0 A;
IOUT1 = 1 A; RSENSE = 1 kΩ
20 µs
tD_CStoVSENSEH
Current sense transition delay
from stable current sense on
ChX to VSENSEH on ChY
VIN0 = 5 V; VIN1 = 0 V; VSEn = 5 V; VSEL1
= 0 V; VSEL0 = 0 V to 5 V; IOUT0 = 1 A;
VOUT1 = 4 V; RSENSE = 1 kΩ
20 µs
1. Parameter defined by design. Not subject to production test.
2. All values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
3. Parameter granted at -40 °C < Tj < 125 °C"
4. Transition delay are measured up to +/- 10% of final conditions.
Figure 4. IOUT/ISENSE versus IOUT
GADG0903171157PS
0
200
400
600
800
1000
1200
0 1 2 3
K-factor
IOUT[A]
Max
Min
Typ
VNQ7E100AJ
Main electrical characteristics
DS12570 - Rev 3 page 12/45
Figure 5. Current sense accuracy versus IOUT
GADG0903171216PS
0
5
10
15
20
25
30
35
40
45
50
0 1 2 3
%
IOUT [A]
Current sense uncalibrated precision
Current sense calibrated precision
Figure 6. Switching times and Pulse skew
VOUT
t
Vcc
twon
80% Vcc
20% Vcc
twoff
INPUT
td(on)
tpLH tpHL
td(off)
t
dVOUT/dt
ON OFF
dVOUT/dt
GAPGCFT00797
VNQ7E100AJ
Main electrical characteristics
DS12570 - Rev 3 page 13/45
Figure 7. Current sense timings (current sense mode)
IN1
I
t t tt
Low
Low
Low
SEL1
SEL0
SEn
OUT1
Current Sense
DSENSE2H DSENSE1L
High
High
High
DSENSE1H DSENSE2L
GADG0704171311PS
Figure 8. TDSKON
TDSTKON
VINPUT
VOUT
MultiSense
VOUT > VOL
GAPG2609141140CFT
VNQ7E100AJ
Main electrical characteristics
DS12570 - Rev 3 page 14/45
Table 11. Truth table
Mode Conditions INXFR SEn SELXOUTXCurrent sense Comments
Standby All logic inputs low L L L L L Hi-Z Low quiescent current
consumption
Normal Nominal load connected;
Tj < 150°C
L X
See (1)
LSee (1)
H L H See (1) Outputs configured for
auto-restart
H H H See (1) Outputs configured for
Latch-off
Overload
Overload or short to GND
causing:
Tj > TTSD or ΔTj > ΔTj_SD
L X
See (1)
LSee (1)
H L H See (1) Output cycles with
temperature hysteresis
H H L See (1) Output latches-off
Under-voltage VCC < VUSD (falling) X X X X L
L
Hi-Z
Hi-Z
Re-start when
VCC > VUSD +
VUSDhyst (rising)
OFF-state
diagnostics
Short to VCC L X
See (1)
HSee (1)
Open-load L X H See (1) External pull-up
Negative output
voltage Inductive loads turn-off L X See (1) < 0 V See (1)
1. Refer to Table 12. Current sense multiplexer addressing
Table 12. Current sense multiplexer addressing
SEn SEL1SEL0
MUX
channel
Current sense output
Nomal mode Overload OFF-state diag. (1) (2)
(3) Negative output
L X X Hi-Z
H L L Channel 0
diagnostic
ISENSE = 1/
K * IOUT0
VSENSE =
VSENSEH
VSENSE = VSENSEH Hi-Z
H L H Channel 1
diagnostic
ISENSE = 1/
K * IOUT1
VSENSE =
VSENSEH
VSENSE = VSENSEH Hi-Z
H H L Channel 2
diagnostic
ISENSE = 1/
K * IOUT2
VSENSE =
VSENSEH
VSENSE = VSENSEH Hi-Z
H H H Channel 3
diagnostic
ISENSE = 1/
K * IOUT3
VSENSE =
VSENSEH
VSENSE = VSENSEH Hi-Z
1. In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low, CS pin
delivers feedback according to OFF-State diagnostic.
2. Example 1: FR = 1; IN0 = 0; OUT0 = L (latched); MUX channel = channel 0 diagnostic; CS = 0
3. Example 2: FR = 1; IN0 = 0; OUT0 = latched, VOUT0 > VOL; MUX channel = channel 0 diagnostic; CS = VSENSEH
VNQ7E100AJ
Main electrical characteristics
DS12570 - Rev 3 page 15/45
2.4 Waveforms
Figure 9. Latch functionality - behavior in hard short-circuit condition (TAMB << TTSD)
Figure 10. Latch functionality - behavior in hard short-circuit condition
Thermal shut down
cycling
in AutoRestart mode
Logic
high
Logic
high
Logic
high
Logic
high
Hard
short
circuit
VsenseH
IlimH
IlimL
TAMB
TTSD
TR
Input
Fault Reset
Multisense
voltage
Output
Voltage
Output
current
Junction
temperature
Sense
enable
Internal
fault
detection
tt > tlatch RST
Vout <5V Vout <5V
VNQ7E100AJ
Waveforms
DS12570 - Rev 3 page 16/45
Figure 11. Latch functionality - behavior in hard short-circuit condition (autorestart mode + latch off)
Figure 12. Standby mode activation
VNQ7E100AJ
Waveforms
DS12570 - Rev 3 page 17/45
Figure 13. Standby state diagram
GAPGCFT00598
Normal Operation
Stand-by Mode
t > t D_STBY
INx = Low
AND
FaultRST = Low
AND
SEn = Low
AND
SELx = Low
INx = High
OR
FaultRST = High
OR
SEn = High
OR
SELx = High
VNQ7E100AJ
Waveforms
DS12570 - Rev 3 page 18/45
2.5 Electrical characteristics curves
Figure 14. OFF-state output current
GADG071220181211OSOC
300
250
200
150
100
50
0
-50 -25 0 25 50 75 100 125 150
Iloff [nA]
T [°C]
VCC = 13 V
Vin = Vout = 0
Off state
175
Figure 15. Standby current
GADG071220181212STBC
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50 -25 0 25 50 75 100 125 150
ISTBY [µA]
T [°C]
VCC = 13 V
175
Figure 16. IGND(ON) vs. Iout
GADG071220181212IGIO
10
8
6
4
2
0
-50 -25 0 25 50 75 100 125 150
IGND(ON) [mA]
T [°C]
VCC = 13 V
IOUT = 1 A
175
Figure 17. Logic input high level voltage
GADG071220181214LILV
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50 -25 0 25 50 75 100 125 150
ViIH ,VFRH ,VSELH ,VSEnH [V]
T [°C]
175
Figure 18. Logic input low level voltage
GADG071220181214LILLV
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50 -25 0 25 50 75 100 125 150
ViIL ,VFRL ,VSELL ,VSEnL [V]
T [°C]
175
Figure 19. High level logic input current
GADG101220181119HLLIC
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150
IiH ,IFRH ,ISELH ,ISEnH [µA]
T [°C]
175
VNQ7E100AJ
Electrical characteristics curves
DS12570 - Rev 3 page 19/45
Figure 20. Low level logic input current
GADG071220181216LLLIC
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150
IiL ,IFRL ,ISELL ,ISEnL [µA]
T [°C]
175
Figure 21. Logic input hysteresis voltage
GADG071220181216LIHV
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150
Vi(hyst) ,VFR(hyst) ,VSEL(hyst) ,VSEn(hyst) [V]
T [°C]
175
Figure 22. FaultRST Input clamp voltage
GADG071220181217FICV
7
6
5
4
3
2
1
0
-1
-2
-50 -25 0 25 50 75 100 125 150
VFRCL(hyst) [V]
T [°C]
IIN = 1 mA
IIN = -1 mA
175
Figure 23. Undervoltage shutdown
GADG071220181217UNSH
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150
VUSD [V]
T [°C]
175
Figure 24. On-state resistance vs. Tcase
GADG071220181217OSRT
180
160
140
120
100
80
60
40
20
0
-50 -25 0 25 50 75 100 125 150
RDS(on) [mΩ]
T [°C]
IOUT = 1 A
VCC = 13 V
175
Figure 25. On-state resistance vs. VCC
GADG071220181218ONRV
200
180
160
140
120
100
80
60
40
20
00 5 10 15 20 25 30 35
RDS(on) [mΩ]
V [V]
T = 150 °C
T = 125 °C
T = 25 °C
40
T = -40 °C
VNQ7E100AJ
Electrical characteristics curves
DS12570 - Rev 3 page 20/45
Figure 26. Turn-on voltage slope
GADG071220181218ONVS
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150
(dVout /dt)on [V/µs]
T [°C]
VCC = 13 V
RL = 13 Ω
175
Figure 27. Turn-off voltage slope
GADG071220181219OFVS
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150
(dVout /dt)off [V/µs]
T [°C]
VCC = 13 V
RL = 13 Ω
175
Figure 28. Won vs. Tcase
GADG071220181220WONT
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150
Won [m/J]
T [°C]
175
Figure 29. Woff vs. Tcase
GADG071220181220WOFFT
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150
Woff [m/J]
T [°C]
175
Figure 30. OFF-state open-load voltage detection
threshold
GADG071220181221OFFOL
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150
IOL [A]
T [°C]
175
Figure 31. VSENSE clamp vs. Tcase
GADG071220181222VCT
5
0
-5
-10
-15
-20
-50 -25 0 25 50 75 100 125 150
VSENSE_CL [V]
T [°C]
Iin = -1 mA
Iin = 1 mA
175
VNQ7E100AJ
Electrical characteristics curves
DS12570 - Rev 3 page 21/45
Figure 32. VSENSEH vs. Tcase
GADG071220181222VST
9
8
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150
VSENSEH [V]
T [°C]
175
VNQ7E100AJ
Electrical characteristics curves
DS12570 - Rev 3 page 22/45
3Protections
3.1 Power limitation
The basic working principle of this protection consists of an indirect measurement of the junction temperature
swing ΔTj through the direct measurement of the spatial temperature gradient on the device surface in order to
automatically shut off the output MOSFET as soon as ΔTj exceeds the safety level of ΔTj_SD. According to the
voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis
according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off
(FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo-
mechanical fatigue.
3.2 Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C), it
automatically switches off and the diagnostic indication is triggered. According to the voltage level on the
FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or
remains off (FaultRST = High).
3.3 Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as the other
components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current
flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a
safety level, ILIMH, by operating the output power MOSFET in the active region.
3.4 Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative
voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor
energy to be dissipated without damaging the device.
VNQ7E100AJ
Protections
DS12570 - Rev 3 page 23/45
4Application information
Figure 33. Application diagram
VDD
OUT
OUT
OUT
OUT
ADC in
OUT
GND
GND
GND GND
Logic
OUTPUT
GND
FaultRST
INPUT
SEn
SEL
VCC
CS
Current mirror
Rprot
Rprot
Rprot
Rprot
Rprot
+5V
R
GND
Rsense
D
GND
Cext
GND GND
Dld
VNQ7E100AJ
Application information
DS12570 - Rev 3 page 24/45
4.1 GND protection network against reverse battery
Figure 34. Simplified internal structure
MCU
INPUT
SEn
CS
FaultRST
Vcc
OUTPUT
GND
Rprot
Rprot
Rprot
Rprot
Dld
Rsense
5V
RGND DGND
GND GAPGCFT00830
4.1.1 Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of
the ground network produces a shift (≈600 mV) in the input threshold and in the status output values if the
microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares
the same diode/resistor network.
4.2 Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the supply lines and injected
into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010.
The related function performance status classification is shown in Table 13. ISO 7637-2 - electrical transient
conduction along supply line.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO
7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed
through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: “The function
does not perform as designed during the test but returns automatically to normal operation after the test”.
VNQ7E100AJ
GND protection network against reverse battery
DS12570 - Rev 3 page 25/45
Table 13. ISO 7637-2 - electrical transient conduction along supply line
Test Pulse
2011(E)
Test pulse severity level with
Status II functional
performance status
Minimum number
of pulses or test
time
Burst cycle / pulse
repetition time Pulse duration and pulse
generator internal
impedance
Level US (1) min max
1 III -112 V 500 pulses 0.5 s 2 ms, 10 Ω
2a(3) III +55 V 500 pulses 0.2 s 5 s 50 µs, 2 Ω
3a IV -220 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b IV +150 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
4 (2) IV -7 V 1 pulse 100 ms, 0.01 Ω
Load dump according to ISO 16750-2:2010
Test B (3) 40 V 5 pulse 1 min 400 ms, 2 Ω
1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
2. Test pulse from ISO 7637-2:2004(E).
3. With 40 V external suppressor referred to ground (-40°C < Tj < 150 °C).
4.3 MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line, the control pins will be
pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins from
latching-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of microcontroller and the current
required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.
Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4 CS - analog current sense
Diagnostic information on device and load status are provided by an analog output pin (CS) delivering the
following signals:
• Current monitor: current mirror of channel output current
Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and
SEn pins, according to the address map in MultiSense multiplexer addressing Table.
VNQ7E100AJ
MCU I/Os protection
DS12570 - Rev 3 page 26/45
Figure 35. CurrentSense and diagnostic – block diagram
1
n
R
R
V
MUX
I
I
T
0
VCC
Gate Driver
VCC – OUT
Clamp
Limitation
Current
Power Limitation
Overtemperature
Open-Load in OFF
Short to VCC K factor
Sense
Current
Control & Diagnostic
shut-down
Undervoltage
Internal Supply
Clamp
VCC – GND
Diagnostic
Fault
SENSEH
CURRENT
MONITOR
GND
INPUT
SEL
SEL
SE
SENSE
PROT
To µC ADC
SENSE
FaultRST
Fault OUT
OUT
CS
GADG2004171456PS
VNQ7E100AJ
CS - analog current sense
DS12570 - Rev 3 page 27/45
4.4.1 Principle of CurrentSense signal generation
Figure 36. CurrentSense block diagram
INPUT
Vcc
OUT
To uC ADC
RPROT RSENSE
Main MOSSense MOS
Fault
CS
Current sense Switch Block
Current sense
GAPG2307131200CFT
Current sense
The output is able to provide:
• Current mirror proportional to the load current in normal operation, delivering current proportional to the load
according to a known ratio named K
• Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted into a voltage VSENSE by using
an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using
simple equations
Current provided by CS output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K
Where:
• VSENSE is the voltage measurable on RSENSE resistor
VNQ7E100AJ
CS - analog current sense
DS12570 - Rev 3 page 28/45
• ISENSE is the current provided from CS pin in current output mode
• IOUT is the current flowing through output
• K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric
factor spread, current sense amplifier offset and process parameters spread of the overall circuitry,
specifying the ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the CS pin which is switched to a “current
limited” voltage source, VSENSEH.
In any case, the current sourced by the CS in this condition is limited to ISENSEH.
Figure 37. Analog HSD – open-load detection in off-state
15k
15k
15k
15k
15k
+5V
R
GN D
4.7k
Vbat
Rsense
15k
V
DD
OUT
OUT
OUT
OUT
ADC in
GND
OUT
100nF
GND
GND GND GND GND GND
100nF/ 50V
CEXT
D
GN D
10 nF /100V
GND
Microcontroller
OUTPUT
Vbat
Rpull-up
External
Pull -Up
switch
Logic
GND
FaultRST
INPUT
SEn
SEL
V
CC
CS
Cu rre nt mirr or
OUTPUT
GAPG1201151432CFT
VNQ7E100AJ
CS - analog current sense
DS12570 - Rev 3 page 29/45
Figure 38. Open-load / short to VCC condition
VSENSEH
VSENSE = 0
VSENSEH
tDSTKON
VSENSE
VSENSE
VIN
Pull-up connected
Pull-up
disconnected
Open-load
Short to VCC
Table 14. CurrentSense pin levels in off-state
Condition Output CS SEn
Open-load
VOUT > VOL
Hi-Z L
VSENSEH H
VOUT < VOL
Hi-Z L
0 H
Short to VCC VOUT > VOL
Hi-Z L
VSENSEH H
Nominal VOUT < VOL
Hi-Z L
0 H
4.4.2 Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the
device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature
of the short-circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive
supply voltage VPU.
It is preferable that VPU is switched off during the module standby mode in order to avoid the overall standby
current consumption to increase in normal conditions, i.e. when load is connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation:
VNQ7E100AJ
CS - analog current sense
DS12570 - Rev 3 page 30/45
Equation
R
PU < V
PU - 4
IL(off2)min @ 4V
VNQ7E100AJ
CS - analog current sense
DS12570 - Rev 3 page 31/45
5Maximum demagnetization energy (Vcc = 16 V)
Figure 40. Maximum turn off current versus inductance
GADG101220181148MTOC
100
10-1
10-1 100101102
I [A]
L [mH]
103
Single pulse
Repetitive pulse Tjstart = 100°C
Repetitive pulse Tjstart = 125°C
Figure 41. Maximum turn off energy versus inductance
GADG101220181149MTOE
102
101
100
10-1 100101102
EI [mJ]
L [mH]
103
Single pulse
Repetitive pulse Tjstart = 100°C
Repetitive pulse Tjstart = 125°C
Note: Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the
temperature specified above for curves A and B.
VNQ7E100AJ
Maximum demagnetization energy (Vcc = 16 V)
DS12570 - Rev 3 page 32/45
6Package and PCB thermal data
6.1 PowerSSO-16 thermal data
Figure 42. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 43. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 15. PCB properties
Dimension Value
Board finish thickness 1.6 mm +/- 10%
Board dimension 77 mm x 86 mm
Board Material FR4
Copper thickness (top and bottom layers) 0.070 mm
Copper thickness (inner layers) 0.035 mm
Thermal vias separation 1.2 mm
Thermal via diameter 0.3 mm +/- 0.08 mm
Copper thickness on vias 0.025 mm
Footprint dimension (top layer) 2.2 mm x 3.9 mm
VNQ7E100AJ
Package and PCB thermal data
DS12570 - Rev 3 page 33/45
Dimension Value
Heatsink copper area dimension (bottom layer) Footprint, 2 cm2 or 8 cm2
Figure 44. Rthj-amb vs PCB copper area in open box free air condition (one channel on)
30
40
50
60
70
80
90
0 2 4 6 8 10
RTHjamb
RTHjamb
GAPG2307131254CFT
Figure 45. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
GAPG2307131257CFT
Time (s)
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10 100 1000
ZTH (°C/W)
Cu=footprint
Cu=2 cm2
Cu=8 cm2
4 Layer
Equation: pulse calculation formula
ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T
VNQ7E100AJ
PowerSSO-16 thermal data
DS12570 - Rev 3 page 34/45
Figure 46. Thermal fitting model of a double-channel HSD in PowerSSO-16
C1
R1
C4
R4
C6
R6
C5
R5
C7
R7
C9
R9
C11
R11
C2
R2
C8
R8
C10
R10
C12
R12
C3
R3
PdCh1
T_amb
Tj
PdCh2
PdCh4
PdCh3
Tj
Tj
Tj
GADG2203171318PS
Note: The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections
(power limitation or thermal cycling during thermal shutdown) are not triggered.
Table 16. Thermal parameters
Area/island (cm²) Footprint 2 8 4L
R1, R7 (°C/W) 1.75
R2, R8 (°C/W) 6
R3 (°C/W) 6.6 6.6 6.6 5.4
R4 (°C/W) 16 6 6 4
R5 (°C/W) 30 20 10 3
R6 (°C/W) 26 20 18 7
C1, C7 (W.s/°C) 0.0002
C2, C8 (W.s/°C) 0.0009
C3 (W.s/°C) 0.023
C4 (W.s/°C) 0.2 0.3 0.3 0.4
C5 (W.s/°C) 0.4 1 1 4
C6 (W.s/°C) 3 5 7 18
VNQ7E100AJ
PowerSSO-16 thermal data
DS12570 - Rev 3 page 35/45
7Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
7.1 PowerSSO-16 package information
Figure 47. PowerSSO-16 package dimensions
GAPG1605141159CFT
8017965_Rev_9
Bottom view
Top view
Section A-A
Section B-B
θ1
θ3
θ2
h
h
R1
R
L1
L
B
B
GAUGE PLANE
S
θ
b1
cc1
b
BASE METAL
WITH PLATING
E2E3
D2
D3
AA2
A1 b
SEATING PLANE
for dual gauge only
for dual gauge only
ccc C
C
H
eee C
ggg
ggg A-B DC
A-B DC
e
index area
(0.25D x 0.75E1)
2x N/2 TIPS
2x
1.2
aaa C D
N
123
D
EE1
f f f
ddd
C
bbb C
C D
A-B
AD
B
2x
AN/2
A
minimum solderable area
VNQ7E100AJ
Package information
DS12570 - Rev 3 page 36/45
Table 17. PowerSSO-16 mechanical data
Symbol
Millimeters
Min. Typ. Max.
Θ 0° 8°
Θ1 0°
Θ2 5° 15°
Θ3 5° 15°
A 1.70
A1 0.00 0.10
A2 1.10 1.60
b 0.20 0.30
b1 0.20 0.25 0.28
c 0.19 0.25
c1 0.19 0.20 0.23
D 4.90 BSC
D2 3.31 3.91
D3 2.61
e 0.50 BSC
E 6.00 BSC
E1 3.90 BSC
E2 2.20 2.80
E3 1.49
h 0.25 0.50
L 0.40 0.60 0.85
L1 1.00 REF
N 16
R 0.07
R1 0.07
S 0.20
Tolerance of form and position
aaa 0.10
bbb 0.10
ccc 0.08
ddd 0.08
eee 0.10
fff 0.10
ggg 0.15
VNQ7E100AJ
PowerSSO-16 package information
DS12570 - Rev 3 page 37/45
7.2 PowerSSO-16 packing information
Figure 48. PowerSSO-16 reel 13"
Access Hole at
Slot Location
( 40 mm min.)
If present,
tape slot in core
for tape start:
2.5 mm min. width x
10.0 mm min. depth
C
N
W2
W1
D
A
B
TAPG2004151655CFT
Table 18. Reel dimensions
Description Value(1)
Base quantity 2500
Bulk quantity 2500
A (max) 330
B (min) 1.5
C (+0.5, -0.2) 13
D (min) 20.2
N 100
W1 (+2 /-0) 12.4
W2 (max) 18.4
1. All dimensions are in mm.
VNQ7E100AJ
PowerSSO-16 packing information
DS12570 - Rev 3 page 38/45
Figure 49. PowerSSO-16 carrier tape
0.30 ±0.05 1.55 ±0.05
1.6 ±0.1
R 0.5
Typical
K1
K0
B0
P2
2.0 ±0.1
P0
4.0 ±0.1
P1A0
F
W
1.75 ±0.1
SECTION X - X
SECTION Y - Y
REF 4.18
REF 0.6
REF 0.5
X
X
Y Y
GAPG2204151242CFT
Table 19. PowerSSO-16 carrier tape dimensions
Description Value(1)
A06.50 ± 0.1
B05.25 ± 0.1
K02.10 ± 0.1
K11.80 ± 0.1
F 5.50 ± 0.1
P18.00 ± 0.1
W 12.00 ± 0.3
1. All dimensions are in mm.
Figure 50. PowerSSO-16 schematic drawing of leader and trailer tape
Embossed carrier
Carrier tape
Round sprocket holes
Elongated sprocket holes
Top cover tape
(32 mm tape and wider)
Top cover tape
Trailer
160 mm minimum
Leader
100 mm min.
400 mm minimumComponents
User direction feed
Punched carrier
8 mm & 12 mm only
END START
GAPG2004151511CFT
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PowerSSO-16 packing information
DS12570 - Rev 3 page 39/45
7.3 PowerSSO-16 marking information
Figure 51. PowerSSO-16 marking information
Spe cial function dig it
&: Engineering sample
<blank>: Commercial sample
PowerSSO-16 TOP VIEW
(not to scale)
GADG0310161234SMD
Parts marked as '&' are not yet qualified and therefore not approved for use in production. ST is not responsible
for any consequences resulting from such use. In no event will ST be liable for the customer using any of these
engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
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PowerSSO-16 marking information
DS12570 - Rev 3 page 40/45
Revision history
Table 20. Document revision history
Date Version Changes
08-June-2018 1 Initial release.
08-Jan-2019 2
Updated features and application in cover page.
Updated Table 4. Thermal data, Section 2.3 Main electrical characteristics, Figure 12. Standby mode
activation.
Inserted Section 2.5 Electrical characteristics curves, Section 5 Maximum demagnetization energy
(Vcc = 16 V) and Section 6 Package and PCB thermal data.
Minor text changes.
18-Feb-2019 3 Updated Figure 44 and Figure 45.
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DS12570 - Rev 3 page 41/45
Contents
1Block diagram and pin description .................................................3
2Electrical specification.............................................................5
2.1 Absolute maximum ratings.......................................................5
2.2 Thermal data ..................................................................6
2.3 Main electrical characteristics ....................................................7
2.4 Waveforms ...................................................................15
2.5 Electrical characteristics curves .................................................19
3Protections .......................................................................23
3.1 Power limitation ...............................................................23
3.2 Thermal shutdown.............................................................23
3.3 Current limitation ..............................................................23
3.4 Negative voltage clamp ........................................................23
4Application information...........................................................24
4.1 GND protection network against reverse battery....................................24
4.1.1 Diode (DGND) in the ground line............................................25
4.2 Immunity against transient electrical disturbances ..................................25
4.3 MCU I/Os protection ...........................................................26
4.4 CS - analog current sense ......................................................26
4.4.1 Principle of CurrentSense signal generation ...................................27
4.4.2 Short to VCC and OFF-state open-load detection ...............................30
5Maximum demagnetization energy (VCC = 16 V)...................................32
6Package and PCB thermal data ...................................................33
6.1 PowerSSO-16 thermal data .....................................................33
7Package information..............................................................36
7.1 PowerSSO-16 package information ..............................................36
7.2 PowerSSO-16 packing information ...............................................37
7.3 PowerSSO-16 marking information...............................................39
Revision history .......................................................................41
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Contents
DS12570 - Rev 3 page 42/45
List of tables
Table 1. Pin functions .......................................................................3
Table 2. Suggested connections for unused and not connected pins .......................................4
Table 3. Absolute maximum ratings .............................................................5
Table 4. Thermal data.......................................................................6
Table 5. Electrical characteristics during cranking....................................................7
Table 6. Power section ......................................................................7
Table 7. Switching .........................................................................8
Table 8. Logic Inputs .......................................................................8
Table 9. Protections ........................................................................9
Table 10. CurrentSense ..................................................................... 10
Table 11. Truth table ....................................................................... 15
Table 12. Current sense multiplexer addressing ..................................................... 15
Table 13. ISO 7637-2 - electrical transient conduction along supply line .................................... 26
Table 14. CurrentSense pin levels in off-state ...................................................... 30
Table 15. PCB properties .................................................................... 33
Table 16. Thermal parameters ................................................................. 35
Table 17. PowerSSO-16 mechanical data ......................................................... 37
Table 18. Reel dimensions ................................................................... 38
Table 19. PowerSSO-16 carrier tape dimensions .................................................... 39
Table 20. Document revision history ............................................................. 41
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List of tables
DS12570 - Rev 3 page 43/45
List of figures
Figure 1. Block diagram ....................................................................3
Figure 2. Configuration diagram (top view)........................................................4
Figure 3. Current and voltage conventions........................................................5
Figure 4. IOUT/ISENSE versus IOUT ............................................................ 12
Figure 5. Current sense accuracy versus IOUT .................................................... 13
Figure 6. Switching times and Pulse skew ....................................................... 13
Figure 7. Current sense timings (current sense mode)............................................... 14
Figure 8. TDSKON ........................................................................ 14
Figure 9. Latch functionality - behavior in hard short-circuit condition (TAMB << TTSD)......................... 16
Figure 10. Latch functionality - behavior in hard short-circuit condition..................................... 16
Figure 11. Latch functionality - behavior in hard short-circuit condition (autorestart mode + latch off) ................ 17
Figure 12. Standby mode activation ............................................................ 17
Figure 13. Standby state diagram.............................................................. 18
Figure 14. OFF-state output current ............................................................ 19
Figure 15. Standby current .................................................................. 19
Figure 16. IGND(ON) vs. Iout .................................................................. 19
Figure 17. Logic input high level voltage ......................................................... 19
Figure 18. Logic input low level voltage .......................................................... 19
Figure 19. High level logic input current.......................................................... 19
Figure 20. Low level logic input current .......................................................... 20
Figure 21. Logic input hysteresis voltage......................................................... 20
Figure 22. FaultRST Input clamp voltage......................................................... 20
Figure 23. Undervoltage shutdown ............................................................. 20
Figure 24. On-state resistance vs. Tcase ......................................................... 20
Figure 25. On-state resistance vs. VCC ......................................................... 20
Figure 26. Turn-on voltage slope .............................................................. 21
Figure 27. Turn-off voltage slope .............................................................. 21
Figure 28. Won vs. Tcase ................................................................... 21
Figure 29. Woff vs. Tcase ................................................................... 21
Figure 30. OFF-state open-load voltage detection threshold ........................................... 21
Figure 31. VSENSE clamp vs. Tcase ............................................................ 21
Figure 32. VSENSEH vs. Tcase ................................................................ 22
Figure 33. Application diagram................................................................ 24
Figure 34. Simplified internal structure .......................................................... 25
Figure 35. CurrentSense and diagnostic – block diagram ............................................. 27
Figure 36. CurrentSense block diagram ......................................................... 28
Figure 37. Analog HSD – open-load detection in off-state ............................................. 29
Figure 38. Open-load / short to VCC condition ..................................................... 30
Figure 40. Maximum turn off current versus inductance............................................... 32
Figure 41. Maximum turn off energy versus inductance ............................................... 32
Figure 42. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ................................. 33
Figure 43. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ................................. 33
Figure 44. Rthj-amb vs PCB copper area in open box free air condition (one channel on) ........................ 34
Figure 45. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) .................... 34
Figure 46. Thermal fitting model of a double-channel HSD in PowerSSO-16 ................................ 35
Figure 47. PowerSSO-16 package dimensions .................................................... 36
Figure 48. PowerSSO-16 reel 13" ............................................................. 38
Figure 49. PowerSSO-16 carrier tape ........................................................... 39
Figure 50. PowerSSO-16 schematic drawing of leader and trailer tape .................................... 39
Figure 51. PowerSSO-16 marking information ..................................................... 40
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List of figures
DS12570 - Rev 3 page 44/45
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