© Semiconductor Components Industries, LLC, 2011
June, 2011 Rev. 7
1Publication Order Number:
74FST3257/D
74FST3257
Quad 2:1 Multiplexer/
Demultiplexer Bus Switch
The ON Semiconductor 74FST3257 is a quad 2:1, high performance
multiplexer/demultiplexer bus switch. The device is CMOS TTL
compatible when operating between 4 and 5.5 Volts. The device
exhibits extremely low RON and adds nearly zero propagation delay.
The device adds no noise or ground bounce to the system.
Features
RON t 4 W Typical
Less Than 0.25 nsMax Delay Through Switch
Nearly Zero Standby Current
No Circuit Bounce
Control Inputs are TTL/CMOS Compatible
PinForPin Compatible With QS3257, FST3257, CBT3257
All Popular Packages: SOIC16, TSSOP16, QFN16
These Devices are PbFree and are RoHS Compliant
1A
2A
2B2
2B1
1B2
SV
CC
OE
GND 3A
1
2
3
4
5
6
7
16
15
14
13
12
11
10
89
Figure 1. 16Lead Pinout Diagrams
Figure 2. Truth Table
1B1
4B1
4B2
4A
3B2
X
L
H
SFunction
H
L
L
OE
Disconnect
A = B1
A = B2
3B1
1A
2A
2B2
2B1
1B2
SVCC
OE
GND 3A
1
2
3
4
5
6
7
16
15
14
13
12
11
10
89
1B1
4B1
4B2
4A
3B2
3B1
GND
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G= PbFree Package
TSSOP16
DT SUFFIX
CASE 948F
16
1
SOIC16
D SUFFIX
CASE 751B
16
1
1
16
FST3257G
AWLYWW
MARKING
DIAGRAMS
1
16
FST
3257
ALYW G
G
Description
PIN NAMES
OE1, OE2
S0, S1
Pin
Bus Switch Enables
Select Inputs
A Bus A
B1, B2, B3, B4Bus B
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
(Note: Microdot may be in either location)
1
QFN16
MN SUFFIX
CASE 485AW
3257
ALYWG
G
74FST3257
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2
Figure 3. Logic Diagram
1B
1B2
2B1
2B2
3B1
3B2
4B1
4B2
1A
3A
OE
S
FLOW CONTROL
2A
4A
ORDERING INFORMATION
Device Order Number Package Shipping
74FST3257DR2G SOIC16
(PbFree)
2500 Units / Tape & Reel
74FST3257DTR2G TSSOP16*
(PbFree)
2500 Units / Tape & Reel
74FST3257MNTWG QFN16
(PbFree)
3000 Units / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently PbFree.
74FST3257
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3
MAXIMUM RATINGS
Symbol Parameter Value Units
VCC DC Supply Voltage 0.5 to +7.0 V
VIDC Input Voltage 0.5 to +7.0 V
VODC Output Voltage 0.5 to +7.0 V
IIK DC Input Diode Current
VI t GND 50
mA
IOK DC Output Diode Current
VO t GND 50
mA
IODC Output Sink Current 128 mA
ICC DC Supply Current per Supply Pin ±100 mA
IGND DC Ground Current per Ground Pin ±100 mA
TSTG Storage Temperature Range 65 to +150 _C
TLLead Temperature, 1 mm from Case for 10 Seconds 260 _C
TJJunction Temperature Under Bias +150 _C
qJA Thermal Resistance
SOIC
TSSOP
QFN
125
170
N/A
_C/W
MSL Moisture Sensitivity Level 1
FRFlammability Rating
Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
VESD ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
u2000
u200
N/A
V
ILatchup Latchup Performance
Above VCC and Below GND at 85_C (Note 4) ±500
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22A114A.
2. Tested to EIA/JESD22A115A.
3. Tested to JESD22C101A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Units
VCC Supply Voltage
Operating, Data Retention Only 4.0 5.5
V
VIInput Voltage (Note 5) 0 5.5 V
VOOutput Voltage (HIGH or LOW State) 0 5.5 V
TAOperating FreeAir Temperature 40 +85 _C
Dt/DVInput Transition Rise or Fall Rate Switch Control Input
Switch I/O VCC = 5.0 V ± 0.5 V 0
DC
5
ns/V
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
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4
DC ELECTRICAL CHARACTERISTICS
VCC TA = 40_C to +85_C
Symbol Parameter Conditions (V) Min Typ* Max Units
VIK Clamp Diode Voltage IIN = 18 mA 4.5 1.2 V
VIH HighLevel Input Voltage 4.0 to 5.5 2.0 V
VIL LowLevel Input Voltage 4.0 to 5.5 0.8 V
IIInput Leakage Current 0 VIN 5.5 V 5.5 ±1.0 mA
IOZ OffState Leakage Current 0 A, B VCC 5.5 ±1.0 mA
RON Switch On Resistance (Note 6) VIN = 0 V, IIN = 64 mA 4.5 4 7 W
VIN = 0 V, IIN = 30 mA 4.5 4 7
VIN = 2.4 V, IIN = 15 mA 4.5 8 15
VIN = 2.4 V, IIN = 15 mA 4.0 11 20
ICC Quiescent Supply Current VIN = VCC or GND, IOUT = 0 5.5 3 mA
DICC Increase In ICC per Input One input at 3.4 V,
Other inputs at VCC or GND
5.5 2.5 mA
*Typical values are at VCC = 5.0 V and TA = 25_C.
6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower
of the voltages on the two (A or B) pins.
AC ELECTRICAL CHARACTERISTICS
TA = 40_C to +85_C
CL = 50 pF, RU = RD = 500 W
VCC = 4.55.5 V VCC = 4.0 V
Symbol Parameter Conditions Min Max Min Max Units
tPHL,
tPLH
Prop Delay Bus to Bus (Note 7) VI = OPEN 0.25 0.25 ns
Prop Delay, Select to Bus A 1.0 4.7 5.2
tPZH,
tPZL
Output Enable Time, Select to Bus B VI = 7 V for tPZL 1.0 5.2 5.7 ns
Output Enable Time, IOE to Bus A, B VI = OPEN for tPZH 1.0 5.1 5.6
tPHZ,
tPLZ
Output Disable Time, Select to Bus B VI = 7 V for tPLZ 1.0 5.2 5.5 ns
Output Disable Time, IOE to Bus A, B VI = OPEN for tPHZ 1.0 5.5 5.5
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE (Note 8)
Symbol Parameter Conditions Typ Max Units
CIN Control Pin Input Capacitance VCC = 5.0 V 3 pF
CI/O A Port Input/Output Capacitance VCC, OE = 5.0 V 7 pF
CI/O B Port Input/Output Capacitance VCC, OE = 5.0 V 5 pF
8. TA = )25_C, f = 1 MHz, Capacitance is characterized but not tested.
74FST3257
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5
VI
VOL
VOL + 0.3 V
tPLH
tPLH
VOL
VOH
VOH 0.3 V
tPHZ
tf = 2.5 nS
90 %
1.5 V
10 %10 %
1.5 V
90 %
tf = 2.5 nS
tPZL tPLZ
OUTPUT 1.5 V
OUTPUT
1.5 V
GND
3.0 V
tPZH
ENABLE
INPUT
tf = 2.5 nS
90 %
1.5 V1.5 V
90 %
10 % 10 %
1.5 V 1.5 V
VOH
GND
3.0 V
SWITCH
INPUT
tf = 2.5 nS
CL*
FROM
OUTPUT
UNDER
TEST
Figure 4. AC Test Circuit
Figure 5. Propagation Delays
AC Loading and Waveforms
NOTES:
1. Input driven by 50 W source terminated in 50 W.
2. CL includes load and stray capacitance.
*CL = 50 pF
500 W
500 W
Figure 6. Enable/Disable Delays
OUTPUT
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6
PACKAGE DIMENSIONS
SOIC16
D SUFFIX
CASE 751B05
ISSUE K
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
16
89
8X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
B
A
M
0.25 (0.010) B S
T
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
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7
PACKAGE DIMENSIONS
TSSOP16
DT SUFFIX
CASE 948F01
ISSUE B
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.
____
SECTION NN
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
U
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
T
V
W
0.25 (0.010)
16X REFK
N
N
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8
PACKAGE DIMENSIONS
QFN16
MN SUFFIX
CASE 485AW01
ISSUE O
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.80
3.80
1.10
0.50
0.60
16X
0.30
16X
DIMENSIONS: MILLIMETERS
1
2.10
PITCH
PACKAGE
OUTLINE
ÉÉÉ
ÉÉÉ
ÉÉÉ
DIM MIN MAX
MILLIMETERS
A
A1 0.00 0.05
A3
b0.20 0.30
D2.50 BSC
D2 0.85 1.15
E3.50 BSC
E2
e0.50 BSC
K0.20 ---
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
0.20 REF
b
D2
L
PIN ONE
E2
1
8
15
10
D
E
B
A
C0.15
C0.15
2X
2X
e
2
16X
16X
0.10 C
0.05 C
A B
NOTE 3
A
16X
K
A1
(A3)
SEATING
PLANE
C0.08
C0.10
0.80 1.00
L0.35 0.45
1.85 2.15
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
ÇÇÇ
ÉÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
DETAIL B
REFERENCE
TOP VIEW
SIDE VIEW
NOTE 4
C
0.15 C A B
0.15 C A B
DETAIL A
BOTTOM VIEW
e/2
L1 --- 0.15
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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PUBLICATION ORDERING INFORMATION
N. American Technical Support: 8002829855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81357733850
74FST3257/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
Email: orderlit@onsemi.com
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For additional information, please contact your local
Sales Representative