© Semiconductor Components Industries, LLC, 2009
November, 2009 − Rev. 9
1Publication Order Number:
NCP3063/D
NCP3063, NCP3063B,
NCV3063
1.5 A, Step-Up/Down/
Inverting Switching
Regulators
The NCP3063 Series is a higher frequency upgrade to the popular
MC34063A and MC33063A monolithic DC−DC converters. These
devices consist of an internal temperature compensated reference,
comparator, a controlled duty cycle oscillator with an active current
limit circuit, a driver and a high current output switch. This series was
specifically designed to be incorporated in Step−Down, Step−Up and
Voltage−Inverting applications with a minimum number of external
components.
Features
•Operation to 40 V Input
•Low Standby Current
•Output Switch Current to 1.5 A
•Output Voltage Adjustable
•Frequency Operation of 150 kHz
•Precision 1.5% Reference
•New Features: Internal Thermal Shutdown with Hysteresis
New Features: Cycle−by−Cycle Current Limiting
•Pb−Free Packages are Available
Applications
•Step−Down, Step−Up and Inverting supply applications
•High Power LED Lighting
•Battery Chargers
Figure 1. Typical Buck Application Circuit
L
REFERENCE
D
COMPARATOR
5
R2
R
S
Q
SET dominant
+
−
7COMPARATOR
CT
3
Rs
1.25 V
8NCP3063
REGULATOR
TSD
0.2 V
+
−
2
6
R1
R
S
Q
4
1
12 V CT
2.2 nF
OSCILLATOR
47 mH
Vout
3.3 V /
800 mA
+
470 mF
Cout
Vin
+
220 mF
Cin
SET dominant
0.15 W
3.9 kW
2.4 kW
PDIP−8
P, P1 SUFFIX
CASE 626
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MARKING
DIAGRAMS
DFN−8
CASE 488AF
SOIC−8
D SUFFIX
CASE 751
1
8
NCP3063x
AWL
YYWWG
NCP3063x = Specific Device Code
x = B
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
ORDERING INFORMATION
V3063
ALYW
G
1
3063x
ALYW
G
1
NCV3063
AWL
YYWWG
1
1
1
8
NCP
3063x
ALYW
G
NCP
3063
ALYW
G
1
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Figure 2. Pin Connections
Timing Capacitor
Comparator
Inverting
Input
VCC
N.C.
Ipk Sense
GND
Switch Emitter
Switch Collector
(Top View)
4
3
2
1
5
6
7
8
Ç
Ç
Ç
Ç
ÇÇ
ÇÇ
ÇÇ
ÇÇ
Comparator
Inverting
Input
VCC
N.C.
Ipk Sense
Timing Capacitor
GND
Switch Emitter
Switch Collector
(Top View)
Figure 3. Pin Connections
NOTE: EP Flag must be tied to GND Pin 4
on PCB
EP Flag
Figure 4. Block Diagram
REFERENCE
COMPARATOR
5
R
S
Q
SET dominant
+
−
7COMPARATOR
CT
3
1.25 V
8
NCP3063
REGULATOR
TSD
0.2 V
+
−
2
6
R
S
Q
4
1
OSCILLATOR
Switch Collector
Switch Emitter
Timing Capacitor
GND
Comparator Inverting Input
+VCC
Ipk Sense
N.C.
SET dominant
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PIN DESCRIPTION
Pin No. Pin Name Description
1Switch Collector Internal Darlington switch collector
2Switch Emitter Internal Darlington switch emitter
3Timing Capacitor
Oscillator Input
Timing Capacitor
4 GND Ground pin for all internal circuits
5 Comparator
Inverting Input
Inverting input pin of internal comparator
6 VCC Voltage Supply
7 Ipk Sense Peak Current Sense Input to monitor the voltage drop across an external resistor to limit the peak
current through the circuit
8 N.C. Pin Not Connected
Exposed
Pad
Exposed Pad The exposed pad beneath the package must be connected to GND (Pin 4). Additionally, using
proper layout techniques, the exposed pad can greatly enhance the power dissipation capabilities
of the NCP3063.
MAXIMUM RATINGS (measured vs. Pin 4, unless otherwise noted)
Rating Symbol Value Unit
VCC pin 6 VCC 0 to +40 V
Comparator Inverting Input pin 5 VCII −0.2 to + VCC V
Darlington Switch Collector pin 1 VSWC 0 to +40 V
Darlington Switch Emitter pin 2 (transistor OFF) VSWE −0.6 to + VCC V
Darlington Switch Collector to Emitter pin 1−2 VSWCE 0 to +40 V
Darlington Switch Current ISW 1.5 A
Ipk Sense Pin 7 VIPK −0.2 to VCC + 0.2 V
Timing Capacitor Pin 3 VTCAP −0.2 to +1.4 V
POWER DISSIPATION AND THERMAL CHARACTERISTICS
Rating Symbol Value Unit
PDIP−8 Thermal Resistance, Junction−to−Air RqJA 100 °C/W
SOIC−8 Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
RqJA
RqJC
180
45
°C/W
DFN−8 Thermal Resistance, Junction−to−Air RqJA 80 °C/W
Storage Temperature Range TSTG −65 to +150 °C
Maximum Junction Temperature TJ MAX +150 °C
Operating Junction Temperature Range (Note 3) NCP3063
NCP3063B, NCV3063
TJ0 to +70
−40 to +125
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pin 1−8: Human Body Model 2000 V per AEC Q100−002; 003 or JESD22/A114; A115
Machine Model Method 200 V
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
3. The relation between junction temperature, ambient temperature and Total Power dissipated in IC is TJ = TA + Rq • PD
4. The pins which are not defined may not be loaded by external signals
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ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TJ = Tlow to Thigh [Note 5], unless otherwise specified)
Symbol Characteristic Conditions Min Typ Max Unit
OSCILLATOR
fOSC Frequency (VPin 5 = 0 V, CT = 2.2 nF,
TJ = 25°C)
110 150 190 kHz
IDISCHG /
ICHG
Discharge to Charge Current Ratio (Pin 7 to VCC, TJ = 25°C) 5.5 6.0 6.5 −
IDISCHG Capacitor Discharging Current (Pin 7 to VCC, TJ = 25°C) 1650 mA
ICHG Capacitor Charging Current (Pin 7 to VCC, TJ = 25°C) 275 mA
VIPK(Sense) Current Limit Sense Voltage (TJ = 25°C) (Note 6) 165 200 235 mV
OUTPUT SWITCH (Note 7)
VSWCE(DROP) Darlington Switch Collector to
Emitter Voltage Drop
(ISW = 1.0 A, Pin 2 to GND,
TJ = 25°C) (Note 7)
1.0 1.3 V
IC(OFF) Collector Off−State Current (VCE = 40 V) 0.01 100 mA
COMPARATOR
VTH Threshold Voltage TJ = 25°C 1.250 V
NCP3063 −1.5 +1.5 %
NCP3063B, NCV3063 −2 +2 %
REGLiNE Threshold Voltage Line Regulation (VCC = 5.0 V to 40 V) −6.0 2.0 6.0 mV
ICII in Input Bias Current (Vin = Vth)−1000 −100 1000 nA
TOTAL DEVICE
ICC Supply Current (VCC = 5.0 V to 40 V,
CT = 2.2 nF, Pin 7 = VCC,
VPin 5 > Vth, Pin 2 = GND,
remaining pins open)
7.0 mA
Thermal Shutdown Threshold 160 °C
Hysteresis 10 °C
5. NCP3063: Tlow = 0°C, Thigh = +70°C;
NCP3063B, NCV3063: Tlow = −40°C, Thigh = +125°C
6. The VIPK(Sense) Current Limit Sense Voltage is specified at static conditions. In dynamic operation the sensed current turn−off value depends
on comparator response time and di/dt current slope. See the Operating Description section for details.
7. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.
8. NCV prefix is for automotive and other applications requiring site and change control.
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Figure 5. Oscillator Frequency vs. Oscillator
Timing Capacitor
Figure 6. Oscillator Frequency vs. Supply
Voltage
Ct, CAPACITANCE (nF) VCC, SUPPLY VOLTAGE (V)
402925161273
110
120
130
150
160
170
180
190
Figure 7. Emitter Follower Configuration Output
Darlington Switch Voltage Drop vs. Temperature
Figure 8. Common Emitter Configuration Output
Darlington Switch Voltage Drop vs. Temperature
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
150100500−50
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
150100500−50
1.0
1.05
1.10
1.15
1.20
1.25
Figure 9. Emitter Follower Configuration Output
Darlington Switch Voltage Drop vs. Emitter Current
Figure 10. Common Emitter Configuration
Output Darlington Switch Voltage Drop vs.
Collector Current
IE, EMITTER CURRENT (A) IC, COLLECTOR CURRENT (A)
1.51.00.50
1.0
1.1
1.2
1.3
1.5
1.7
1.8
2.0
1.51.00.50
0.5
0.6
0.7
0.8
0.9
1.1
1.4
1.5
FREQUENCY (kHz)
FREQUENCY (kHz)
21 34 38
140
CT = 2.2 nF
TJ = 25°C
VOLTAGE DROP (V)
VCC = 5.0 V
IE = 1 A
VOLTAGE DROP (V)
VCC = 5.0 V
IC = 1 A
VOLTAGE DROP (V)
VOLTAGE DROP (V)
1.4
1.6
1.9
1.0
1.3
1.2
VCC = 5.0 V
TJ = 25°C
VCC = 5.0 V
TJ = 25°C
0
50
100
150
200
250
300
350
400
450
0 1 2 3 4 5 6 7 8 9 10 11 12 1314 15161718 1920
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Figure 11. Comparator Threshold Voltage vs.
Temperature
Figure 12. Current Limit Sense Voltage vs.
Temperature
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
1259535205−25−40
1.20
1.22
1.24
1.26
1.28
1.30
12550355−10−25−40
0.10
0.12
0.14
0.18
0.20
0.22
0.28
0.30
Figure 13. Standby Supply Current vs. Supply Voltage
VCC, SUPPLY VOLTAGE (V)
3833288.03.0
2.0
2.5
3.0
3.5
4.5
5.0
5.5
6.0
Vth, COMPARATOR THRESHOLD VOLTAGE (V)
Vipk(sense), CURRENT LIMIT SENSE
VOLTAGE (V)
20 95 110
0.16
ICC, SUPPLY CURRENT (mA)
CT = 2.2 nF
Pin 5, 7 = VCC
Pin 2 = GND
−10 806550 110
0.26
0.24
65 80
13 18 23 43
4.0
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INTRODUCTION
The NCP3063 is a monolithic power switching regulator
optimized for dc to dc converter applications. The
combination of its features enables the system designer to
directly implement step−up, step−down, and voltage−
inverting converters with a minimum number of external
components. Potential applications include cost sensitive
consumer products as well as equipment for industrial
markets. A representative block diagram is shown in
Figure 4.
Operating Description
The NCP3063 is a hysteretic, dc−dc converter that uses a
gated oscillator to regulate output voltage. In general, this
mode of operation is somewhat analogous to a capacitor
charge pump and does not require dominant pole loop
compensation for converter stability. The Typical Operating
Waveforms are shown in Figure 14. The output voltage
waveform shown is for a step−down converter with the
ripple and phasing exaggerated for clarity. During initial
converter startup, the feedback comparator senses that the
output voltage level is below nominal. This causes the
output switch to turn on and off at a frequency and duty cycle
controlled by the oscillator, thus pumping up the output filter
capacitor. When the output voltage level reaches nominal,
the output switch next cycle turning on is inhibited. The
feedback comparator will enable the switching immediately
when the load current causes the output voltage to fall below
nominal. Under these conditions, output switch conduction
can be enabled for a partial oscillator cycle, a partial cycle
plus a complete cycle, multiple cycles, or a partial cycle plus
multiple cycles. (See AN920/D for more information).
Oscillator
The oscillator frequency and off−time of the output switch
are programmed by the value selected for timing capacitor
CT. Capacitor CT is charged and discharged by a 1 to 6 ratio
internal current source and sink, generating a positive going
sawtooth waveform at Pin 3. This ratio sets the maximum
tON/(tON + tOFF) of the switching converter as 6/(6 + 1) or
0.857 (typical) The oscillator peak and valley voltage
difference is 500 mV typically. To calculate the CT capacitor
value for required oscillator frequency, use the equations
found in Figure 15. An Excel based design tool can be found
at www.onsemi.com on the NCP3063 product page.
Figure 14. Typical Operating Waveforms
1
0
Output Switch
1
0
On
Off
Feedback Comparator Output
Nominal Output Voltage Level
Startup Operation
Output Voltage
Timing Capacitor, CT
IPK Comparator Output
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8
Peak Current Sense Comparator
With a voltage ripple gated converter operating under
normal conditions, output switch conduction is initiated by
the Voltage Feedback comparator and terminated by the
oscillator. Abnormal operating conditions occur when the
converter output is overloaded or when feedback voltage
sensing is lost. Under these conditions, the Ipk Current Sense
comparator will protect the Darlington output Switch. The
switch current is converted to a voltage by inserting a
fractional ohm resistor, RSC, in series with VCC and the
Darlington output switch. The voltage drop across RSC is
monitored by the Current Sense comparator. If the voltage
drop exceeds 200 mV with respect to VCC, the comparator
will set the latch and terminate output switch conduction on
a cycle−by−cycle basis. This Comparator/Latch
configuration ensures that the Output Switch has only a
single on−time during a given oscillator cycle.
Real
Vturn−off on
Rs Resistor
t_delay
I1
Io
di/dt slope I through the
Darlington
Switch
Vipk(sense)
The VIPK(Sense) Current Limit Sense Voltage threshold is
specified at static conditions. In dynamic operation the
sensed current turn−off value depends on comparator
response time and di/dt current slope.
Real Vturn−off on Rsc resistor
Vturn_off +Vipk(sense) )Rs @(t_delay @dińdt)
Typical Ipk comparator response time t_delay is 350 ns.
The di/dt current slope is growing with voltage difference on
the inductor pins and with decreasing inductor value.
It is recommended to check the real max peak current in
the application at worst conditions to be sure that the max
peak current will never get over the 1.5 A Darlington Switch
Current max rating.
Thermal Shutdown
Internal thermal shutdown circuitry is provided to protect
the IC in the event that the maximum junction temperature
is exceeded. When activated, typically at 160°C, the Output
Switch is disabled. The temperature sensing circuit is
designed with 10°C hysteresis. The Switch is enabled again
when the chip temperature decreases to at least 150°C
threshold. This feature is provided to prevent
catastrophic failures from accidental device
overheating. It is not intended to be used as a
replacement for proper heatsinking.
Output Switch
The output switch is designed in a Darlington
configuration. This allows the application designer to
operate at all conditions at high switching speed and low
voltage drop. The Darlington Output Switch is designed to
switch a maximum of 40 V collector to emitter voltage and
current up to 1.5 A.
APPLICATIONS
Figures 16 through 24 show the simplicity and flexibility
of the NCP3063. Three main converter topologies are
demonstrated with actual test data shown below each of the
circuit diagrams.
Figure 15 gives the relevant design equations for the key
parameters. Additionally, a complete application design aid
for the NCP3063 can be found at www.onsemi.com.
Figures 25 through 31 show typical NCP3063
applications with external transistors. This solution helps to
increase output current and helps with efficiency still
keeping low cost bill of materials. Typical schematics of
boost configuration with NMOS transistor, buck
configuration with PMOS transistor and buck configuration
with LOW VCE(sat) PNP are shown.
Another advantage of using the external transistor is
higher operating frequency which can go up to 250 kHz.
Smaller size of the output components such as inductor and
capacitor can be used then.
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(See Notes 9, 10, 11) Step−Down Step−Up Voltage−Inverting
ton
toff
Vout )VF
Vin *VSWCE *Vout
Vout )VF*Vin
Vin *VSWCE
|Vout|)VF
Vin *VSWCE
ton ton
toff
fǒton
toff )1Ǔ
ton
toff
fǒton
toff )1Ǔ
ton
toff
fǒton
toff )1Ǔ
CTCT+381.6 @10*6
fosc *343 @10*12
IL(avg) Iout Iout ǒton
toff )1ǓIout ǒton
toff )1Ǔ
Ipk (Switch) IL(avg) )DIL
2IL(avg) )DIL
2IL(avg) )DIL
2
RSC 0.20
Ipk (Switch)
0.20
Ipk (Switch)
0.20
Ipk (Switch)
LǒVin *VSWCE *Vout
DILǓton ǒVin *VSWCE
DILǓton ǒVin *VSWCE
DILǓton
Vripple(pp)
DILǒ1
8fCOǓ2
)(ESR)2
Ǹ[ton Iout
CO)DIL@ESR [ton Iout
CO)DIL@ESR
Vout VTHǒR2
R1)1ǓVTHǒR2
R1)1ǓVTHǒR2
R1)1Ǔ
9. VSWCE − Darlington Switch Collector to Emitter Voltage Drop, refer to Figures 7, 8, 9 and 10.
10.VF − Output rectifier forward voltage drop. Typical value for 1N5819 Schottky barrier rectifier is 0.4 V.
11. The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio.
The Following Converter Characteristics Must Be Chosen:
Vin − Nominal operating input voltage.
Vout − Desired output voltage.
Iout − Desired output current.
DIL − Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that DIL be chosen to be
less than 10% of the average inductor current IL(avg). This will help prevent Ipk (Switch) from reaching the current limit threshold
set by RSC. If the design goal is to use a minimum inductance value, let DIL = 2(IL(avg)). This will proportionally reduce
converter output current capability.
f − Maximum output switch frequency.
Vripple(pp) − Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low
value since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR)
electrolytic designed for switching regulator applications.
Figure 15. Design Equations
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Figure 16. Typical Buck Application Schematic
J204
GND
1
J203
1
C203
2.2 nF
C202
C205
C206
C201
R202
U201
NCP3063
5
36
4
8
7
1
2
COMP
TCAP
GND
N.C. SWC
SWE
R203
R201
0R15
D201
1N5819
J202
GND
1
J201
1
L201
+VIN = +12 V
0.1 mF
2K4 ±1%
3K9 ±1%
220 mF / 50 V
+0.1 mF470 mF / 25 V
+
+VOUT = +3.3 V / 800 mA
VCC
IPK
47 mH
Value of Components
Name Value
L201 47 mH, Isat > 1.5 A
D201 1 A, 40 V Schottky Rectifier
C202 220 mF, 50 V, Low ESR
C205 470 mF, 25 V, Low ESR
C203 2.2 nF Ceramic Capacitor
Name Value
R201 150 mW, 0.5 W
R202 2.40 kW
R203 3.90 kW
C201 100 nF Ceramic Capacitor
C202 100 nF Ceramic Capacitor
Test Results
Test Condition Results
Line Regulation Vin = 9 V to 12 V, Io = 800 mA 8 mV
Load Regulation Vin = 12 V, Io = 80 mA to 800 mA 9 mV
Output Ripple Vin = 12 V, Io = 40 mA to 800 mA ≤ 85 mVpp
Efficiency Vin = 12 V, Io = 400 mA to 800 mA > 73%
Short Circuit Current Vin = 12 V, Rload = 0.15 W1.25 A
Figure 17. Buck Demoboard Layout
Figure 18. Efficiency vs. Output Current for the Buck
Demo Board at Vin = 12 V, Vout = 3.3 V, TA = 255C
OUTPUT LOAD (Adc)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
EFFICIENCY (%)
76
74
72
70
68
66
64
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Figure 19. Typical Boost Application Schematic
J104
GND
1
J103
1
C103
2.2 nF
C102
C105
C106
C101
R102
U101
NCP3063
5
36
4
8
7
1
2
COMP
TCAP
GND
N.C. SWC
SWE
R103
R101
0R15
D101 1N5819
J102
GND
1
J101
1
L101
+VIN = +12 V
0.1 mF
1K0 ±1%
18K0 ±1%
470 mF / 25 V
+0.1 mF330 mF / 50 V
+
+VOUT = +24 V / 350 mA
VCC
IPK
100 mH
Value of Components
Name Value
L101 100 mH, Isat > 1.5 A
D101 1 A, 40 V Schottky Rectifier
C102 470 mF, 25 V, Low ESR
C105 330 mF, 50 V, Low ESR
C103 2.2 nF Ceramic Capacitor
Name Value
R101 150 mW, 0.5 W
R102 1.00 kW
R103 18.00 kW
C101 100 nF Ceramic Capacitor
C106 100 nF Ceramic Capacitor
Test Results
Test Condition Results
Line Regulation Vin = 9 V to 15 V, Io = 250 mA 2 mV
Load Regulation Vin = 12 V, Io = 30 mA to 350 mA 5 mV
Output Ripple Vin = 12 V, Io = 10 mA to 350 mA ≤ 350 mVpp
Efficiency Vin = 12 V, Io = 50 mA to 350 mA > 85.5%
Figure 20. Boost Demoboard Layout
Figure 21. Efficiency vs. Output Current for the Boost
Demo Board at Vin = 12 V, Vout = 24 V, TA = 255C
OUTPUT LOAD (Adc)
0 0.05 0.1 0.15 0.2 0.3 0.4
EFFICIENCY (%)
90
85
84
83
82
81
80
0.25 0.35
89
88
87
86
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Figure 22. Typical Voltage Inverting Application Schematic
J504
GND
1J503
1
C503
2.2 nF
C502
C501
R502
U501
NCP3063
5
36
4
8
7
1
2
COMP
TCAP
GND
N.C. SWC
SWE
R503
R501
0R15
L501
J502
GND
1
J501
1
+VIN = +5 V
0.1 mF
16K9 ±1%
1K96 ±1%
330 mF / 25 V
+22 mH
VOUT = −12 V / 100 mA
VCC
IPK
D501
C505
470 mF / 35 V
+
C506
0.1 mF
1N5819
Value of Components
Name Value
L501 22 mH, Isat > 1.5 A
D501 1 A, 40 V Schottky Rectifier
C502 330 mF, 25 V, Low ESR
C505 470 mF, 35 V, Low ESR
C503 2.2 nF Ceramic Capacitor
Name Value
R501 150 mW, 0.5 W
R502 16.9 kW
R503 1.96 kW
C501 100 nF Ceramic Capacitor
C506 100 nF Ceramic Capacitor
Test Results
Test Condition Results
Line Regulation Vin = 4.5 V to 6 V, Io = 50 mA 1.5 mV
Load Regulation Vin = 5 V, Io = 10 mA to 100 mA 1.6 mV
Output Ripple Vin = 5 V, Io = 0 mA to 100 mA ≤ 300 mVpp
Efficiency Vin = 5 V, Io = 100 mA 49.8%
Short Circuit Current Vin = 5 V, Rload = 0.15 W0.885 A
Figure 23. Voltage Inverting Demoboard Layout Figure 24. Efficiency vs. Output Current for the
Voltage Inverting Demo Board at Vin = +5 V,
Vout = −12 V, TA = 255C
OUTPUT LOAD (mAdc)
8040200
36
38
40
44
46
48
50
52
EFFICIENCY (%)
60 100
42
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Figure 25. Typical Boost Application Schematic with External NMOS Transistor
IC1 NCP3063
5
36
4
8
7
1
2
R4
VIN = 8 − 18 V/0.6 A VOUT = 31 V/0.35 A
+
COMP
TC
GND
N.C. SWC
SWE
VCC
IPK
1k
1N5819
D1
R3
M18
C2
100n
C1
0V GND
C6
100n
C7
R8
1k
C4
1n2
C5 6n8
R7
470
R5 24k
C3 10n
R2 1k
R1 82m 10m
L1
6
2
5
1
4
3
G
D
S
Q1
NTD18N06
IC2 BC846BPD
330m330m
Figure 26. Typical Efficiency for Application
Shown in Figure 25.
70
72
74
76
78
80
82
84
86
6 8 10 12 14 16 18 20
70
72
74
76
78
80
82
84
86
6 8 10 12 14 16 18 20
EFFICIENCY (%)
INPUT VOLTAGE (V)
ILOAD = 350 mA
External transistor is recommended in applications where
wide input voltage ranges and higher power is required. The
suitable schematic with an additional NMOS transistor and
its driving circuit is shown in the Figure 25. The driving
circuit is controlled from SWE Pin of the NCP3063 through
frequency compensated resistor divider R7/R8. The driver
IC2 is ON Semiconductor low cost dual NPN/PNP
transistor BC846BPD. Its NPN transistor is connected as a
super diode for charging the gate capacitance. The PNP
transistor works as an emitter follower for discharging the
gate capacitor. This configuration assures sharp driving
edge between 50 − 100 ns as well as it limits power
consumption of R7/R8 divider down to 50 mW. The output
current limit is balanced by resistor R3. The fast switching
with low RDS(on) NMOS transistor will achieve efficiencies
up to 85% in automotive applications.
NCP3063, NCP3063B, NCV3063
http://onsemi.com
14
Figure 27. Typical Buck Application Schematic with External PMOS Transistor
IC1 NCP3063
5
36
4
8
7
1
2
R3
VIN = 8 − 19 V VOUT = 3V3/3 A
+
COMP
TC
GND
N.C. SWC
SWE
VCC
IPK
1k
C2
100n
C1
0V GND
C6
100n
C7
R8
470
C5
2n2
R6
22k
R2 1k7
R1 50m 10m
L1
6
1
Q2
NTGS4111P
C4
6n8
R5
1k
D1
1N5822
+
4
3
2
5
T1
BC848CPD
330m330m
60
65
70
75
80
85
90
95
100
0 0.5 1 1.5 2 2.5
3
Figure 28. NCP3063 Efficiency vs. Output Current for
Buck External PMOS at Vout = 3.3 V, f = 220 kHz,
TA = 255C
EFFICIENCY (%)
OUTPUT LOAD (Adc)
VIN = 8 V
VIN = 18 V
Figure 27 shows typical buck configuration with external
PMOS transistor. The principle of driving the Q2 gate is the
same as shown in Figure 27.
Resistor R6 connected between TC and SWE pin provides
a pulsed feedback voltage. It is recommended to use this
pulsed feedback approach on applications with a wide input
voltage range, applications with the input voltage over
+12 V or applications with tighter specifications on output
ripple. The suitable value of resistor R6 is between
10k − 68k. The pulse feedback approach increases the
operating frequency by about 20%. It also creates more
regular switching waveforms with constant operating
frequency which results in lower output ripple voltage and
improved efficiency.
The pulse feedback resistor value has to be selected so that
the capacitor charge and discharge currents as listed in the
electrical characteristic table, are not exceeded. Improper
selection will lead to errors in the oscillator operation. The
maximum voltage at the TC Pin cannot exceed 1.4 V when
implementing pulse feedback.
NCP3063, NCP3063B, NCV3063
http://onsemi.com
15
Figure 29. Typical Buck Application Schematic with External Low VCE(sat) PNP Transistor
IC1 NCP3063
5
36
4
8
7
1
2
R2
VIN = 8 − 19 V VOUT = 3V3/1 A
+
COMP
TC
GND
N.C. SWC
SWE
VCC
IPK
1k
C2
100n
C1
0V GND
C5
100n
C6
C3
2n2
R5
33
R3 1k7
R1
150m
33m
L1
Q1 NSS35200
D2
NSR0130
+
R4
33
D1
1N5819 100m100m
50
55
60
65
70
75
80
85
90
95
100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Figure 30. NCP3063 Efficiency vs. Output Current for
External Low VCE(sat) at Vin = +5 V, f = 160 kHz,
TA = 255C
EFFICIENCY (%)
OUTPUT LOAD (Adc)
Typical application of the buck converter with external
bipolar transistor is shown in the Figure 29. It is an ideal
solution for configurations where the input and output
voltage difference is small and high efficiency is required.
NSS35200, the low VCE(sat) transistor from
ON Semiconductor will be ideal for applications with 1 A
output current, the input voltages up to 15 V and operating
frequency 100 − 150 kHz. The switching speed could be
improved by using desaturation diode D2.
NCP3063, NCP3063B, NCV3063
http://onsemi.com
16
Figure 31. Typical Schematic of Buck Converter with RC Snubber and Pulse Feedback
IC1 NCP3063
5
36
4
8
7
1
2
R3
COMP
TC
GND
N.C. SWC
SWE
VCC
IPK
C1
0V 0V
C4
C2
R5
22k
R2
R1
L1
D1C3
R4
4n7
10R
In some cases where there are oscillations on the output
due to the input/output combination, output load variations
or PCB layout a snubber circuit on the SWE Pin will help
minimize the oscillation. Typical usage is shown in the
Figure 31. C3 values can be selected between 2.2 nF and
6.8 nF and R4 can be from 10 W to 22 W.
ORDERING INFORMATION
Device Package Shipping†
NCP3063PG PDIP−8
(Pb−Free)
50 Units / Rail
NCP3063BPG PDIP−8
(Pb−Free)
50 Units / Rail
NCP3063BMNTXG DFN−8
(Pb−Free)
4000 / Tape & Reel
NCP3063DR2G SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP3063BDR2G SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP3063MNTXG DFN−8
(Pb−Free)
4000 / Tape & Reel
NCV3063PG PDIP−8
(Pb−Free)
50 Units / Rail
NCV3063DR2G SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCV3063MNTXG DFN−8
(Pb−Free)
4000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCV prefix is for automotive and other applications requiring site and change control.
NCP3063, NCP3063B, NCV3063
http://onsemi.com
17
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
NCP3063, NCP3063B, NCV3063
http://onsemi.com
18
PACKAGE DIMENSIONS
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC - IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
14
58
F
NOTE 2 −A−
−B−
−T−
SEATING
PLANE
H
J
G
DK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M--- 10 --- 10
N0.76 1.01 0.030 0.040
__
8 LEAD PDIP
CASE 626−05
ISSUE L
NCP3063, NCP3063B, NCV3063
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19
PACKAGE DIMENSIONS
8 PIN DFN, 4x4
CASE 488AF−01
ISSUE C
ÉÉ
ÉÉ
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. DETAILS A AND B SHOW OPTIONAL
CONSTRUCTIONS FOR TERMINALS.
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.25 0.35
D4.00 BSC
D2 1.91 2.21
E4.00 BSC
E2 2.09 2.39
e0.80 BSC
K0.20 −−−
L0.30 0.50
D
B
E
C0.15
A
C0.15
2X
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Ç
Ç
ÇÇ
Ç
Ç
Ç
Ç
ÇÇ
ÇÇ
Ç
C
A
(A3)
A1
8X
SEATING
PLANE
C0.08
C0.10
Ç
Ç
Ç
Ç
ÇÇ
Ç
e
8X L
K
E2
D2
b
NOTE 3
14
58
8X
0.10 C
0.05 C
AB
PIN ONE
REFERENCE
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
8X
0.63
2.21
2.39
8X
0.80
PITCH
4.30
0.35
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
ÉÉÉ
ÉÉÉ
ÇÇÇ
A1
A3
L
ÇÇÇ
ÇÇÇ
ÉÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
L1 −−− 0.15
DETAIL B
NOTE 4
DETAIL A
DIMENSIONS: MILLIMETERS
PACKAGE
OUTLINE
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
NCP3063/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
