Quad Channel, High Speed
Digital Isolators
Data Sheet ADuM3440/ADuM3441/ADuM3442
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Low power operation
5 V operation
1.7 mA per channel maximum @ 0 Mbps to 2 Mbps
68 mA per channel maximum @ 150 Mbps
3.3 V operation
1.0 mA per channel maximum @ 0 Mbps to 2 Mbps
33 mA per channel maximum @ 150 Mbps
Bidirectional communication
3.3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 150 Mbps (NRZ)
Precise timing characteristics
5 ns maximum pulse width distortion
5 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
APPLICATIONS
High speed multichannel isolation
SPI interface/data converter isolation
Instrumentation
FUNCTIONAL BLOCK DIAGRAMS
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
VDD1
GND1
VIA
VIB
VIC
VID
NC
GND1
VDD2
GND2
VOA
VOB
VOC
VOD
VE2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
06837-001
ADuM3440
Figure 1. ADuM3440 Functional Block Diagram
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
VDD1
GND1
VIA
VIB
VIC
VOD
VE1
GND1
VDD2
GND2
VOA
VOB
VOC
VID
VE2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
06837-002
ADuM3441
Figure 2. ADuM3441 Functional Block Diagram
DECODE ENCODE
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
VDD1
GND1
VIA
VIB
VOC
VOD
VE1
GND1
VDD2
GND2
VOA
VOB
VIC
VID
VE2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
06837-003
ADuM3442
Figure 3. ADuM3442 Functional Block Diagram
GENERAL DESCRIPTION
The ADuM344x1 are four channel, digital isolators based on the
Analog Devices, Inc., iCoupler® technology supporting data rates
up to 150 Mbps. Combining high speed CMOS and monolithic
air core transformer technology, these isolation components
provide outstanding performance characteristics superior to
alternatives such as optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler
devices remove the design difficulties commonly associated
with optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with these iCoupler products.
Furthermore, iCoupler devices consume one-tenth to one-sixth
the power of optocouplers at comparable signal data rates.
The ADuM344x isolators provide four independent isolation
channels in a variety of channel configurations (see the
Ordering Guide). The ADuM344x operates with the supply
voltage on either side ranging from 3.0 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling
voltage translation functionality across the isolation barrier. In
addition, the ADuM344x provides low pulse width distortion
and tight channel-to-channel matching. Unlike other opto-
coupler alternatives, the ADuM344x isolators have a patented
refresh feature that ensures dc correctness in the absence of
input logic transitions and during the power-up/power-down
condition.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
ADuM3440/ADuM3441/ADuM3442 Data Sheet
Rev. D | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3.3 V Operation ............................ 5
Electrical Characteristics—Mixed 5 V/3.3 V or 3.3 V/5 V
Operation ....................................................................................... 7
Package Characteristics ............................................................. 10
Regulatory Information ............................................................. 10
Insulation and Safety-Related Specifications .......................... 10
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 11
Recommended Operating Conditions .................................... 11
Absolute Maximum Ratings ......................................................... 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions ......................... 13
Typical Performance Characteristics ........................................... 16
Applications Information .............................................................. 18
PC Board Layout ........................................................................ 18
Propagation Delay-Related Parameters ................................... 18
System-Level ESD Considerations and Enhancements ........ 18
DC Correctness and Magnetic Field Immunity........................... 18
Power Consumption .................................................................. 19
Insulation Lifetime ..................................................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
2/12—Rev. C to Rev. D
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section ................................................................. 1
Change to PC Board Layout Section ............................................ 18
Updated Outline Dimensions ....................................................... 21
1/09—Rev. B to Rev. C
Change to Propagation Delay Parameter (Table 1) ...................... 3
Change to Propagation Delay Parameter (Table 2) ...................... 5
Change to Propagation Delay Parameter (Table 3) ...................... 8
9/08—Rev. A to Rev. B
Changes to Pulse Width Distortion, |tPLH − tPHL| Parameter and
Channel-to-Channel Matching, Codirectional Channels
Parameter, Table 1 ............................................................................. 3
Changes to Pulse Width Distortion, |tPLH − tPHL| Parameter and
Channel-to-Channel Matching, Codirectional Channels
Parameter, Table 2 ............................................................................. 5
Changes to Pulse Width Distortion, |tPLH − tPHL| Parameter and
Channel-to-Channel Matching, Codirectional Channels
Parameter, Table 3 ............................................................................. 8
5/08—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 21
11/07—Rev. 0: Initial Version
Data Sheet ADuM3440/ADuM3441/ADuM3442
Rev. D | Page 3 of 24
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications
apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.75 1.3 mA
Output Supply Current per Channel, Quiescent I
DDO (Q)
0.5 1.2 mA
ADuM3440, Total Supply Current, Four Channels1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
3 3.9 mA DC to 1 MHz logic signal frequency
VDD2 Supply Current IDD2 (Q) 2 3 mA DC to 1 MHz logic signal frequency
150 Mbps
VDD1 Supply Current
IDD1 (150)
120
220
mA
75 MHz logic signal frequency
VDD2 Supply Current IDD2 (150) 47 55 mA 75 MHz logic signal frequency
ADuM3441, Total Supply Current, Four Channels
1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
2.8
3.6
mA
DC to 1 MHz logic signal frequency
VDD2 Supply Current IDD2 (Q) 2.3 2.9 mA DC to 1 MHz logic signal frequency
150 Mbps
V
DD1
Supply Current I
DD1 (150)
101 165 mA 75 MHz logic signal frequency
VDD2 Supply Current IDD2 (150) 65 80 mA 75 MHz logic signal frequency
ADuM3442, Total Supply Current, Four Channels
1
DC to 2 Mbps
V
DD1
or V
DD2
Supply Current I
DD1 (Q)
, I
DD2 (Q)
2.5 3.5 mA DC to 1 MHz logic signal frequency
150 Mbps
VDD1 or VDD2 Supply Current
IDD1 (150), IDD2 (150)
83
130
mA
75 MHz logic signal frequency
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 µA 0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 ≤ V
E1
, V
E2
≤ V
DD1
or V
DD2
Logic High Input Threshold VIH, VEH 2.0 V
Logic Low Input Threshold
V
IL
, V
EL
0.8 V
Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
(VDD1 or
VDD2) − 0.1
5.0 V IOx = −20 µA, VIx = VIxH
(VDD1 or
V
DD2
) − 0.4
4.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL,
V
OCL
, V
ODL
0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.04 0.1 V IOx = 400 µA, VIx = VIxL
0.2 0.4 V I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
Minimum Pulse Width2 PW 6.67 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate3 150 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 32 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6
tPSK
12
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels5
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels5
tPSKOD 5 ns CL = 15 pF, CMOS signal levels
ADuM3440/ADuM3441/ADuM3442 Data Sheet
Rev. D | Page 4 of 24
Parameter Symbol Min Typ Max Unit Test Conditions
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
F
2.5 ns C
L
= 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output7
|CMH| 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output7
|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel
8
I
DDI (D)
0.196 mA/Mbps
Output Dynamic Supply Current per Channel8 I
DDO (D)
0.1 mA/Mbps
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3440/ADuM3441/ADuM3442 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDO. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Data Sheet ADuM3440/ADuM3441/ADuM3442
Rev. D | Page 5 of 24
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent I
DDI (Q)
0.43 0.90 mA
Output Supply Current per Channel, Quiescent I
DDO (Q)
0.3 0.60 mA
ADuM3440, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.7 2.4 mA DC to 1 MHz logic signal frequency
V
DD2
Supply Current I
DD2 (Q)
1.2 1.7 mA DC to 1 MHz logic signal frequency
150 Mbps
VDD1 Supply Current IDD1 (150) 63 110 mA 75 MHz logic signal frequency
V
DD2
Supply Current I
DD2 (150)
17 25 mA 75 MHz logic signal frequency
ADuM3441, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.6 2.2 mA DC to 1 MHz logic signal frequency
V
DD2
Supply Current I
DD2 (Q)
1.3 1.9 mA DC to 1 MHz logic signal frequency
150 Mbps
VDD1 Supply Current IDD1 (150) 52 80 mA 75 MHz logic signal frequency
V
DD2
Supply Current I
DD2 (150)
29 40 mA 75 MHz logic signal frequency
ADuM3442, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 or VDD2 Supply Current IDD1 (Q), IDD2 (Q) 1.5 2.0 mA DC to 1 MHz logic signal frequency
150 Mbps
VDD1 or VDD2 Supply Current IDD1 (150), IDD2 (150) 40 66 mA 75 MHz logic signal frequency
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 µA 0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
V
IH
, V
EH
1.6 V
Logic Low Input Threshold V
IL
, V
EL
0.4 V
Logic High Output Voltages VOAH, VOBH,
V
OCH
, V
ODH
(VDD1 or
V
DD2
) − 0.1
3.0 V IOx = −20 µA, VIx = VIxH
(VDD1 or
VDD2) − 0.4
2.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
V
OAL
, V
OBL
,
VOCL, VODL
0.0
0.1
V
I
Ox
= 20 µA, V
Ix
= V
IxL
0.04 0.1 V I
Ox
= 400 µA, V
Ix
= V
IxL
0.2 0.4 V I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
Minimum Pulse Width2 PW 6.67 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate
3
150 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay4 t
PHL
, t
PLH
20 36 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
16 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels5
t
PSKOD
5
ns
C
L
= 15 pF, CMOS signal levels
ADuM3440/ADuM3441/ADuM3442 Data Sheet
Rev. D | Page 6 of 24
Parameter Symbol Min Typ Max Unit Test Conditions
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
F
3 ns C
L
= 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output7
|CMH| 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output7
|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per Channel
8
I
DDI (D)
0.076 mA/Mbps
Output Dynamic Supply Current per Channel8 I
DDO (D)
0.028 mA/Mbps
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3440/ADuM3441/ADuM3442 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDO. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Data Sheet ADuM3440/ADuM3441/ADuM3442
Rev. D | Page 7 of 24
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OR 3.3 V/5 V OPERATION
All voltages are relative to their respective ground. 5 V/3.3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation:
3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range,
unless otherwise noted. All typical specifications are at TA = 25°C; VDD1 = 3.3 V, VDD2 = 5 V or VDD1 = 5 V, V DD2 = 3.3 V.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q)
5 V/3.3 V Operation
0.75
1.3
mA
3.3 V/5 V Operation 0.43 0.9 mA
Output Supply Current per Channel, Quiescent I
DDO (Q)
5 V/3.3 V Operation 0.3 0.7 mA
3.3 V/5 V Operation 0.5 1.2 mA
ADuM3440, Total Supply Current, Four Channels
1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
5 V/3.3 V Operation 3 3.9 mA DC to 1 MHz logic signal frequency
3.3 V/5 V Operation 1.7 2.4 mA DC to 1 MHz logic signal frequency
V
DD2
Supply Current I
DD2 (Q)
5 V/3.3 V Operation 1.2 1.7 mA DC to 1 MHz logic signal frequency
3.3 V/5 V Operation 2 3 mA DC to 1 MHz logic signal frequency
150 Mbps
VDD1 Supply Current IDD1 (150)
5 V/3.3 V Operation 120 220 mA 75 MHz logic signal frequency
3.3 V/5 V Operation 63 110 mA 75 MHz logic signal frequency
VDD2 Supply Current IDD2 (150)
5 V/3.3 V Operation
17
25
mA
75 MHz logic signal frequency
3.3 V/5 V Operation 47 55 mA 75 MHz logic signal frequency
ADuM3441, Total Supply Current, Four Channels
1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
5 V/3.3 V Operation 2.8 3.6 mA DC to 1 MHz logic signal frequency
3.3 V/5 V Operation 1.6 2.2 mA DC to 1 MHz logic signal frequency
V
DD2
Supply Current I
DD2 (Q)
5 V/3.3 V Operation 1.3 1.9 mA DC to 1 MHz logic signal frequency
3.3 V/5 V Operation 2.3 2.9 mA DC to 1 MHz logic signal frequency
150 Mbps
VDD1 Supply Current IDD1 (150)
5 V/3.3 V Operation
101
165
mA
75 MHz logic signal frequency
3.3 V/5 V Operation 52 80 mA 75 MHz logic signal frequency
V
DD2
Supply Current I
DD2 (150)
5 V/3.3 V Operation 29 40 mA 75 MHz logic signal frequency
3.3 V/5 V Operation 65 80 mA 75 MHz logic signal frequency
ADuM3442, Total Supply Current, Four Channels
1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
5 V/3.3 V Operation 2.5 3.5 mA DC to 1 MHz logic signal frequency
3.3 V/5 V Operation 1.5 2.0 mA DC to 1 MHz logic signal frequency
VDD2 Supply Current IDD2 (Q)
5 V/3.3 V Operation 1.5 2.0 mA DC to 1 MHz logic signal frequency
3.3 V/5 V Operation 2.5 3.5 mA DC to 1 MHz logic signal frequency
ADuM3440/ADuM3441/ADuM3442 Data Sheet
Rev. D | Page 8 of 24
Parameter Symbol Min Typ Max Unit Test Conditions
150 Mbps
V
DD1
Supply Current I
DD1 (150)
5 V/3.3 V Operation 83 130 mA 75 MHz logic signal frequency
3.3 V/5 V Operation 40 66 mA 75 MHz logic signal frequency
V
DD2
Supply Current I
DD2 (150)
5 V/3.3 V Operation 40 66 mA 75 MHz logic signal frequency
3.3 V/5 V Operation 83 130 mA 75 MHz logic signal frequency
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 µA 0 ≤ VIA,VIB, VIC,VID ≤ VDD1 or VDD2,
0 ≤
V
E1
,V
E2
≤
V
DD1
or V
DD2
Logic High Input Threshold
VIH, VEH
5 V/3.3 V Operation 2.0 V
3.3 V/5 V Operation 1.6 V
Logic Low Input Threshold V
IL
, V
EL
5 V/3.3 V Operation 0.8 V
3.3 V/5 V Operation
0.4
V
Logic High Output Voltages VOAH, VOBH,
V
OCH
, V
ODH
(VDD1 or
V
DD2
) − 0.1
(VDD1 or
V
DD2
)
V IOx = −20 µA, VIx = VIxH
(VDD1 or
VDD2) − 0.4
(VDD1 or
VDD2) − 0.2
V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
V
OAL
, V
OBL
,
V
OCL
, V
ODL
0.0
0.1
V
I
Ox
= 20 µA, V
Ix
= V
IxL
0.04 0.1 V I
Ox
= 400 µA, V
Ix
= V
IxL
0.2 0.4 V I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
Minimum Pulse Width2 PW 6.67 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate
3
150 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay4 t
PHL
, t
PLH
20 35 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|
4
PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK
15 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels6
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels5
tPSKOD 5 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
CL = 15 pF, CMOS signal levels
5 V/3 V Operation 3.0 ns
3 V/5 V Operation 2.5 ns
Common-Mode Transient Immunity
at Logic High Output7
|CMH| 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output7
|CM
L
|
25
35
kV/µs
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate f
r
5 V/3.3 V Operation 1.2 Mbps
3.3 V/5 V Operation
1.1
Mbps
Input Dynamic Supply Current per Channel8 IDDI (D)
5 V/3.3 V Operation 0.196 mA/Mbps
3.3 V/5 V Operation 0.076 mA/Mbps
Output Dynamic Supply Current per Channel8 IDDO (D)
5 V/3.3 V Operation 0.028 mA/Mbps
3.3 V/5 V Operation 0.01 mA/Mbps
Data Sheet ADuM3440/ADuM3441/ADuM3442
Rev. D | Page 9 of 24
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3440/ADuM3441/ADuM3442 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDO. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
ADuM3440/ADuM3441/ADuM3442 Data Sheet
Rev. D | Page 10 of 24
PACKAGE CHARACTERISTICS
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input to Output)1
RI-O
1012
Ω
Capacitance (Input to Output)
1
C
I-O
2.2 pF f = 1 MHz
Input Capacitance
2
C
I
4.0 pF
IC Junction-to-Case Thermal Resistance, Side 1 θ
JCI
33 °C/W Thermocouple located at
center of package underside
IC Junction-to-Case Thermal Resistance, Side 2 θ
JCO
28 °C/W
1 The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM344x is approved by the organizations listed in Table 5. Refer to Table 10 and the Insulation Lifetime section for details
regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 5.
UL CSA VDE
Recognized under
1577 component recognition program1
Approved under
CSA Component Acceptance Notice #5A
Certified according to
DIN V VDE V 0884-10 (VDE V 0884-10):2006-122
Single protection,
2500 V rms isolation voltage
Basic insulation per CSA 60950-1-03 and
IEC 60950-1, 800 V rms (1131 V peak)
maximum working voltage
Reinforced insulation, 560 V peak
Reinforced insulation per CSA 60950-1-03
and IEC 60950-1, 400 V rms (566 V peak)
maximum working voltage
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM344x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).
2 In accordance with DIN V VDE V 0884-10, each ADuM344x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection
limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration
Minimum External Air Gap (Clearance) L(I01) 7.7 min mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(I02) 8.1 min mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Data Sheet ADuM3440/ADuM3441/ADuM3442
Rev. D | Page 11 of 24
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval.
Table 7.
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage V
IORM
560 V peak
Input-to-Output Test Voltage, Method B1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VPR 1050 V peak
Input-to-Output Test Voltage, Method A V
IORM
× 1.6 = V
PR
, t
m
= 60 sec, partial discharge < 5 pC V
PR
After Environmental Tests Subgroup 1 896 V peak
After Input and/or Safety Test
Subgroup 2 and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak
Highest Allowable Overvoltage Transient overvoltage, t
TR
= 10 seconds V
TR
4000 V peak
Safety-Limiting Values Maximum value allowed in the event of a failure
(see Figure 4)
Case Temperature T
S
150 °C
Side 1 Current I
S1
265 mA
Side 2 Current I
S2
335 mA
Insulation Resistance at T
S
V
IO
= 500 V R
S
>109 Ω
CASE TEMPERATURE (°C)
SAF E TY-LI M ITING CURRE NT (mA)
0
0
350
300
250
200
150
100
50
50 100 150 200
SI DE #1
SI DE #2
06837-004
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 8.
Parameter Rating
Operating Temperature Range, T
A
−40°C to +105°C
Supply Voltage Range, V
DD1
, V
DD2
1 3.0 V to 5.5 V
Input Signal Rise and Fall Time 1.0 ms
1 All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on immunity to external
magnetic fields.
ADuM3440/ADuM3441/ADuM3442 Data Sheet
Rev. D | Page 12 of 24
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 9.
Parameter Rating
Storage Temperature Range (T
ST
) −65°C to +150°C
Ambient Operating Temperature Range (T
A
) −40°C to +105°C
Supply Voltages (V
DD1
, V
DD2
)
1
−0.5 V to +7.0 V
Input Voltage (VIA, VIB, VIC, VID, VE1, VE2)1, 2 −0.5 V to V
DD1
+ 0.5 V
Output Voltage (VOA, VOB, VOC, VOD)1, 2 −0.5 V to V
DDO
+ 0.5 V
Average Output Current per Pin3
Side 1 (I
O1
) −18 mA to +18 mA
Side 2 (I
O2
) −22 mA to +22 mA
Common-Mode Transients (CMH, CML)4 −100 kV/µs to
+100 kV/µs
1 All voltages are relative to their respective ground.
2 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PC Board Layout section.
3 See Figure 4 for maximum rated current values for various temperatures.
4 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the Absolute Maximum Ratings can cause latch-
up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Table 10. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime
AC Voltage, Unipolar Waveform
Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1
Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1
Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 11. Truth Table (Positive Logic)
VIX Input1
VEX Input2
VDDI State1
VDDO State1
VOX Output1
Notes
H H or NC Powered Powered H
L H or NC Powered Powered L
X L Powered Powered Z
X H or NC Unpowered Powered H Outputs return to the input state within 1 µs of V
DDI
power restoration.
X L Unpowered Powered Z
X X Powered Unpowered
Indeterminate Outputs return to the input state within 1 µs of VDDO power
restoration if VEX state is H or NC. Outputs return to high impedance
state within 8 ns of VDDO power restoration if VEX state is L.
1 VIX and VOX refer to the input and output signals of a given channel (A, B, C, or D). VEX refers to the output enable signal on the same side as the VOX outputs. VDDI and
VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
2 In noisy environments, connecting VEX to an external logic high or low is recommended.
Data Sheet ADuM3440/ADuM3441/ADuM3442
Rev. D | Page 13 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD1 1
GND
1
*
2
V
IA 3
V
IB 4
V
DD2
16
GND
2
*
15
V
OA
14
V
OB
13
V
IC 5
V
OC
12
V
ID 6
V
OD
11
NC
7
V
E2
10
GND
1
*
8
GND
2
*
9
NC = NO CONNECT
ADuM3440
TOP VI EW
(No t t o Scal e)
*PI N 2 AND P IN 8 ARE I NTERNALLY CONNECTED AND CO NNE CTI NG BO TH TO
GND
1
IS RE COMME NDE D. PIN 9 AND PI N 15 ARE INT E RNALLY CONNECTED AND
CONNECTING BOTH TO GND
2
IS RECOMMENDED.
06837-005
Figure 5. ADuM3440 Pin Configuration
Table 12. ADuM3440 Pin Function Descriptions
Pin No. Mnemonic Description
1 V
DD1
Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V.
2, 8 GND
1
Ground 1. Ground reference for Isolator Side 1.
3 V
IA
Logic Input A.
4 V
IB
Logic Input B.
5 V
IC
Logic Input C.
6 V
ID
Logic Input D.
7 NC No Connect.
9, 15 GND
2
Ground 2. Ground reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected.
VOA, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external
logic high or low is recommended.
11 V
OD
Logic Output D.
12 V
OC
Logic Output C.
13 V
OB
Logic Output B.
14 V
OA
Logic Output A.
16 V
DD2
Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V.
ADuM3440/ADuM3441/ADuM3442 Data Sheet
Rev. D | Page 14 of 24
V
DD1 1
GND
1
*
2
V
IA 3
V
IB 4
V
DD2
16
GND
2
*
15
V
OA
14
V
OB
13
V
IC 5
V
OC
12
V
OD 6
V
ID
11
V
E1 7
V
E2
10
GND
1
*
8
GND
2
*
9
ADuM3441
TOP VI EW
(No t t o Scal e)
*PI N 2 AND P IN 8 ARE I NTERNALLY CONNECTED AND CO NNE CTI NG BO TH TO
GND
1
IS RE COMME NDE D. PIN 9 AND PI N 15 ARE INT E RNALLY CONNECTED AND
CONNECTING BOTH TO GND
2
IS RECOMMENDED.
06837-006
Figure 6. ADuM3441 Pin Configuration
Table 13. ADuM3441 Pin Function Descriptions
Pin No. Mnemonic
Description
1 V
DD1
Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V.
2, 8
GND1
Ground 1. Ground reference for Isolator Side 1.
3 V
IA
Logic Input A.
4 V
IB
Logic Input B.
5 V
IC
Logic Input C.
6 V
OD
Logic Output D.
7 VE1 Output Enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled
when V
E1
is low. In noisy environments, connecting V
E1
to an external logic high or low is recommended.
9, 15
GND2
Ground 2. Ground reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA,
VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or
low is recommended.
11 V
ID
Logic Input D.
12 V
OC
Logic Output C.
13 V
OB
Logic Output B.
14 V
OA
Logic Output A.
16 V
DD2
Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V.
Data Sheet ADuM3440/ADuM3441/ADuM3442
Rev. D | Page 15 of 24
V
DD1 1
GND
1
*
2
V
IA 3
V
IB 4
V
DD2
16
GND
2
*
15
V
OA
14
V
OB
13
V
OC 5
V
IC
12
V
OD 6
V
ID
11
V
E1 7
V
E2
10
GND
1
*
8
GND
2
*
9
ADuM3442
TOP VI EW
(No t t o Scal e)
*PI N 2 AND P IN 8 ARE I NTERNALLY CONNECTED AND CO NNE CTI NG BO TH TO
GND
1
IS RE COMME NDE D. PIN 9 AND PI N 15 ARE INT E RNALLY CONNECTED AND
CONNECTING BOTH TO GND
2
IS RECOMMENDED.
06837-007
Figure 7. ADuM3442 Pin Configuration
Table 14. ADuM3442 Pin Function Descriptions
Pin No. Mnemonic Function
1 V
DD1
Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V.
2, 8 GND
1
Ground 1. Ground reference for Isolator Side 1.
3 V
IA
Logic Input A.
4 V
IB
Logic Input B.
5 V
OC
Logic Output C.
6
VOD
Logic Output D.
7 VE1 Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected. VOC and
VOD outputs are disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is
recommended.
9, 15 GND
2
Ground 2. Ground reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected. VOA and
VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is
recommended.
11 V
ID
Logic Input D.
12 V
IC
Logic Input C.
13 V
OB
Logic Output B.
14
VOA
Logic Output A.
16 V
DD2
Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V.
ADuM3440/ADuM3441/ADuM3442 Data Sheet
Rev. D | Page 16 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
DATA RATE (M bp s)
0
0
35
50 100 150
5V
3.3V
15
20
25
30
10
5
06837-008
CURRENT/CHANNEL (mA)
Figure 8. Typical Input Supply Current per Channel vs. Data Rate
for 5 V and 3.3 V Operation
DATA RATE (M bp s)
CURRENT /CHANNEL ( mA)
050 100 150
5V
3.3V
06837-009
0
2
4
6
8
10
12
14
Figure 9. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3.3 V Operation (No Output Load)
DATA RATE (M bp s)
CURRENT /CHANNEL ( mA)
0
050 100 150
5V
3.3V
06837-010
0
2
4
6
8
10
12
14
16
18
20
Figure 10. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3.3 V Operation (15 pF Output Load)
DATA RATE (M bp s)
CURRENT ( mA)
0
0
140
50 100 150
5V
3.3V
60
80
100
120
40
20
06837-011
Figure 11. Typical ADuM3440 VDD1 Supply Current vs. Data Rate
for 5 V and 3.3 V Operation
DATA RATE (M bp s)
CURRENT ( mA)
050 100 150
5V
3.3V
06837-012
0
5
10
15
20
25
30
35
40
45
50
Figure 12. Typical ADuM3440 VDD2 Supply Current vs. Data Rate
for 5 V and 3.3 V Operation
DATA RATE (M bp s)
CURRENT ( mA)
0
0
120
50 100 150
5V
3.3V
06837-013
20
40
60
80
100
Figure 13. Typical ADuM3441 VDD1 Supply Current vs. Data Rate
for 5 V and 3.3 V Operation
Data Sheet ADuM3440/ADuM3441/ADuM3442
Rev. D | Page 17 of 24
DATA RATE (M bp s)
CURRENT ( mA)
0
0
70
50 100 150
5V
3.3V
40
50
60
30
20
10
06837-014
Figure 14. Typical ADuM3441 VDD2 Supply Current vs. Data Rate
for 5 V and 3.3 V Operation
DATA RATE (M bp s)
CURRENT ( mA)
0
0
90
50 100 150
5V
3.3V
70
80
60
40
50
30
20
10
06837-015
Figure 15. Typical ADuM3442 VDD1 or VDD2 Supply Current vs.Data Rate
for 5 V and 3.3 V Operation
ADuM3440/ADuM3441/ADuM3442 Data Sheet
Rev. D | Page 18 of 24
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM344x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 16). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16
for VDD2. The capacitor value should be between 0.01 μF and 0.1 μF.
The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm. Bypassing
between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should
be considered unless the ground pair on each package side is
connected close to the package.
V
DD1
GND
1
V
IA
V
IB
V
IC/OC
V
ID/OD
V
E1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC/IC
V
OD/ID
V
E2
GND
2
0
6837-017
Figure 16. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isolation
barrier is minimized. Furthermore, the board layout should be
designed such that any coupling that does occur equally affects
all pins on a given component side. Failure to ensure this could
cause voltage differentials between pins exceeding the device’s
absolute maximum ratings, thereby leading to latch-up or
permanent damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output may differ from the propagation
delay to a logic high.
INPUT (
V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
06837-018
Figure 17. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM344x component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM344x
components operating under the same conditions.
SYSTEM-LEVEL ESD CONSIDERATIONS AND
ENHANCEMENTS
System-level ESD reliability (for example, per IEC 61000-4-x)
is highly dependent on system design, which varies widely by
application. The ADuM344x incorporate many enhancements
to make ESD reliability less dependent on system design. The
enhancements include the following:
ESD protection cells added to all input/output interfaces.
Key metal trace resistances reduced using wider geometry
and paralleling of lines with vias.
The SCR effect inherent in CMOS devices is minimized by
the use of guarding and isolation techniques between
PMOS and NMOS devices.
Areas of high electric field concentration eliminated using
45° corners on metal traces.
Supply pin overvoltage prevented with larger ESD clamps
between each supply pin and its respective ground.
While the ADuM344x improve system-level ESD reliability,
they are no substitute for a robust system-level design. See the
AN-793 application note, ESD/Latch-Up Considerations with
iCoupler Isolation Products for detailed recommendations on
board layout and system-level design.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than ~1 μs, a periodic set
of refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses of more than about 5 μs, the input side is assumed
unpowered or nonfunctional, in which case the isolator output
is forced to a default state (see the Absolute Maximum Ratings
section) by the watchdog timer circuit.
The limitation on the magnetic field immunity of the ADuM344x
is set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this can occur. The 3 V operating condition of the
ADuM344x is examined because it represents the most susceptible
mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
thus establishing a 0.5 V margin in which induced voltages can
be tolerated.
Data Sheet ADuM3440/ADuM3441/ADuM3442
Rev. D | Page 19 of 24
The voltage induced across the receiving coil is given by
V = (−dβ/dt)∑ πrn
2; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM344x and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 18.
MAG NE TIC FI E LD FRE QUENCY ( Hz )
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY ( kgau ss)
0.001 1M
10
0.01
1k 10k 10M
0.1
1
100M100k
06837-019
Figure 18. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V—still well above the 0.5 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM344x transformers. Figure 19 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown, the ADuM344x is extremely immune
and can be affected only by extremely large currents operated
at high frequency very close to the component. For the 1 MHz
example noted, one would have to place a 0.5 kA current 5 mm
away from the ADuM344x to affect the component’s operation.
MAG NE TIC FI E LD FRE QUENCY ( Hz )
MAXIMUM ALL OWABLE CURRE NT (kA)
1000
100
10
1
0.1
0.011k 10k 100M100k 1M 10M
DIS TANCE = 5mm
DIS TANCE = 1m
DIS TANCE = 100mm
06837-020
Figure 19. Maximum Allowable Current
for Various Current-to-ADuM344x Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce error voltages sufficiently large enough to trigger
the thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM344x
isolator is a function of the supply voltage, the channel’s data
rate, and the channel’s output load.
For each input channel, the supply current is given by
IDDI = IDDI (Q) f ≤ 0.5 fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5 fr
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5 fr
IDDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half of the input
data rate expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. Figure 8 and Figure 9
provide per-channel supply currents as a function of data rate
for an unloaded output condition. Figure 10 provides per-
channel supply current as a function of data rate for a 15 pF
output condition. Figure 11 through Figure 15 provide total
VDD1 and VDD2 supply current as a function of data rate for
ADuM3440/ADuM3441/ADuM3442 channel configurations.
ADuM3440/ADuM3441/ADuM3442 Data Sheet
Rev. D | Page 20 of 24
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM344x.
Analog Devices performs accelerated life testing using voltage levels
higher than the rated continuous working voltage. Acceleration
factors for several operating conditions are determined. These
factors allow calculation of the time to failure at the actual working
voltage. The values shown in Figure 20 summarize the peak voltage
for 50 years of service life for a bipolar ac operating condition, and
the maximum CSA/VDE approved working voltages. In many
cases, the approved working voltage is higher than the 50-year
service life voltage. Operation at these high working voltages
can lead to shortened insulation life in some cases.
The insulation lifetime of the ADuM344x depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 20, Figure 21, and Figure 22 illustrate these
different isolation voltage waveforms.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the maximum working voltage recommended by
Analog Devices.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower, which allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 10 can be applied while maintaining the
50-year minimum lifetime provided the voltage conforms to
either the unipolar ac or dc voltage cases. Any cross insulation
voltage waveform that does not conform to Figure 21 or Figure 22
should be treated as a bipolar ac waveform and its peak voltage
should be limited to the 50-year lifetime voltage value listed in
Table 10.
Note that the voltage presented in Figure 21 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
0V
RATED P E AK V OL TAG E
06837-021
Figure 20. Bipolar AC Waveform
0V
RATED P E AK V OL TAG E
06837-022
Figure 21. Unipolar AC Waveform
0V
RATED P E AK V OL TAG E
06837-023
Figure 22. DC Waveform
Data Sheet ADuM3440/ADuM3441/ADuM3442
Rev. D | Page 21 of 24
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 23. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1, 2
Number of
Inputs,
V
DD1
Side
Number of
Inputs,
V
DD2
Side
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay, 5 V (ns)
Maximum
Pulse Width
Distortion (ns)
Temperature
Range
Package
Description
Package
Option
ADuM3440CRWZ 4 0 150 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM3441CRWZ 3 1 150 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM3442CRWZ 2 2 150 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16
1 Z = RoHS Compliant Part.
2 Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape-and-reel option.
ADuM3440/ADuM3441/ADuM3442 Data Sheet
Rev. D | Page 22 of 24
NOTES
Data Sheet ADuM3440/ADuM3441/ADuM3442
Rev. D | Page 23 of 24
NOTES
