74HC14-Q100; 74HCT14-Q100 Hex inverting Schmitt trigger Rev. 5 -- 1 December 2015 Product data sheet 1. General description The 74HC14-Q100; 74HCT14-Q100 is a hex inverter with Schmitt-trigger inputs. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Complies with JEDEC standard no. 7A Low-power dissipation ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Applications Wave and pulse shapers Astable multivibrators Monostable multivibrators 74HC14-Q100; 74HCT14-Q100 NXP Semiconductors Hex inverting Schmitt trigger 4. Ordering information Table 1. Ordering information Type number Package 74HC14D-Q100 Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm 74HCT14D-Q100 74HC14PW-Q100 74HCT14PW-Q100 74HC14BQ-Q100 74HCT14BQ-Q100 5. Functional diagram $ < $ < $ < $ < $ < $ < Logic symbol 74HC_HCT14_Q100 Product data sheet PQD Fig 1. $ PQD DDF Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 5 -- 1 December 2015 < Fig 3. Logic diagram (one Schmitt-trigger) (c) NXP Semiconductors N.V. 2015. All rights reserved. 2 of 19 74HC14-Q100; 74HCT14-Q100 NXP Semiconductors Hex inverting Schmitt trigger 6. Pinning information 6.1 Pinning $ WHUPLQDO LQGH[DUHD +&4 +&74 9&& +&4 +&74 < $ $ 9&& $ < < $ < $ $ < $ < $ $ < < < $ *1' < *1' < *1' < $ DDD 7UDQVSDUHQWWRSYLHZ DDD (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 6.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 6A 1, 3, 5, 9, 11, 13 data input 1 1Y to 6Y 2, 4, 6, 8, 10, 12 data output 1 GND 7 ground (0 V) VCC 14 supply voltage 7. Functional description Table 3. Function table[1] Input Output nA nY L H H L [1] H = HIGH voltage level; L = LOW voltage level. 74HC_HCT14_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 3 of 19 74HC14-Q100; 74HCT14-Q100 NXP Semiconductors Hex inverting Schmitt trigger 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V - 20 mA - 20 mA - 25 mA 50 mA IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current 0.5 V < VO < VCC + 0.5 V ICC supply current - IGND ground current 50 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot SO14, TSSOP14 and DHVQFN14 packages [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC14-Q100 Min Typ 74HCT14-Q100 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C 74HC_HCT14_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 4 of 19 74HC14-Q100; 74HCT14-Q100 NXP Semiconductors Hex inverting Schmitt trigger 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Min Typ Max Min Max Min Max IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V 74HC14-Q100 VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT VI = VT+ or VT II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 2.0 - 20 - 40 A CI input capacitance - 3.5 - - - - - pF IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V IO = 20 A; - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; - 0.15 0.26 - 0.33 - 0.4 V 74HCT14-Q100 VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT; VCC = 4.5 V VI = VT+ or VT; VCC = 4.5 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 A ICC additional supply current per input pin; VI = VCC 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V - 30 108 - 135 - 147 A CI input capacitance - 3.5 - - - - - pF 74HC_HCT14_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 5 of 19 74HC14-Q100; 74HCT14-Q100 NXP Semiconductors Hex inverting Schmitt trigger 11. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 7. Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) VCC = 2.0 V - 41 125 155 190 ns VCC = 4.5 V - 15 25 31 38 ns VCC = 5.0 V; CL = 15 pF - 12 - - - ns - 12 21 26 32 ns VCC = 2.0 V - 19 75 95 110 ns VCC = 4.5 V - 7 15 19 22 ns - 6 13 15 19 ns - 7 - - - pF 74HC14-Q100 tpd propagation delay nA to nY; see Figure 6 [1] VCC = 6.0 V tt transition time [2] see Figure 6 VCC = 6.0 V CPD power dissipation capacitance per package; VI = GND to VCC [3] 74HCT14-Q100 tpd tt CPD propagation delay nA to nY; see Figure 6 transition time power dissipation capacitance [1] VCC = 4.5 V - 20 34 43 51 ns VCC = 5.0 V; CL = 15 pF - 17 - - - ns VCC = 4.5 V; see Figure 6 [2] - 7 15 19 22 ns per package; VI = GND to VCC 1.5 V [3] - 8 - - - pF [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 74HC_HCT14_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 6 of 19 74HC14-Q100; 74HCT14-Q100 NXP Semiconductors Hex inverting Schmitt trigger 12. Waveforms 9, 90 Q$LQSXW 90 *1' W 3+/ W 3/+ 92+ 90 90 Q