DM74S280NX - Fairchild Semiconductor

August 1986

Revised May 2000

DM74S280 9-Bit Parity Generator/Checker

DM74S280

9-Bit Parity Generator/Chec ker

General Description

These universal, nin e-bit parity gener ators/checkers utilize

Schottky-cl a mp ed TTL hi gh -pe rfo rm anc e ci rcu itry, and fe a-

ture odd/even outputs to facilitate operation of either odd or

even parity applications. T he word-leng th capability is ea s-

ily expanded by cascading.

The DM74S280 can be use d to upgrade the performance

of most systems utilizing the DM74180 parity generator/

checker. Although the DM74S280 is implemented without

expander i nputs, the correspo nding funct ion is provid ed by

the availability of all input at pin 4, an d no internal connec-

tion at pin 3. This p ermi ts the DM 74S280 t o be substitut ed

for the 180 in existing designs to produce an identical func-

tion, even if DM74S280’s are mixed with existing 180’s.

Input buffers are provided so that each input represents

only one normal 74S load, and full fan-out to 10 normal

Series 74S loads is available from each of the outputs at

low logic levels. A fan-out to 20 normal Series 74S loads is

provided at high logic levels, to facilitate connection of

unused inputs to used inputs.

Features

■Generates either odd or even parity for nine data lines

■Cascadable for N-bits

■Can be used to upgrade existing systems using MSI par-

ity circuits

■Typical data-to-output delay—14 ns

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er “X” to the ordering code.

Connection Diagram Function Table

Order Number Package Number Package Description

DM74S280M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74S280N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Number of Inputs Outputs

(A Thru I) that are HIGH ∑Even ∑Odd

0, 2, 4, 6, 8 H L

1, 3, 5, 7, 9 L H

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DM74S280

Logic Diagram

Typical Applications

Three DM74S280’s can be used to implement a 25-line

parity generator/checker. This arrangement will provide

parity in typically 25 ns. (See Figure 1.)

Longer word lengths can be implemented by cascading

DM74S280’s. As shown in Figure 2, parity can be gener-

ated for word lengths up to 81 bits in typically 25 ns.

FIGURE 1. 25-Line Parity/Generator Checker FIGURE 2. 81-Line Parity/Generator Checker

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DM74S280

Absolute Maximum Ratings(Note 1) Note 1: The “Absolute Maximum Ratings” are those valu es b eyo nd w hich

the saf ety of the device cannot be gu aranteed. Th e device shou ld not be

operated at these limits. The parametric values defined in the Electrical

Char ac teristi c s tables are not guar ant eed at t he ab s olute maxi m um ratings.

The “R ecomm ended Ope rating Co ndition s” table will define the condit ions

for actu al device operation.

Recommended Operating Conditions

Electri cal Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 2: All typ icals are at VCC = 5V, TA = 25°C.

Note 3: Not more than one out put shou ld be shorte d at a t im e, and the duration sh ould not ex c eed one s ec ond.

Note 4: ICC is measured with all inputs grounded and all outputs OPEN.

Switching Characteristics

at VCC = 5V and TA = 25°C

Supply Voltage 7V

Input Voltage 5.5V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Curr en t −1mA

IOL LOW Level Output Current 20 mA

TAFree Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

(Note 2)

VIInput Clamp Voltage VCC = Min, II=−18 mA −1.2 V

VOH HIGH Level VCC = Min, IOH = Max 2.7 3.4 V

Output Voltage VIL = Max, VIH = Min

VOL LOW Level VCC = Min, IOL =Max 0.5 V

Output Voltage VIH = Min, VIL = Max

IIInput Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA

IIH HIGH Level Input Current VCC = Max, VI = 2.7V 50 µA

IIL LOW Level Input Current VCC = Max, VI = 0.5V −2mA

IOS Short Circuit Output Current VCC = Max (Note 3) −40 −100 mA

ICC Supply Current VCC Max (Note 4) 67 105 mA

RL = 280ΩRL = 280Ω

Symbol Parameter From (Input) CL = 15 pF CL = 50 pF Units

To (Output) Min Max Min Max

tPLH Propagation Delay Time Data to ∑ Even 21 24 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time Data to ∑ Even 18 21 ns

HIGH-to-LOW Level Output

tPLH Propagation Delay Time Data to ∑ Odd 21 24 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time Data to ∑ Odd 18 21 ns

HIGH-to-LOW Level Output

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DM74S280

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

Package Number M14A

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DM74S280 9-Bit Parity Generator/Checker

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume an y responsibility for u se of any circuitry d escribed, no circu it patent licenses are im plied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.