DS1216C-3.3V - Hytronics - Datasheet.Directory

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FEATURES

 Keeps track of hundredths of seconds,

seconds, minutes, hours, days, date of the

month, months, and years

 Converts standard 2k x 8 up to 512k x 8

CMOS static RAMs into nonvolatile memory

 Embedded lithium energy cell maintains

watch information and retains RAM data

 Watch function is transparent to RAM

operation

 Month and year determine the number of days

in each month; leap year compensation valid

up to 2100

 Lithium energy source is electrically

disconnected to retain freshness until power is

applied for the first time

 Proven gas–tight socket contacts

 Full ±10% operating range

 Operating temperature range 0°C to 70°C

 Accuracy is better than ±1 minute/month @

25°C

ORDERING INFORMATION ( 5V)

DS1216B, DS1216C, DS1216D, DS1216H

ORDERING INFORMATION (3.3V)

DS1216B-3.3V, DS1216C-3.3V,

DS1216D-3.3V, DS1216H-3.3V

PIN DESCRIPTION DS1216B &

DS1216C

Pin 1 RST - RESET

Pin 11 DQ0 - Data Input/Output 0

Pin 14 GND - Ground

Pin 20 CE - Conditioned Chip Enable

Pin 22 OE - Output Enable

Pin 27 WE - Write Enable

Pin 28 VCC - Switched VCC

(DS1216B only)

Pin 26 Vcc - Switched Vcc for 24-pin RAM

DS1216

SmartWatch/RAM

DS1216B, DS1216C, DS1216D and DS1216H

www.dalsemi.com

28-Pin Intelligent Socket

Vcc

(B)

DQ0

GND

RST 1 28 VCC

DS1216

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PIN DESCRIPTION FOR DS1216D AND DS1216H

All pins pass through except 22 and 32.

Pin 1 RST - RESET

Pin 13 DQ0 - Data Input/Output

Pin 16 GND - Ground

Pin 22 CE - Conditioned Chip Enable

Pin 24 OE - Output Enable

Pin 29 WE - Write Enable

Pin 32 VCC - Switched VCC for 32-pin RAM

( DS1216D only)

(Pin 30 Vcc - Switched Vcc for 28-Pin RAM)

DESCRIPTION

The DS1216 SmartWatch/RAM Sockets are 600-mil wide DIP sockets with a built–in CMOS watch

function, a nonvolatile RAM controller circuit, and an embedded lithium energy source. The sockets

provide a NV RAM solution for memory sized from 2k x8 to 512k x 8 with package sizes from 26 pin to

32 pins. When a socket is mated with a CMOS SRAM, it provides a complete solution to problems

associated with memory volatility and uses a common energy source to maintain time and date. A key

feature of the SmartWatch is that the watch function remains transparent to the RAM. The SmartWatch

monitors VCC for an out–of–tolerance condition. When such a condition occurs, an internal lithium energ y

source is automatically switched on and write protection is unconditionally enabled to prevent loss of

watch and RAM data.

Using the SmartWatch saves PC board space since the combination of SmartWatch and the mated RAM

take up no more area than the memory alone. The SmartWatch uses the Vcc, Data I/O 0, CE , OE , and

WE for RAM and watch control. All other pins are passed straight through to the socket receptacle.

The SmartWatch provides timekeeping information including hundredths of seconds, seconds, minutes,

hours, day, date, month, and year information. The date at the end of the month is automaticall y adjusted

for months with less than 31 days, including correction for leap years. The SmartWatch operates in either

24–hour or 12–hour format with an AM/PM indicator.

OPERATION

Communication with the SmartWatch is established by pattern recognition on a serial bit stream of 64 bits

which must be matched by executing 64 consecutive write c ycles containing the proper data on DQ0. All

accesses which occur prior to recognition of the 64–bit pattern are directed to memory.

After recognition is established, the next 64 read or write cycles either extract or update data in the

SmartWatch, and memory access is inhibited.

30 (Vcc D)

VCC

GND

DQ0

RST

32-Pin Intelligent Socket

DS1216

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Data transfer to and from the timekeepin g function is accomplished with a serial bit stream under control

of Chip Enable (CE ), Output Enable (OE ), and Write Enable (WE). Initially, a read cycle to any memory

location using theCE and OE control of the SmartWatch starts the pattern recognition sequence by

moving a pointer to the first bit of the 64–bit comparison register. Next, 64 consecutive write cycles are

executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain

access to the SmartWatch. Therefore, any address to the memory in the socket is acceptable. However,

the write cycles generated to gain access to the SmartWatch are also writing data to a location in the

mated RAM. The preferred way to manage this requirement is to set aside just one address location in

RAM as a SmartWatch scratch pad. When the first write cycle is ex ecuted, it is compared to bit 0 of the

64–bit comparison register. If a match is found, the pointer increments to the next location of the

comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance

and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,

the present sequence is aborted and the comparison register pointer is reset. Pattern r ecognition continues

for a total of 64 write cycles as described above until all the bits in the comparison register have been

matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is

enabled and data transfer to or from the timekeeping registers can pro ceed. The next 64 cycles will cause

the SmartWatch to either receive or transmit data on DQ0, depending on the level of the OE pin or the

WE pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without

interrupting the pattern recognition sequence or data transfer sequence to the SmartWatch.

SMARTWATCH COMPARISON REGISTER DEFINI TION Figure 1

NOTE:

The pattern recognition in Hex is C5, 3A, 5C, C5, 3A, A3, 5C. The odds of this pattern accidentally

duplicating and causi n g inadvert ent entry to the SmartW atch a re less than 1 i n 1019. This pattern is sent to

the SmartWatch LSB to MSB.

110001 01

001110 10

101000 11

010111 00

110001 01

001110 10

101000 11

010111 00

BYTE 0

BYTE 1

BYTE 2

BYTE 3

BYTE 4

BYTE 5

BYTE 6

BYTE 7

HEX

VALUE

7 0

DS1216

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NONVOLATILE CONTROLLER OPERATION

The DS1216 SmartWatch performs circuit functions r equired to make a CMOS RAM nonvolatile. First, a

switch is provided to direct power from the battery or VCC supply, depending on which voltage is greater.

This switch has a voltage drop of less than 0.2 volts. The second function which the SmartWatch provides

is power–fail detection. Power–fail detection occurs at VTP. The DS1216 constantly monitors the VCC

supply. When VCC goes out of tolerance, a comparator outputs a power–fail signal to the chip enable

logic. The third function accomplishes write protection by holding the chip enable signal to the memory

within 0.2 volts of VCC or battery. During nominal power supply conditions the memory chip enable

signal will track the chip enable signal sent to the socket with a maximum propagation delay of 7 ns for

the 5 volt and 12 ns for the 3.3 volt version.

FRESHNESS SEAL

Each DS1216 is shipped from Dallas Semiconductor with its lithium energy source disconnected,

insuring full energy capacity. When VCC is first applied at a level greater than the lithium energy source is

enabled for battery backup operation.

SMARTWATCH REGISTE R INF OR MATION

The SmartWatch information is contained in eight registers of 8 bits, each of which is sequentially

accessed one bit at a time after the 64–bit pattern recognition sequence has been completed. When

updating the SmartWatch registers, each must be handled in groups of 8 bits. Writing and reading

individual bits within a register could produce erroneous results. These read/ write registers are defined

in Figure 2.

Data contained in the SmartWatch registers is in binary coded decimal format (BCD). Reading and

writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of

AM–PM/12/24 MODE

Bit 7 of the hours register is defined as the 12– or 24–hour mode select bit. When high, the 12–hour

mode is selected. In the 12–hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24–hour

mode, bit 5 is the second 10–hour bit (20–23 hours).

OSCILLATOR AND RESET BITS

Bits 4 and 5 of the day register are us ed to control the RESET and oscillator functions. Bit 4 controls the

RESET (pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET bit

is set to logic 0, a low input on the RESET pin will cause the SmartWatch to abort data transfer without

changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the oscillator is

off. When set to logic 0, the oscillator turns on and the watch becomes operational. These bits are

shipped from the factory set to logic 1.

ZERO BITS

Registers 1,2,3,4,5, and 6 contain one or more bits which will always read logic 0. When writing these

locations, either a logic 1 or 0 is acceptable.

ADDITIONAL INFORMATION

Please see Application Notes 4 and 52 for information regarding optional modifications and utilization of

the Phantom Clock contained within the SmartWatch.

DS1216

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SMARTWATCH REGISTER DEFI NITION Figure 2

0.1 SEC 0.01 SEC

0 10 SEC SECONDS

0 10 MIN MINUTES

12/24 0 10 A/P HR HOUR

0 0 OSC RST 0 DAY

0 0 10 DATE DATE

0 0 0 10 MONTH MONTH

10 YEAR YEAR

00-99

00-59

01-12

01-07

00-23

01-31

01-12

00-99

RANGE (BCD)REGISTER 7 0

7 0

DS1216

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ABSOLUTE MAXIMUM RATINGS*

Voltage on any Pin Relative to Ground –0.3V to +7.0V for 5V

Voltage on any Pin Relative to Ground –0.3V to +3.6V for 3.3V

Operating Temperature 0°C to 70°C

Storage Temperature –40°C to +70°C

Soldering Temperature See J-STD-020A specification (See Note 6)

* This is a stress rating only and functional operation of the d evice at these or an y other conditions abov e

those indicated in the operation sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Vcc pin 5V Supply VCC 4.5 5.0 5.5 V 1, 3

Vcc pin 3 V Supply Vcc 3.0 3.3 3.6 V 1,3

Logic 1 VIH 2.2 VCC + 0.3 V 1, 10

Logic 0 VIL -0.3 +0.8 V 1, 10

DC ELECTRICAL CHARACTERISTICS-5V (0°C to 70°C; VCC = 5.0 ± 10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Vcc Supply ICCI 5 mA 3, 4,5

Vcc Supply Voltage VCCO VCC - 0.2 V 3, 8

Vcc Supply Current ICCO 80 mA 3, 8

Input Leakage IIL -1.0 +1.0 µA4,10,13

Output @ 2.4V IOH -1.0 mA 2

Output @ 0.4V IOL 4.0 mA 2

Write Protection Voltage 5V Vcc VTP 4.25 4.5 V

DS1216

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DC ELECTRICAL CHARACTERISTICS-3.3V (0°C to 70°C; VCC = 3.3 ±10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Vcc Supply ICCI 3.5 mA 3, 4,5

Vcc Supply Voltage VCCO VCC - 0.2 V 3, 8

Vcc Supply Current ICCO 60 mA 3, 8

Input Leakage IIL -1.0 +1.0 µA4,10,13

Output @ 2.4V IOH -1.0 mA 2

Output @ 0.4V IOL 3.0 mA 2

Write Protection Voltage 5V Vcc VTP 2.8 3.0 V

BACKUP POWER CHARACTERISTICS (0°C to 70°C; Vcc<VTP)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

CE Output VOHL VBAT-0.2 V 3

RAM Vcc pin Battery Current IBAT RAM Stby

I +1 ua uA 3

RAM VCC (Battery) Voltage VBAT 2 3 3.6 V 3,15

RAM VCC (Battery) I max Ibmax 10 uA 14

Total Battery Capacity Available Ebat 90 mAH 14

Recover y at Power-Up tREC 2ms

VCC Slew Rate fall tF0µs

CE Pulse Width tCE 1.5 µs7

DS1216

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CAPACITANCE (tA = 25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance CIN 5pF

Output Capacitance COUT 7pF

AC E LECTRICAL CHARAC TER ISTIC S (0°C to 70°C; VCC = 4.5 to 5.5V)

PARAMETER SYMBOL MIN TYPE MAX UNITS NOTES

Read Cycle Time tRC 75 ns

CE Access Time tCO 65 ns

OE Access Time tOE 65 ns

CE To Output Low Z tCOE 6ns

OE To Output Low Z tOEE 6ns

CE To Output High Z tOD 30 ns

OE To Output High Z tODO 30 ns

Read Recovery tRR 15 ns

Write Cycle Time tWC 75 ns

Write Pulse Width tWP 75 ns

Write Recovery tWR 15 ns 11

Data Setup Time tDS 35 ns 12

Data Hold Time tDH 0ns 12

CE Pulse Width tCW 65 ns

RESET Pulse Width tRST 75 ns

CE Propagation Delay tPD 6ns2,9

CE High to Power-Fail tPF 0ns

DS1216

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AC E LECTRICAL CHARAC TER ISTIC S (0°C to 70°C; VCC = 3.3± 10%)

PARAMETER SYMBOL MIN TYPE MAX UNITS NOTES

Read Cycle Time tRC 130 ns

CE Access Time tCO 0 110 ns

OE Access Time tOE 110 ns

CE To Output Low Z tCOE 6ns

OE To Output Low Z tOEE 6ns

CE To Output High Z tOD 45 ns

OE To Output High Z tODO 45 ns

Read Recovery tRR 25 ns

Write Cycle Time tWC 130 ns

Write Pulse Width tWP 110 ns

Write Recovery tWR 25 ns 11

Data Setup Time tDS 50 ns 12

Data Hold Time tDH 0ns 12

CE Pulse Width tCW 110 ns

RESET Pulse Width tRST 130 ns

CE Propagation Delay tPD 12 ns 2,9

CE High to Power-Fail tPF 0ns

DS1216

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TIMING DIAGR AM: RE AD CYCLE TO SMARTWATCH

TIMING DI AGR AM: WRITE CYCLE TO SMARTWATCH

TIMING DIAGRAM: RESET FOR SMARTWATCH

DS1216

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TIMING DI AGRAM: POWER-DOWN

TIMING DI AGRAM: POWER-UP

WARNING:

Under no circumstances are negative undershoots of any amplitude allowed when device is in battery

backup mode. Water washing for flux removal will discharge internal lithium source because exposed

voltage pins are present.

DS1216

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NOTES:

1. All voltages are referenced to ground.

2. Measured with a load as shown in Figure 3.

3. Pin locations are designated “U” when a parameter definition refers to the socket receptacle and “L”

when a parameter definition refers to the socket pin.

4. No memory inserted in the socket.

5. Pin 26L can be connected to VCC or left disconnected at the PC board.

6. SmartWatch sockets can be successfully processed through some conventional wave–soldering

techniques as long as temperature exposure to the lithium energy source contained within does not

exceed +85°C. However, post solder cleaning with water washing techniques is not permissible.

Discharge to the lithium energy source may result, even if de-ionized water is utilized. It is equally

imperative that ultrasonic vibration is not used in order to avert damage to the quartz crystal re sonator

employ ed by the oscillator circuit.

7. tCE max. must be met to ensure data integrity on power loss.

8. VCC is within nominal limits and a memory is installed in the socket.

9. Input pulse rise and fall times equal 10 ns.

10. Applies to Pins 1 L, 11 L, 20 L, 22 L, and 27 L.

11. tWR is a functions of the latter occurring edge of WE or CE .

12. tDH and tDS are a function of the first occurring edge of WE or CE .

13. RST (Pin 1) has an internal pull–up resistor.

14. Total battery capacity is used to determine the expected lifetime of a DS1216 in battery back mode.

The user should determine the Standby Current of the selected RAM and calculate the expected

lifetime. The maximum (Ibmax) current draw from the DS1216 is 10 ua.

15. The DS1216 products are shipped with backup battery power off. First power up switches backup

battery on to clock and RAM Vcc pin upon power down.

OUTPUT LOAD Figure 3

DS1216

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DS1216 28 SMARTWATCH

PKG

DIM MIN MAX MIN MAX

A IN. 1.390 1.420 1.580 1.620

MM 35.31 36.07 40.13 41.14

B IN. 0.690 0.720 0.690 0.720

MM 17.53 18.29 17.53 18.29

C IN. 0.420 0.470 0.400 0.470

MM 10.67 11.94 10.16 11.94

D IN. 0.035 0.065 0.035 0.065

MM 0.89 1.65 0.89 1.65

E IN. 0.055 0.075 0.055 0.075

MM 1.39 1.90 1.39 1.90

F IN. 0.120 0.160 0.120 0.160

MM 3.04 4.06 3.04 4.06

G IN. 0.090 0.110 0.090 0.110

MM 2.29 2.79 2.29 2.79

H IN. 0.590 0.630 0.590 0.630

MM 14.99 16.00 14.99 16.00

J IN. 0.008 0.012 0.008 0.012

MM 0.20 0.30 0.20 0.30

K IN. 0.015 0.021 0.015 0.021

MM 0.38 0.53 0.38 0.53

L IN. 0.380 0.420 0.380 0.420

MM 9.65 10.67 9.65 10.67

28-PIN 32-PIN