1. General description
The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD) with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily
cascaded for larger LCD applications. The PCF8576D is compatible with most
microprocessors or microcontrollers and communicates via a two-line bidirectional
I2C-bus. Communication overheads are minimized by a display RAM with
auto-incremented addressing, by hardware subaddressing and by display memory
switching (static and duplex drive modes).
AEC-Q100 compliant (PCF8576DH/2 and PCF8576DT/S400/2) for automotive
applications.
2. Features
nSingle chip LCD controller and driver
nSelectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing
nSelectable display bias configuration: static, 1⁄2or 1⁄3
nInternal LCD bias generation with voltage-follower buffers
n40 segment drives:
uUp to twenty 7-segment numeric characters
uUp to ten 14-segment alphanumeric characters
uAny graphics of up to 160 elements
n40 × 4-bit RAM for display data storage
nAuto-incremented display data loading across device subaddress boundaries
nDisplay memory bank switching in static and duplex drive modes
nVersatile blinking modes
nIndependent supplies possible for LCD and logic voltages
nWide power supply range: from 1.8 V to 5.5 V
nWide logic LCD supply range:
uFrom 2.5 V for low-threshold LCDs
uUp to 6.5 V for guest-host LCDs and high-threshold twisted nematic LCDs
nLow power consumption
n400 kHz I2C-bus interface
nMay be cascaded for large LCD applications (up to 2560 elements possible)
nNo external components
nCompatible with chip-on-glass and chip-on-board technology
nManufactured in silicon gate CMOS process
PCF8576D
Universal LCD driver for low multiplex rates
Rev. 09 — 25 August 2009 Product data sheet
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 2 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
3. Ordering information
[1] Chips in tray.
[2] Chips with bumps in tray.
4. Marking
Table 1. Ordering information
Type number Package
Name Description Version
PCF8576DH/2 TQFP64 plastic thin quad flat package, 64 leads;
body 10 ×10 ×1.0 mm SOT357-1
PCF8576DT/2 TSSOP56 plastic thin shrink small outline package, 56 leads;
body width 6.1 mm SOT364-1
PCF8576DT/S400/2 TSSOP56 plastic thin shrink small outline package, 56 leads;
body width 6.1 mm SOT364-1
PCF8576DU/DA/2 PCF8576DU/DA wire bond die; 59 bonding pads; 2.26 × 2.01 × 0.38 mm[1] PCF8576DU/DA
PCF8576DU/2DA/2 PCF8576DU/2DA bare die; 59 bumps; 2.26 × 2.01 × 0.40 mm[2] PCF8576DU/2DA
Table 2. Marking codes
Type number Marking code
PCF8576DH/2 PCF8576DH
PCF8576DT/2 PCF8576DT
PCF8576DT/S400/2 PCF8576DT/S400
PCF8576DU/DA/2 PC8576D-2
PCF8576DU/2DA/2 PC8576D-2
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 3 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
5. Block diagram
Fig 1. Block diagram of PCF8576D
40
001aai900
LCD BIAS
GENERATOR
LCD
VOLTAGE
SELECTOR
PCF8576D
BACKPLANE
OUTPUTS
DISPLAY
CONTROLLER
COMMAND
DECODER WRITE DATA
CONTROL
DISPLAY RAM
40 × 4-BIT
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY
REGISTER
DISPLAY SEGMENT
OUTPUTS
DATA POINTER AND
AUTO INCREMENT
SUBADDRESS
COUNTER
CLOCK SELECT
AND TIMING
OSCILLATOR
INPUT
FILTERS
BLINKER
TIMEBASE
POWER-ON
RESET
I2C-BUS
CONTROLLER
BP0 BP2 BP1 BP3
A2A1A0SA0
SDA
SCL
VDD
OSC
SYNC
CLK
VSS
VLCD
S0 to S39
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 4 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
Top view. For mechanical details, see Figure 24.
Fig 2. Pinning diagram for PCF8576DH/2 (TQFP64)
PCF8576DH
n.c. n.c.
S34 S17
S35 S16
S36 S15
S37 S14
S38 S13
S39 S12
n.c. S11
n.c. S10
SDA S9
SCL S8
SYNC S7
CLK S6
VDD S5
OSC S4
A0 n.c.
A1 S33
A2 S32
SA0 S31
VSS S30
VLCD S29
n.c. S28
n.c. S27
n.c. S26
BP0 S25
BP2 S24
BP1 S23
BP3 S22
S0 S21
S1 S20
S2 S19
S3 S18
001aaf645
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 5 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
Top view. For mechanical details, see Figure 25.
Fig 3. Pinning diagram for PCF8576DT/x (TSSOP56)
PCF8576DT
BP2 BP0
BP1 VLCD
BP3 VSS
S0 SA0
S1 A2
S2 A1
S3 A0
S4 OSC
S5 VDD
S6 CLK
S7 SYNC
S8 SCL
S9 SDA
S10 S39
S11 S38
S12 S37
S13 S36
S14 S35
S15 S34
S16 S33
S17 S32
S18 S31
S19 S30
S20 S29
S21 S28
S22 S27
S23 S26
S24 S25
001aaf646
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 6 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
Top view. C1 and C2 are alignment marks. For mechanical details, see Figure 26 and Figure 27.
Fig 4. Pinning diagram for PCF8576DU/x (bare die)
S25
S26
S27
S28
S29
S30
S31
S32
S33
C2
S4
S6
S5
S7
S9
S10
S8
S11
S12
S13
S15
S14
S16
S17
OSC
A0
SYNC
SCL
CLK
SDA
SDA
SDA
SCL
S39
S38
S36
S37
S35
S34
A2
A1
C1
SA0
VSS
BP2
BP0
VLCD
BP1
BP3
S0
S2
S1
S3
PCF8576DU
VDD
001aag424
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
52
53
54
55
56
57
58
59
1
2
3
4
5
6
7
8
43
44
45
46
47
48
49
S18
S19
S20
S21
S22
S23
S24
36
37
38
39
40
41
42
50
51
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 7 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
6.2 Pin description
[1] The substrate (rear side of the die) is wired to VSS but should not be electrically connected.
7. Functional description
The PCF8576D is a versatile peripheral device designed to interface any
microprocessor or microcontroller with a wide variety of LCDs. It can directly drive any
static or multiplexed LCD containing up to four backplanes and up to 40 segments.
The possible display configurations of the PCF8576D depend on the number of active
backplane outputs required. A selection of display configurations is shown in Table 4. All
of these configurations can be implemented in the typical system shown in Figure 5.
Table 3. Pin description
Symbol Pin Description
PCF8576DH/2 PCF8576DT/x PCF8576DU/x
SDA 10 44 1, 58 and 59 I2C-bus serial data input and output
SCL 11 45 2 and 3 I2C-bus serial clock input
CLK 13 47 5 external clock input or output
VDD 14 48 6 supply voltage
SYNC 12 46 4 cascade synchronization input or
output
OSC 15 49 7 internal oscillator enable input
A0 to A2 16 to 18 50 to 52 8 to 10 subaddress inputs
SA0 19 53 11 I2C-bus address input; bit 0
VSS 20 54 12[1] ground supply voltage
VLCD 21 55 13 LCD supply voltage
BP0, BP2,
BP1, BP3 25 to 28 56, 1, 2, 3 14 to 17 LCD backplane outputs
S0 to S39 29 to 32, 34 to 47,
49 to 64, 2 to 7 4 to 43 18 to 57 LCD segment outputs
n.c. 1, 8, 9, 22 to 24,
33, 48 - - not connected
Table 4. Display configurations
Number of: 7-segment numeric 14-segment numeric Dot matrix
Backplanes Segments Digits Indicator
symbols Characters Indicator
symbols
4 160 20 20 10 20 160 dots (4 × 40)
3 120 15 15 8 8 120 dots (3 × 40)
2 80 10 10 5 10 80 dots (2 × 40)
1 40 5 5 2 12 40 dots (1 × 40)
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 8 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication
channel with the PCF8576D. The internal oscillator is enabled by connecting
pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms
are generated internally. The only other connections required to complete the system are
to the power supplies (VDD, VSS and VLCD) and the LCD panel chosen for the application.
7.1 Power-on reset
At power-on the PCF8576D resets to the following starting conditions:
•All backplane outputs are set to VLCD
•All segment outputs are set to VLCD
•The selected drive mode is: 1:4 multiplex with 1⁄3bias
•Blinking is switched off
•Input and output bank selectors are reset
•The I2C-bus interface is initialized
•The data pointer and the subaddress counter are cleared (set to logic 0)
•Display is disabled
Data transfers on the I2C-bus must be avoided for 1 ms following power-on to allow the
reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of
three impedances connected in series between VLCD and VSS. The middle resistor can be
bypassed to provide a 1⁄2bias voltage level for the 1:2 multiplex configuration. The LCD
voltage can be temperature compensated externally using the supply to pin VLCD.
The resistance of the power lines must be kept to a minimum.
For chip-on-glass applications, due to the Indium Tin Oxide (ITO) track resistance, each supply line
must be routed separately between the chip and the connector.
Fig 5. Typical system configuration
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
tr
2CB
SDA
SCL
OSC
40 segment drives
4 backplanes
LCD PANEL
(up to 160
elements)
PCF8576D
A0 A1 A2 SA0
VDD
VSS
VSS
VDD VLCD
mdb079
R ≤
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 9 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command (see Table 9) from the command decoder. The biasing configurations
that apply to the preferred modes of operation, together with the biasing characteristics as
functions of VLCD and the resulting discrimination ratios (D), are given in Table 5.
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD >3V
th.
Multiplex drive modes of 1:3 and 1:4 with 1⁄2bias are possible but the discrimination and
hence the contrast ratios are smaller.
Bias is calculated by , where the values for a are
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1
(1)
where the values for n are
n = 1 for static mode
n = 2 for 1:2 multiplex
n = 3 for 1:3 multiplex
n = 4 for 1:4 multiplex
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
Table 5. Discrimination ratios
LCD drive
mode Number of: LCD bias
configuration
Backplanes Levels
static 1 2 static 0 1 ∞
1:2 multiplex 2 3 1⁄20.354 0.791 2.236
1:2 multiplex 2 4 1⁄30.333 0.745 2.236
1:3 multiplex 3 4 1⁄30.333 0.638 1.915
1:4 multiplex 4 4 1⁄30.333 0.577 1.732
V
off
RMS
()
V
LCD
--------------------------
V
on
RMS
()
V
LCD
-------------------------
DV
on
RMS
()
V
off
RMS
()
--------------------------=
1
1a
+
-------------
Von RMS() a22a n++
n
1a
+()
2
×
------------------------------
V
LCD
=
Voff RMS() a22a–n+
n
1a
+()
2
×
------------------------------
V
LCD
=
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 10 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
(3)
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄2bias is and the discrimination for an LCD drive mode of 1:4 multiplex with
1⁄2bias is .
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
•1:3 multiplex (1⁄2 bias):
•1:4 multiplex (1⁄2 bias):
These compare with when 1⁄3 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
D
V
on RMS()
V
off RMS()
------------------------
a1
+()
2
n
1
–()+
a1
–()
2
n
1
–()+
--------------------------------------------==
3 1.732
=
21
3
----------
1.528
=
V
LCD
6V
off
RMS
()
×
2.449V
off
RMS
(
)
==
V
LCD
43
×()
3
----------------------
2.309V
off
RMS
()
==
V
LCD
3V
off
RMS
()
=
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 11 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. The
backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Figure 6.
(1) Vstate1(t) = VSn(t) − VBP0(t).
(2) Von(RMS) = VLCD.
(3) Vstate2(t) = VSn+1(t) − VBP0(t).
(4) Voff(RMS) = 0 V.
Fig 6. Static drive mode waveforms
mgl745
VSS
VLCD
VSS
VLCD
VSS
VLCD
VLCD
−VLCD
−VLCD
VLCD
state 1 0 V
BP0
Sn
Sn+1
state 2 0 V
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 1
(on) state 2
(off)
Tfr
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 12 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This
mode allows fractional LCD bias voltages of 1⁄2 bias or 1⁄3 bias as shown in Figure 7 and
Figure 8.
(1) Vstate1(t) = VSn(t) − VBP0(t).
(2) Von(RMS) = 0.791VLCD.
(3) Vstate2(t) = VSn+1(t) − VBP1(t).
(4) Voff(RMS) = 0.354VLCD.
Fig 7. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
mgl746
state 1
BP0
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 2
state 1
VSS
VLCD
VLCD / 2
VSS
VSS
VLCD
VLCD
VSS
VLCD
VLCD
VLCD
0 V
0 V
VLCD / 2
VLCD / 2
VLCD / 2
−VLCD
−VLCD
−VLCD / 2
−VLCD / 2
Sn
Sn+1
Tfr
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 13 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
(1) Vstate1(t) = VSn(t) − VBP0(t).
(2) Von(RMS) = 0.745VLCD.
(3) Vstate2(t) = VSn+1(t) − VBP1(t).
(4) Voff(RMS) = 0.333VLCD.
Fig 8. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
mgl747
state 1
BP0
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
0 V
VLCD
2VLCD / 3
−2VLCD / 3
VLCD / 3
−VLCD / 3
−VLCD
−VLCD
0 V
VLCD
2VLCD / 3
−2VLCD / 3
VLCD / 3
−VLCD / 3
Sn
Sn+1
Tfr
VSS
VLCD
2VLCD / 3
VLCD / 3
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 14 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies
(see Figure 9).
(1) Vstate1(t) = VSn(t) − VBP0(t).
(2) Von(RMS) = 0.638VLCD.
(3) Vstate2(t) = VSn+1(t) − VBP1(t).
(4) Voff(RMS) = 0.333VLCD.
Fig 9. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
mgl748
state 1
BP0
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
(a) Waveforms at driver.
BP2
Sn
Sn+1
Sn+2
Tfr
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
0 V
VLCD
2VLCD / 3
−2VLCD / 3
VLCD / 3
−VLCD / 3
−VLCD
0 V
VLCD
2VLCD / 3
−2VLCD / 3
VLCD / 3
−VLCD / 3
−VLCD
VSS
VLCD
2VLCD / 3
VLCD / 3
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 15 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see
Figure 10).
(1) Vstate1(t) = VSn(t) − VBP0(t).
(2) Von(RMS) = 0.577VLCD.
(3) Vstate2(t) = VSn+1(t) − VBP1(t).
(4) Voff(RMS) = 0.333VLCD.
Fig 10. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
mgl749
state 1
BP0
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
BP2
(a) Waveforms at driver.
BP3
Sn
Sn+1
Sn+2
Sn+3
Tfr
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
0 V
VLCD
2VLCD / 3
−2VLCD / 3
VLCD / 3
−VLCD / 3
−VLCD
0 V
VLCD
2VLCD / 3
−2VLCD / 3
VLCD / 3
−VLCD / 3
−VLCD
VSS
VLCD
2VLCD / 3
VLCD / 3
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 16 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.5 Oscillator
7.5.1 Internal clock
The internal logic of the PCF8576D and its LCD drive signals are timed either by its
internal oscillator or by an external clock. The internal oscillator is enabled by connecting
pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used
as the clock signal for several PCF8576Ds in the system that are connected in cascade.
After power-on, pin SDA must be HIGH to guarantee that the clock starts.
7.5.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD.
The LCD frame signal frequency is determined by the clock frequency (fclk).
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing
The PCF8576D timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the correct timing relationship between each PCF8576D in the system is
maintained by the synchronization signal at pin SYNC. The timing also generates the LCD
frame signal whose frequency is derived from the clock frequency. The frame signal
frequency is a fixed division of the clock frequency from either the internal or an external
clock: .
7.7 Display register
The display latch holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display latch, the
LCD segment outputs and each column of the display RAM.
7.8 Segment outputs
The LCD drive section includes 40 segment outputs S0 to S39 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display latch. When
less than 40 segment outputs are required, the unused segment outputs should be left
open-circuit.
7.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit.
In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
ffr
f
clk
24
--------
=
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 17 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals
and may also be paired to increase the drive capabilities.
In the static drive mode the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.10 Display RAM
The display RAM is a static 40 × 4-bit RAM which stores LCD data. A logic 1 in the RAM
bit-map indicates the on-state of the corresponding LCD element; similarly, a logic 0
indicates the off-state. There is a one-to-one correspondence between the RAM
addresses and the segment outputs, and between the individual bits of a RAM word and
the backplane outputs. The display RAM bit map Figure 11 shows the rows 0 to 3 which
correspond with the backplane outputs BP0 to BP3, and the columns 0 to 39 which
correspond with the segment outputs S0 to S39. In multiplexed LCD applications the
segment data of the first, second, third and fourth row of the display RAM are
time-multiplexed with BP0, BP1, BP2 and BP3 respectively.
When display data is transmitted to the PCF8576D, the display bytes received are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and does not wait for an acknowledge cycle as with the commands. Depending
on the current multiplex drive mode, data is stored singularly, in pairs, triplets or
quadruplets. To illustrate the filling order, an example of a 7-segment numeric display
showing all drive modes is given in Figure 12; the RAM filling organization depicted
applies equally to other LCD types.
Display RAM bit map showing direct relationship between RAM addresses and segment outputs;
also between bits in a RAM word and the backplane outputs.
Fig 11. Display RAM bit map
0
0
1
2
3
1234 3536373839
display RAM addresses (columns)/segment outputs (S)
display RAM bits
(rows)/
backplane outputs
(BP)
mbe525
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 18 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
x = data bit unchanged.
Fig 12. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus
001aaj646
acbDPfegd
MSB LSB
bDPcadgfe
MSB LSB
abfgecdDP
MSB LSB
cbafgedDP
MSB LSB
drive mode
static
1:2
multiplex
1:3
multiplex
1:4
multiplex
LCD segments LCD backplanes display RAM filling order transmitted display byte
BP0
BP0
BP1
BP0
BP1 BP2
BP1
BP2
BP3
BP0
n
c
x
x
x
0
1
2
3
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
display RAM
bits (rows)/
backplane
outputs (BP)
byte1
display RAM addresses (columns)/segment outputs (S)
n
a
b
x
x
0
1
2
3
f
g
x
x
e
c
x
x
d
DP
x
x
n + 1 n + 2 n + 3
byte1 byte2
display RAM
bits (rows)/
backplane
outputs (BP)
display RAM addresses (columns)/segment outputs (S)
n
b
DP
c
x
0
1
2
3
a
d
g
x
f
e
x
x
n + 1 n + 2
byte1 byte2 byte3
display RAM
bits (rows)/
backplane
outputs (BP)
display RAM addresses (columns)/segment outputs (S)
n + 1
n
a
c
b
DP
0
1
2
3
f
e
g
d
byte1 byte2 byte3 byte4 byte5
display RAM
bits (rows)/
backplane
outputs (BP)
display RAM addresses (columns)/segment outputs (S)
Sn+2
Sn+3
Sn+1
Sn
DP
a
fb
g
ec
d
Sn+2
Sn+1
Sn+7
Sn
Sn+3
Sn+5
Sn+6
Sn+4
DP
a
fb
g
ec
d
Sn
Sn+1
Sn+2
DP
a
fb
g
ec
d
Sn+1
Sn
DP
a
fb
g
ec
d
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 19 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
The following applies to Figure 12:
•In the static drive mode, the eight transmitted data bits are placed in row 0 of eight
successive 4-bit RAM words.
•In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into
row 0 and 1 of four successive 4-bit RAM words.
•In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1 and 2 to
three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted.
•In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into
row 0, 1, 2 and 3 of two successive 4-bit RAM words.
7.11 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer.
This allows the loading of an individual display data byte, or a series of display data bytes,
into any location of the display RAM. The sequence commences with the initialization of
the data pointer by the load-data-pointer command (see Section 7.17).
Following this command, an arriving data byte is stored at the display RAM address
indicated by the data pointer. The filling order is shown in Figure 12.
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
After each byte is stored, the contents of the data pointer is automatically incremented by
a value dependent on the selected LCD drive mode:
•In static drive mode by eight
•In 1:2 multiplex drive mode by four
•In 1:3 multiplex drive mode by three
•In 1:4 multiplex drive mode by two
If an I2C-bus data access is terminated early then the state of the data pointer is unknown.
The data pointer should be re-written prior to further RAM accesses.
7.12 Subaddress counter
The storage of display data is determined by the contents of the subaddress counter.
Storage is allowed to take place only when the contents of the subaddress counter match
with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is
defined by the device-select command (see Section 7.17). If the contents of the
subaddress counter and the hardware subaddress do not match then data storage is
inhibited but the data pointer is incremented as if data storage had taken place. The
subaddress counter is also incremented when the data pointer overflows.
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 20 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8576D occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character (such as during the 14th
display data byte transmitted in 1:3 multiplex mode).
The hardware subaddress must not be changed while the device is being accessed on the
I2C-bus interface.
7.13 Output bank selector
The output bank selector selects one of the four bits per display RAM address for transfer
to the display latch. The actual bit chosen depends on the selected LCD drive mode in
operation and on the instant in the multiplex sequence.
•In 1:4 mode, all RAM addresses of bit 0 are selected, these are followed by the
contents of bit 1, bit 2 and then bit 3.
•In 1:3 mode, bits 0, 1 and 2 are selected sequentially
•In 1:2 mode, bits 0 and 1 are selected
•In static mode, bit 0 is selected
The PCF8576D includes a RAM bank switching feature in the static and 1:2 drive modes.
In the static drive mode, the bank-select command (see Section 7.17) may request the
contents of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 mode, the
contents of bits 2 and 3 may be selected instead of bits 0 and 1. This gives the provision
for preparing display information in an alternative bank and to be able to switch to it once it
is assembled.
7.14 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration.
The bank-select command (see Section 7.17) can be used to load display data in bit 2 in
static drive mode or in bits 2 and 3 in 1:2 mode. The input bank selector functions are
independent of the output bank selector.
7.15 Blinker
The PCF8576D has a very versatile display blinking capability. The whole display can
blink at a frequency selected by the blink-select command (see Section 7.17). Each blink
frequency is a fraction of the clock frequency; the ratio between the clock frequency and
blink frequency depends on the blink mode selected (see Table 6).
An additional feature allows an arbitrary selection of LCD segments to blink in the static
and 1:2 drive modes. This is implemented without any communication overheads by the
output bank selector which alternates the displayed data between the data in the display
RAM bank and the data in an alternative RAM bank at the blink frequency. This mode can
also be implemented by the blink-select command (see Section 7.17).
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 21 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
In the 1:3 and 1:4 drive modes, where no alternative RAM bank is available, groups of
LCD segments can blink selectively by changing the display RAM data at fixed time
intervals.
The entire display can blink at a frequency other than the nominal blink frequency by
sequentially resetting and setting the display enable bit E at the required rate using the
mode-set command (see Section 7.17).
[1] Blink modes 1, 2 and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz correspond to an oscillator
frequency (fclk) of 1536 Hz (see Section 11).
7.16 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
7.16.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 13).
Table 6. Blinking frequencies[1]
Blink mode Normal operating mode ratio Nominal blink frequency
off - blinking off
1 2 Hz
2 1 Hz
3 0.5 Hz
f
clk
768
----------
f
clk
1536
-------------
f
clk
3072
-------------
Fig 13. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 22 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.16.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 14).
7.16.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves (see Figure 15).
7.16.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
•A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
•Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
•The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
Fig 14. Definition of START and STOP conditions
mbc622
SDA
SCL P
STOP condition
SDA
SCL
S
START condition
Fig 15. System configuration
mga807
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 23 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
•A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 16.
7.16.5 I2C-bus controller
The PCF8576D acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8576D are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0, A1 and A2 are normally
tied to VSS which defines the hardware subaddress 0. In multiple device
applications A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding
scheme such that no two devices with a common I2C-bus slave address have the same
hardware subaddress.
7.16.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.16.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8576D.
The least significant bit of the slave address that a PCF8576D will respond to is defined by
the level tied to its SA0 input. The PCF8576D is a write-only device and will not respond to
a read access. Having two reserved slave addresses allows the following on the same
I2C-bus:
•Up to 16 PCF8576Ds for very large LCD applications
•The use of two types of LCD multiplex drive.
Fig 16. Acknowledgement of the I2C-bus
mbc602
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 24 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of two possible PCF8576D
slave addresses available. All PCF8576Ds whose SA0 inputs correspond to bit 0 of the
slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is
ignored by all PCF8576Ds whose SA0 inputs are set to the alternative level.
After an acknowledgement, one or more command bytes follow, that define the status of
each addressed PCF8576D.
The last command byte sent is identified by resetting its most significant bit, continuation
bit C, (see Figure 18). The command bytes are also acknowledged by all addressed
PCF8576D on the bus.
After the last command byte, one or more display data bytes may follow. Display data
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data directed to the intended PCF8576D device.
An acknowledgement after each byte is asserted only by the PCF8576Ds that are
addressed via address lines A0, A1 and A2. After the last display byte, the I2C-bus master
asserts a STOP condition (P). Alternately a START may be asserted to restart an I2C-bus
access.
Fig 17. I2C-bus protocol
Fig 18. Format of command byte
mdb078
S
A
0
S011100 0AC COMMAND A P
ADISPLAY DATA
slave address R/W
acknowledge by
all addressed
PCF8576Ds
acknowledge
by A0, A1 and A2
selected
PCF8576D only
1 byte
update data pointers
and if necessary,
subaddress counter
n ≥ 1 byte(s) n ≥ 0 byte(s)
msa833
REST OF OPCODE
C
MSB LSB
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Product data sheet Rev. 09 — 25 August 2009 25 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.17 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus.
The commands available to the PCF8576D are defined in Table 7.
[1] Not used.
All available commands carry a continuation bit C in their most significant bit position as
shown in Figure 18. When this bit is set, it indicates that the next byte of the transfer to
arrive will also represent a command. If this bit is reset, it indicates that the command byte
is the last in the transfer. Further bytes will be regarded as display data (see Table 8).
[1] The possibility to disable the display allows implementation of blinking under external control.
Table 7. Definition of PCF8576D commands
Command Operation Code Reference
Bit 7 6 5 4 3 2 1 0
mode-set C 1 0 [1] E B M1 M0 Table 9
load-data-pointer C 0 P5 P4 P3 P2 P1 P0 Table 10
device-select C 1100A2A1A0
Table 11
bank-select C 11110I O
Table 12
blink-select C 1110ABF1BF0
Table 13
Table 8. C bit description
Bit Symbol Value Description
7C continue bit
0 last control byte in the transfer; next byte will be regarded
as display data
1 control bytes continue; next byte will be a command too
Table 9. Mode-set command bits description
Bit Symbol Value Description
7 C 0, 1 see Table 8
6, 5 - 10 fixed value
4 - - unused
3E display status
0 disabled (blank)[1]
1 enabled
2B LCD bias configuration
01⁄3 bias
11⁄2 bias
1 to 0 M[1:0] LCD drive mode selection
01 static; BP0
10 1:2 multiplex; BP0, BP1
11 1:3 multiplex; BP0, BP1, BP2
00 1:4 multiplex; BP0, BP1, BP2, BP3
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 26 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[2] Alternating RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
Table 10. Load-data-pointer command bits description
Bit Symbol Value Description
7 C 0, 1 see Table 8
6 - 0 fixed value
5 to 0 P[5:0] 000000 to
100111 6 bit binary value, 0 to 39; transferred to the data pointer to
define one of forty display RAM addresses
Table 11. Device-select command bits description
Bit Symbol Value Description
7 C 0, 1 see Table 8
6 to 3 - 1100 fixed value
2 to 0 A[2:0] 000 to 111 3 bit binary value, 0 to 7; transferred to the subaddress
counter to define one of eight hardware subaddresses
Table 12. Bank-select command bits description
Bit Symbol Value Description
Static 1:2 multiplex[1]
7 C 0, 1 see Table 8
6 to 2 - 11110 fixed value
1I input bank selection; storage of arriving display data
0 RAM bit 0 RAM bits 0 and 1
1 RAM bit 2 RAM bits 2 and 3
0O output bank selection; retrieval of LCD display data
0 RAM bit 0 RAM bits 0 and 1
1 RAM bit 2 RAM bits 2 and 3
Table 13. Blink-select command bits description
Bit Symbol Value Description
7 C 0, 1 see Table 8
6 to 3 - 1110 fixed value
2A blink mode selection
0 normal blinking[1]
1 alternate RAM bank blinking[2]
1 to 0 BF[1:0] blink frequency selection
00 off
01 1
10 2
11 3
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Product data sheet Rev. 09 — 25 August 2009 27 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.18 Display controller
The display controller executes the commands identified by the command decoder. It
contains the device’s status registers and coordinates their effects. The display controller
is also responsible for loading display data into the display RAM in the correct filling order.
8. Internal circuitry
Fig 19. Device protection circuits
SA0
VDD VDD
VSS VSS
VLCD
VSS
SDA
mdb076
VSS
SCL
VSS
CLK
VDD
VSS
OSC
VDD
VSS
SYNC
VDD
VSS
A0, A1 A2
VDD
VSS
BP0, BP1,
BP2, BP3
VLCD
VSS
S0 to S39
VLCD
VSS
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Product data sheet Rev. 09 — 25 August 2009 28 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
9. Limiting values
[1] Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114”.
[2] Pass level; Machine Model (MM), according to Ref. 8 “JESD22-A115”.
[3] Pass level; Charged-Device Model (CDM), according to Ref. 9 “JESD22-C101”.
[4] Pass level; latch-up testing, according to Ref. 10 “JESD78”.
[5] According to the NXP store and transport conditions (see Ref. 12 “SNW-SQ-623”) the devices have to be
stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 14. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage −0.5 6.5 V
VLCD LCD supply voltage −0.5 +7.5 V
VIinput voltage on each of the pins CLK,
SDA, SCL, SYNC, SA0,
OSC, A0 to A2
−0.5 +6.5 V
VOoutput voltage on each of the pins S0 to
S39, BP0 to BP3 −0.5 +7.5 V
IIinput current −10 +10 mA
IOoutput current −10 +10 mA
IDD supply current −50 +50 mA
IDD(LCD) LCD supply current −50 +50 mA
ISS ground supply current −50 +50 mA
Ptot total power dissipation - 400 mW
Pooutput power - 100 mW
VESD electrostatic discharge
voltage HBM [1] -±5000 V
MM [2] -±200 V
CDM [3] -±1000 V
Ilu latch-up current [4] - 100 mA
Tstg storage temperature [5] −65 +150 °C
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Product data sheet Rev. 09 — 25 August 2009 29 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
10. Static characteristics
[1] VLCD > 3 V for 1⁄3 bias.
[2] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[3] When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 14 (see Figure 19
too).
[4] Propagation delay of driver between clock (CLK) and LCD driving signals.
[5] Periodically sampled, not 100 % tested.
[6] Outputs measured one at a time.
Table 15. Static characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 6.5 V; T
amb
=
−
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDD supply voltage 1.8 - 5.5 V
VLCD LCD supply voltage [1] 2.5 - 6.5 V
IDD supply current fclk = 1536 Hz [2] -820µA
IDD(LCD) LCD supply current fclk = 1536 Hz [2] -2460µA
Logic
VP(POR) power-on reset supply voltage 1.0 1.3 1.6 V
VIL LOW-level input voltage on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
VSS - 0.3VDD V
VIH HIGH-level input voltage on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
[3][4] 0.7VDD -V
DD V
IOL LOW-level output current VOL = 0.4 V; VDD =5V
on pins CLK and SYNC 1 - - mA
on pin SDA 3 - - mA
IOH(CLK) HIGH-level output current on pin CLK VOH = 4.6 V; VDD =5V −1- - mA
ILleakage current VI=V
DD or VSS;
on pins CLK, SCL, SDA,
A0 to A2 and SA0
−1- +1µA
IL(OSC) leakage current on pin OSC VI=V
DD −1- +1µA
CIinput capacitance [5] --7pF
LCD outputs
∆VOoutput voltage variation on pins BP0 to BP3 and
S0 to S39 −100 - +100 mV
ROoutput resistance VLCD = 5 V [6]
on pins BP0 to BP3 - 1.5 - kΩ
on pins S0 to S39 - 6.0 - kΩ
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Product data sheet Rev. 09 — 25 August 2009 30 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
11. Dynamic characteristics
[1] Typical output duty factor: 50 % measured at the CLK output pin.
[2] Not tested in production.
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
Table 16. Dynamic characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 6.5 V; T
amb
=
−
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Clock
fclk(int) internal clock frequency [1] 1440 1850 2640 Hz
fclk(ext) external clock frequency 960 - 2640 Hz
tclk(H) HIGH-level clock time 60 - - µs
tclk(L) LOW-level clock time 60 - - µs
Synchronization
tPD(SYNC_N) SYNC propagation delay - 30 - ns
tSYNC_NL SYNC LOW time 1 - - µs
tPD(drv) driver propagation delay VLCD = 5 V [2] --30µs
I2C-bus[3]
Pin SCL
fSCL SCL clock frequency - - 400 kHz
tLOW LOW period of the SCL clock 1.3 - - µs
tHIGH HIGH period of the SCL clock 0.6 - - µs
Pin SDA
tSU;DAT data set-up time 100 - - ns
tHD;DAT data hold time 0 - - ns
Pins SCL and SDA
tBUF bus free time between a STOP and
START condition 1.3 - - µs
tSU;STO set-up time for STOP condition 0.6 - - µs
tHD;STA hold time (repeated) START condition 0.6 - - µs
tSU;STA set-up time for a repeated START
condition 0.6 - - µs
trrise time of both SDA and SCL signals fSCL = 400 kHz - - 0.3 µs
fSCL < 125 kHz - - 1.0 µs
tffall time of both SDA and SCL signals - - 0.3 µs
Cbcapacitive load for each bus line - - 400 pF
tw(spike) spike pulse width on the I2C-bus - - 50 ns
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 31 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
Fig 20. Driver timing waveforms
Fig 21. I2C-bus timing waveforms
001aai163
tPD(drv)
tSYNC_NL
tPD(SYNC_N)
CLK
SYNC
BP0 to BP3,
and S0 to S39
tclk(H) tclk(L)
1 / fCLK
0.7 VDD
0.3 VDD
0.7 VDD
0.3 VDD
0.5 V
(VDD = 5 V)
0.5 V
SDA
mga728
SDA
SCL
tSU;STA tSU;STO
tHD;STA
tBUF tLOW
tHD;DAT tHIGH
tr
tf
tSU;DAT
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 32 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
12. Application information
12.1 Cascaded operation
In large display configurations, up to 16 PCF8576Ds can be differentiated on the same
I2C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the
programmable I2C-bus slave address (SA0).
PCF8576Ds connected in cascade are synchronized to allow the backplane signals from
only one device in the cascade to be shared. This arrangement is cost-effective in large
LCD applications since the backplane outputs of only one device need to be
through-plated to the backplane electrodes of the display. The other cascaded
PCF8576Ds contribute additional segment outputs but their backplane outputs are left
open-circuit (see Figure 22).
All PCF8576Ds connected in cascade are correctly synchronized by the SYNC signal.
This synchronization is guaranteed after the power-on reset. The only time that SYNC is
likely to be needed is if synchronization is lost accidentally, for example, by noise in
adverse electrical environments, or if the LCD multiplex drive mode is changed in an
application using several cascaded PCF8576Ds, as the drive mode cannot be changed on
all of the cascaded devices simultaneously. SYNC can be either an input or an output
signal; a SYNC output is implemented as an open-drain driver with an internal pull-up
resistor. The PCF8576D asserts SYNC at the start of its last active backplane signal and
monitors the SYNC line at all other times. If cascade synchronization is lost, it is restored
by the first PCF8576D to assert SYNC. The timing relationship between the backplane
waveforms and the SYNC signal for each LCD drive mode is shown in Figure 23.
Table 17. Addressing cascaded PCF8576D
Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device
100000
0011
0102
0113
1004
1015
1106
1117
210008
0019
01010
01111
10012
10113
11014
11115
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 33 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
The contact resistance between the SYNC on each cascaded device must be controlled.
If the resistance is too high, the device is not able to synchronize properly; this is
particularly applicable to chip-on-glass applications. The maximum SYNC contact
resistance allowed for the number of devices in cascade is given in Table 18.
The PCF8576D can be cascaded with the PCF8562, the PCF8533 or the PCF8534A.
This allows optimal drive selection for a given number of pixels to display. Figure 20 and
Figure 21 show the timing of the synchronization signals.
Table 18. SYNC contact resistance
Number of devices Maximum contact resistance
26 kΩ
3 to 5 2.2 kΩ
6 to 10 1.2 kΩ
10 to 16 700 Ω
Fig 22. Cascaded PCF8576D configuration
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDA
SCL
CLK
OSC
SYNC
1, 58, 59
2, 3
4
5
7
89
6
8 9 10 11 12
13
10 11 12
40 segment drives
4 backplanes
40 segment drives LCD PANEL
(up to 2560
elements)
PCF8576DU
A0 A1 A2 SA0
VDD
VLCD
DD
VLCD
V
mdb077
SDA
SCL
SYNC
CLK
OSC
1, 58, 59
613
2, 3
4
5
7BP0 to BP3
(open-circuit)
A0 A1 A2 SA0 VSS
VSS
VSS
VDD VLCD
PCF8576DU
BP0 to BP3
Rtr
2CB
≤
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 34 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
Fig 23. Synchronization of the cascade for the various PCF8576D drive modes
Tfr =ffr
1
BP0
SYNC
BP0
(1/2 bias)
SYNC
BP0
(1/3 bias)
(a) static drive mode.
(b) 1:2 multiplex drive mode.
(c) 1:3 multiplex drive mode.
(d) 1:4 multiplex drive mode.
BP0
(1/3 bias)
SYNC
SYNC
BP0
(1/3 bias)
mgl755
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 35 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
13. Package outline
Fig 24. Package outline SOT357-1 (TQFP64)
UNIT A
max. A1A2A3bpcE
(1) eH
ELL
pZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.2 0.15
0.05 1.05
0.95 0.25 0.27
0.17 0.18
0.12 10.1
9.9 0.5 12.15
11.85 1.45
1.05 7
0
o
o
0.08 0.11 0.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT357-1 137E10 MS-026 00-01-19
02-03-14
D(1) (1)(1)
10.1
9.9
HD
12.15
11.85
E
Z
1.45
1.05
D
bp
e
θ
EA1
A
Lp
detail X
L
(A )
3
B
16
c
D
H
bp
E
HA2
vMB
D
ZD
A
ZE
e
vMA
X
1
64
49
48 33
32
17
y
pin 1 index
wM
wM
0 2.5 5 mm
scale
TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm SOT357-1
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 36 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
Fig 25. Package outline SOT364-1 (TSSOP56)
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT364-1 99-12-27
03-02-19
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
128
56 29
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 14.1
13.9 6.2
6.0 0.5 1
8.3
7.9 0.50
0.35 0.5
0.1
0.080.25
0.8
0.4
p
EvMA
A
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 37 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
14. Bare die outline
Fig 26. Bare die outline PCF8576DU/DA/2
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
PCF8576DU/DA
pcf8576du_da_do
08-10-20
08-12-10
Unit
mm max
nom
min 0.38 2.26 0.072 0.09 0.08 0.066
A
Dimensions
Notes
1. Pad size
2. Passivation opening
3. Dimension not drawn to scale
4. Marking code: PC8576D-2
Wire bond die; 59 bonding pads; 2.26 x 2.01 x 0.38 mm PCF8576DU/DA
DE
2.01
e(3) P1(1) P2(2) P3(1) P4(2)
0.056
0 0.5 1 mm
scale
A
e
X
(4)
00y
x
D
E
C2 59 152 8 C1
2235
36
51 9
21
detail X
P2
P1
P4P3
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 38 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
Fig 27. Bare die outline PCF8576DU/2DA/2
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
PCF8576DU/2DA
pcf8576du_2da_do
08-10-23
08-12-10
Bare die; 59 bumps; 2.26 x 2.01 x 0.40 mm PCF8576DU/2DA
e
X
(2)
00y
x
D
E
C2 59 152 8 C1
2235
36
51 9
21
detail X
b
L
Unit
mm max
nom
min 0.40 2.26 0.072 0.0770.052
A
0.381
A2
0.015
A1
Dimensions
Notes
1. Dimension not drawn to scale
2. Marking code: PC8576D-2
DE
2.01
e(1) Lb
0 0.5 1 mm
scale
Y
detail Y
A1
A2
A
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 39 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
Table 19. Bonding pad location for PCF8576DU/x
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 4,Figure 26 and Figure 27).
Symbol Pad X (µm) Y (µm) Description
SDA 1 −34.38 −876.6 I2C-bus serial data input/output
SCL 2 109.53 −876.6 I2C-bus serial clock input
SCL 3 181.53 −876.6
SYNC 4 365.58 −876.6 cascade synchronization input/output
CLK 5 469.08 −876.6 external clock input/output
VDD 6 577.08 −876.6 supply voltage
OSC 7 740.88 −876.6 internal oscillator enable input
A0 8 835.83 −876.6 subaddress inputs
A1 9 1005.48 −630.9
A2 10 1005.48 −513.9
SA0 11 1005.48 −396.9 I2C-bus address input; bit 0
VSS 12 1005.48 −221.4 ground supply voltage
VLCD 13 1005.48 10.71 LCD supply voltage
BP0 14 1005.48 156.51 LCD backplane outputs
BP2 15 1005.48 232.74
BP1 16 1005.48 308.97
BP3 17 1005.48 385.2
S0 18 1005.48 493.2 LCD segment outputs
S1 19 1005.48 565.2
S2 20 1005.48 637.2
S3 21 1005.48 709.2
S4 22 347.22 876.6
S5 23 263.97 876.6
S6 24 180.72 876.6
S7 25 97.47 876.6
S8 26 14.22 876.6
S9 27 −69.03 876.6
S10 28 −152.28 876.6
S11 29 −235.53 876.6
S12 30 −318.78 876.6
S13 31 −402.03 876.6
S14 32 −485.28 876.6
S15 33 −568.53 876.6
S16 34 −651.78 876.6
S17 35 −735.03 876.6
S18 36 −1005.5 625.59
S19 37 −1005.5 541.62
S20 38 −1005.5 458.19
S21 39 −1005.5 374.76
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 40 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in
JESD625-A
,
IEC 61340-5
or equivalent
standards.
S22 40 −1005.5 291.33 LCD segment outputs
S23 41 −1005.5 207.9
S24 42 −1005.5 124.47
S25 43 −1005.5 41.04
S26 44 −1005.5 −42.39
S27 45 −1005.5 −125.8
S28 46 −1005.5 −209.3
S29 47 −1005.5 −292.7
S30 48 −1005.5 −376.1
S31 49 −1005.5 −459.5
S32 50 −1005.5 −543
S33 51 −1005.5 −625.6
S34 52 −735.03 −876.6
S35 53 −663.03 −876.6
S36 54 −591.03 −876.6
S37 55 −519.03 −876.6
S38 56 −447.03 −876.6
S39 57 −375.03 −876.6
SDA 58 −196.38 −876.6 I2C-bus serial data input/output
SDA 59 −106.38 −876.6
Table 20. Alignment marks
All x/y coordinates represent the position of the center of each alignment mark with respect to the
center (x/y = 0) of the chip (see Figure 4,Figure 26 and Figure 27).
Symbol X (µm) Y (µm)
C1 930.42 −870.3
C2 −829.98 −870.3
Table 19. Bonding pad location for PCF8576DU/x
…continued
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 4,Figure 26 and Figure 27).
Symbol Pad X (µm) Y (µm) Description
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 41 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
16. Packing information
16.1 Tray information
Fig 28. Tray details
Table 21. Tray dimensions (see Figure 28)
Symbol Description Value Unit
A pocket pitch in x direction 5.59 mm
B pocket pitch in y direction 6.35 mm
C pocket width in x direction 3.16 mm
D pocket width in y direction 3.16 mm
E tray width in x direction 50.8 mm
F tray width in y direction 50.8 mm
G cut corner to pocket 1.1 center 5.83 mm
H cut corner to pocket 1.1 center 6.35 mm
x number of pockets, x direction 8 -
y number of pockets, y direction 7 -
x
y
F
H
mce404
D
E
A
G
1,1 x,12,1
1,2
1,y x,y
C
B
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 42 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
16.2 Carrier tape information
Fig 29. Tray alignment
mdb080
PC8576D
Fig 30. Tape details
Table 22. Carrier tape dimensions
Symbol Description Value Unit
A0 pocket width in x direction 8.6 mm
B0 pocket width in y direction 14.5 mm
K0 pocket height 1.8 mm
P1 sprocket hole pitch 12 mm
W tape width in y direction 24 mm
001aaj314
direction of feed
K04A0
P1
B0
W
pin 1 index
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 43 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note
AN10365 “Surface mount reflow
soldering description”
.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
•Through-hole components
•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•Board specifications, including the board finish, solder masks and vias
•Package footprints, including solder thieves and orientation
•The moisture sensitivity level of the packages
•Package placement
•Inspection and repair
•Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
•Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
•Solder bath specifications, including temperature and impurities
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 44 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
17.4 Reflow soldering
Key characteristics in reflow soldering are:
•Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 31) than a SnPb process, thus
reducing the process window
•Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
•Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 23 and 24
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 31.
Table 23. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 ≥ 350
< 2.5 235 220
≥ 2.5 220 220
Table 24. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 45 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
For further information on temperature profiles, refer to Application Note
AN10365
“Surface mount reflow soldering description”
.
18. Soldering of WLCSP packages
18.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note
AN10439 “Wafer Level Chip Scale Package”
and in application note
AN10365 “Surface
mount reflow soldering description”
.
Wave soldering is not suitable for this package.
All NXP WLCSP packages are lead-free.
18.2 Board mounting
Board mounting of a WLCSP requires several steps:
1. Solder paste printing on the PCB
2. Component placement with a pick and place machine
3. The reflow soldering itself
18.3 Reflow soldering
Key characteristics in reflow soldering are:
•Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 32) than a PbSn process, thus
reducing the process window
MSL: Moisture Sensitivity Level
Fig 31. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 46 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
•Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
•Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature), and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic) while being low enough that the packages and/or boards are not
damaged. The peak temperature of the package depends on package thickness and
volume and is classified in accordance with Table 25.
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 32.
For further information on temperature profiles, refer to application note
AN10365
“Surface mount reflow soldering description”
.
18.3.1 Stand off
The stand off between the substrate and the chip is determined by:
•The amount of printed solder on the substrate
•The size of the solder land on the substrate
Table 25. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
MSL: Moisture Sensitivity Level
Fig 32. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 47 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
•The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
18.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been
wetted by the solder from the bump. The surface of the joint should be smooth and the
shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps
after reflow can occur during the reflow process in bumps with high ratio of bump diameter
to bump height, i.e. low bumps with large diameter. No failures have been found to be
related to these voids. Solder joint inspection after reflow can be done with X-ray to
monitor defects such as bridging, open circuits and voids.
18.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the
chip from the substrate and replacing it with a new chip. If a chip is removed from the
substrate, most solder balls of the chip will be damaged. In that case it is recommended
not to re-use the chip again.
Device removal can be done when the substrate is heated until it is certain that all solder
joints are molten. The chip can then be carefully removed from the substrate without
damaging the tracks and solder lands on the substrate. Removing the device must be
done using plastic tweezers, because metal tweezers can damage the silicon. The
surface of the substrate should be carefully cleaned and all solder and flux residues
and/or underfill removed. When a new chip is placed on the substrate, use the flux
process instead of solder on the solder lands. Apply flux on the bumps at the chip side as
well as on the solder pads on the substrate. Place and align the new chip while viewing
with a microscope. To reflow the solder, use the solder profile shown in application note
AN10365 “Surface mount reflow soldering description”
.
18.3.4 Cleaning
Cleaning can be done after reflow soldering.
19. Abbreviations
Table 26. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
CDM Charged-Device Model
HBM Human Body Model
ITO Indium Tin Oxide
LCD Liquid Crystal Display
LSB Least Significant Bit
MM Machine Model
MSB Most Significant Bit
MSL Moisture Sensitivity Level
PCB Printed Circuit Board
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 48 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
RAM Random Access Memory
RMS Root Mean Square
SCL Serial Clock Line
SDA Serial Data Line
SMD Surface Mount Device
WLCSP Wafer Level Chip-Size Package
Table 26. Abbreviations
…continued
Acronym Description
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 49 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
20. References
[1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD
drivers
[2] AN10365 — Surface mount reflow soldering description
[3] AN10706 — Handling bare die
[4] IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[6] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[7] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[8] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[9] JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[10] JESD78 — IC Latch-Up Test
[11] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[12] SNW-SQ-623 — NXP store and transport conditions
[13] UM10204 — I2C-bus specification and user manual
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 50 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
21. Revision history
Table 27. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCF8576D_9 20090825 Product data sheet - PCF8576D_8
Modifications: •Added new type of PCF8576DT/S400/2
•Corrected LCD voltage equations
PCF8576D_8 20090319 Product data sheet - PCF8576D_7
Modifications: •The typical value of the frame frequency has been corrected (see Table 16)
PCF8576D_7 20081218 Product data sheet - PCF8576D_6
Modifications: •Added tape and reel delivery form
PCF8576D_6 20081202 Product data sheet - PCF8576D_5
PCF8576D_5 20041222 Product specification - PCF8576D_4
PCF8576D_4 20041008 Product specification - PCF8576D_3
PCF8576D_3 20040617 Product specification - PCF8576D_2
PCF8576D_2 20030623 Product specification - PCF8576D_1
PCF8576D_1 20030401 Objective specification - -
PCF8576D_9 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 09 — 25 August 2009 51 of 52
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
22. Legal information
22.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
22.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
23. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 August 2009
Document identifier: PCF8576D_9
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
24. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
7 Functional description . . . . . . . . . . . . . . . . . . . 7
7.1 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.2 LCD bias generator. . . . . . . . . . . . . . . . . . . . . . 8
7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 9
7.4 LCD drive mode waveforms . . . . . . . . . . . . . . 11
7.4.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 11
7.4.2 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 12
7.4.3 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 14
7.4.4 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 15
7.5 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.5.1 Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.5.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.6 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.7 Display register. . . . . . . . . . . . . . . . . . . . . . . . 16
7.8 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 16
7.9 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 16
7.10 Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.11 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.12 Subaddress counter . . . . . . . . . . . . . . . . . . . . 19
7.13 Output bank selector. . . . . . . . . . . . . . . . . . . . 20
7.14 Input bank selector . . . . . . . . . . . . . . . . . . . . . 20
7.15 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.16 Characteristics of the I2C-bus. . . . . . . . . . . . . 21
7.16.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.16.2 START and STOP conditions . . . . . . . . . . . . . 22
7.16.3 System configuration . . . . . . . . . . . . . . . . . . . 22
7.16.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.16.5 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 23
7.16.6 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.16.7 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 23
7.17 Command decoder. . . . . . . . . . . . . . . . . . . . . 25
7.18 Display controller . . . . . . . . . . . . . . . . . . . . . . 27
8 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 27
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28
10 Static characteristics. . . . . . . . . . . . . . . . . . . . 29
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 30
12 Application information. . . . . . . . . . . . . . . . . . 32
12.1 Cascaded operation . . . . . . . . . . . . . . . . . . . . 32
13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 35
14 Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 37
15 Handling information . . . . . . . . . . . . . . . . . . . 40
16 Packing information . . . . . . . . . . . . . . . . . . . . 41
16.1 Tray information . . . . . . . . . . . . . . . . . . . . . . . 41
16.2 Carrier tape information . . . . . . . . . . . . . . . . . 42
17 Soldering of SMD packages. . . . . . . . . . . . . . 43
17.1 Introduction to soldering. . . . . . . . . . . . . . . . . 43
17.2 Wave and reflow soldering. . . . . . . . . . . . . . . 43
17.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 43
17.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 44
18 Soldering of WLCSP packages . . . . . . . . . . . 45
18.1 Introduction to soldering WLCSP packages. . 45
18.2 Board mounting . . . . . . . . . . . . . . . . . . . . . . . 45
18.3 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 45
18.3.1 Stand off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
18.3.2 Quality of solder joint . . . . . . . . . . . . . . . . . . . 47
18.3.3 Rework. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
18.3.4 Cleaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 47
20 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
21 Revision history . . . . . . . . . . . . . . . . . . . . . . . 50
22 Legal information . . . . . . . . . . . . . . . . . . . . . . 51
22.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 51
22.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
22.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 51
22.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51
23 Contact information . . . . . . . . . . . . . . . . . . . . 51
24 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
