Ground.

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not

running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 107 on page 250.

Shorter pulses are not guaranteed to generate a reset.

The reset pin can also be used as a (weak) I/O pin.

This is an 8-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have high sink

ATtiny828 provides the following features:

download at http://www.atmel.com/avr.

This documentation contains simple code examples that briefly show how to use various parts of the device. These code

examples assume that the part specific header file is included before compilation. Be aware that not all C compiler

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years

at 85°C or 100 years at 25°C.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register

operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect

information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the

accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O

functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File,

0x20 - 0x5F. In addition, the ATtiny828 has Extended I/O Space from 0x60 - 0xFF in SRAM where only the ST/STS/STD

and LD/LDS/LDD instructions can be used.

instructions, resulting in faster and more compact code. See external document “AVR Instruction Set” and “Instruction

Set Summary” on page 301 section for more information.

The Status Register is neither automatically stored when entering an interrupt routine, nor restored when returning from

an interrupt. This must be handled by software.

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance

and flexibility, the following input/output schemes are supported by the Register File:

are non-volatile, i.e. they retain stored information even when not powered.

and the application program section. For more information, see “Self-Programming the Flash” on page 218, and

“Application and Boot Loader Flash Sections” on page 214.

Program Memory), and SPM (Store Program Memory) in “Instruction Set Summary” on page 301. Flash program

memory can also be programmed from an external device, as described in “External Programming” on page 232.

internal data memory.

addresses should never be written.

Purpose Register File” on page 9.

and the general purpose register file using instructions such as IN, OUT, LD, ST, and derivatives.

See “Instruction Set Summary” on page 301.

See “Register Summary” on page 297 for a list of I/O registers.

Following the general purpose register file and the I/O register files, the remaining 512 locations are reserved for the

internal data SRAM.

There are five addressing modes available:

which single bytes can be read and written. All access registers are located in the I/O space.

The EEPROM has a minimum endurance of 100,000 write/erase cycles.

There are two methods for EEPROM programming:

At low supply voltages data in EEPROM can be corrupted in two ways:

The EEPROM address register is required by the read and write operations to indicate the memory location that is being

EEPROM data bytes are addressed linearly over the entire memory range (0...[256-1]). The initial value of these bits is

undefined and a legitimate value must therefore be written to the register before EEPROM is accessed.

Devices with 256 bytes of EEPROM, or less, do not require a high address registers (EEARH). In such devices the high

address register is therefore left out but, for compatibility issues, the remaining register is still referred to as the low byte

These bits are reserved and will always read zero.

EEPROM programming mode bits define the action that will be triggered when EEPE is written. Data can be

programmed in a single atomic operation, where the previous value is automatically erased before the new value is

programmed, or Erase and Write can be split in two different operations. The programming times for the different modes

When EEMPE is set and EEPE written within four clock cycles the EEPROM at the selected address will be

This is the read strobe of the EEPROM. When the target address has been set up in the EEAR, the EERE bit must be

written to one to trigger the EEPROM read operation.

EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is

read the EEPROM, or to change the address register (EEAR).

Note: 1. This is the initial value when CKDIV8 fuse has been unprogrammed.

the factory calibrated frequency specified in Table 104 on page 249.

frequencies specified in Table 104 on page 249. Calibration outside that range is not guaranteed.

the factory calibrated frequency as specified in Table 105 on page 250.

frequencies as specified in Table 105 on page 250. Calibration outside that range is not guaranteed.

during changes to clock frequency.

application’s requirements.

Figure 11 on page 27 presents the different clock systems and their distribution in ATtiny828. The figure is helpful in

selecting an appropriate sleep mode. Table 9 shows the different sleep modes and the sources that may be used for

following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a

reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.

Note that if a level triggered interrupt is used for wake-up the changed level must be held for some time to wake up the

This sleep mode halts clkI/O, clkCPU, and clkFLASH, while allowing other clocks to run. In ADC Noise Reduction mode, the

CPU is stopped but the following peripherals continue to operate:

This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a

The following events can wake up the MCU:

The following events can wake up the MCU:

The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 37, provides a method to reduce

power consumption by stopping the clock to individual peripherals. When the clock for a peripheral is stopped then:

There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In

general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as

mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically

enabled by the BODPD Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper

application, this module can also be set to Sampled BOD mode to save power. See “Brown-out Detection” on page 41 for

details on how to configure the Brown-out Detector.

in Table 107 on page 250 for details on the start-up time.

When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then

when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled.

This bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To

avoid the MCU entering sleep mode unintentionally, it is recommended to write the Sleep Enable (SE) bit to one just

before the execution of the SLEEP instruction and to clear it immediately after waking up.

The Power Reduction Register provides a method to reduce power consumption by allowing peripheral clock signals to

Writing a logic one to this bit shuts down the Two-Wire Interface module.

These bits are reserved and will always read zero.

During reset, all I/O registers are set to their initial values, and the program starts execution from the Reset Vector. The

instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the

the BOD is enabled, a BOD reset will be given when VCC falls and remains below the trigger level for the length of the