Low Noise, 1 GHz FastFET Op Amps ADA4817-1/ADA4817-2 Data Sheet CONNECTION DIAGRAMS ADA4817-1 TOP VIEW (Not to Scale) PD 1 8 +VS FB 2 7 OUT -IN 3 6 NIC +IN 4 5 -VS NOTES 1. NIC = NO INTERNAL CONNECTION. 07756-001 High speed -3 dB bandwidth (G = 1, RL = 100 ): 1050 MHz Slew rate: 870 V/s 0.1% settling time: 9 ns Input bias current: 2 pA typical Input capacitance Common-mode capacitance: 1.3 pF typical Differential mode capacitance: 0.1 pF typical Low input noise Voltage noise: 4 nV/Hz at 100 kHz Current noise: 2.5 fA/Hz at 100 kHz Low distortion: -90 dBc at 10 MHz (G = 1, RL = 1 k) orms a pole in the lo: 40 mA Supply quiescent current per amplifier: 19 mA typical Powered down supply quiescent current per amplifier: 1.5 mA typical Figure 1. 8-Lead LFCSP (CP-8-13) ADA4817-1 TOP VIEW (Not to Scale) FB 1 8 PD -IN 2 7 +VS +IN 3 6 OUT -VS 4 5 NIC NOTES 1. NIC = NO INTERNAL CONNECTION. APPLICATIONS 07756-002 FEATURES Figure 2. 8-Lead SOIC (RD-8-1) Photodiode amplifiers Data acquisition front ends Instrumentation Filters ADC drivers Output buffers ADA4817-2 13 OUT1 -IN1 1 12 -VS1 +IN1 2 11 NIC NIC 3 10 +IN2 9 -IN2 FB2 8 PD2 7 +VS2 6 OUT2 5 -VS2 4 NOTES 1. NIC = NO INTERNAL CONNECTION. 07756-003 14 +VS1 16 FB1 15 PD1 TOP VIEW (Not to Scale) Figure 3. 16-Lead LFCSP (CP-16-20) Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. 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Technical Support www.analog.com ADA4817-1/ADA4817-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driving Capacitive Loads .......................................................... 20 Applications ....................................................................................... 1 Thermal Considerations............................................................ 20 Connection Diagrams ...................................................................... 1 Power-Down Operation ............................................................ 21 Revision History ............................................................................... 3 Capacitive Feedback................................................................... 21 General Description ......................................................................... 4 Higher Frequency Attenuation ................................................. 22 Specifications..................................................................................... 5 Layout, Grounding, and Bypassing Considerations .................. 23 5 V Operation ............................................................................. 5 Signal Routing............................................................................. 23 5 V Operation ............................................................................... 6 Power Supply Bypassing ............................................................ 23 Absolute Maximum Ratings ............................................................ 8 Grounding ................................................................................... 23 Thermal Resistance ...................................................................... 8 Exposed Pad ................................................................................ 23 Maximum Safe Power Dissipation ............................................. 8 Leakage Currents ........................................................................ 24 ESD Caution .................................................................................. 8 Input Capacitance ...................................................................... 24 Pin Configurations and Function Descriptions ........................... 9 Input-to-Input/Output Coupling ............................................. 24 Typical Performance Characteristics ........................................... 11 Applications Information .............................................................. 25 Test Circuits ..................................................................................... 18 Low Distortion Pinout ............................................................... 25 Theory of Operation ...................................................................... 19 Wideband Photodiode Preamp ................................................ 25 Closed-Loop Frequency Response ........................................... 19 High Speed JFET Input Instrumentation Amplifier.............. 27 Noninverting Closed-Loop Frequency Response .................. 19 Active Low-Pass Filter (LPF) .................................................... 28 Inverting Closed-Loop Frequency Response ............................. 19 Outline Dimensions ....................................................................... 30 Wideband Operation ................................................................. 20 Ordering Guide .......................................................................... 31 Rev. F | Page 2 of 31 Data Sheet ADA4817-1/ADA4817-2 REVISION HISTORY 6/2018--Rev. E to Rev. F Changes to Input Common-Mode Voltage Range, Table 1 ......... 5 Changes to Input Common-Mode Voltage Range, Table 2 ......... 7 1/2018--Rev. D to Rev. E Changes to Figure 57 ......................................................................21 10/2017--Rev. C to Rev. D Changes to Features Section and Applications Section ...................... 1 Changes to Table 1 ............................................................................ 5 Changes to Table 2 ............................................................................ 6 Changes to Thermal Resistance Section, Table 4, and Maximum Safe Power Dissipation Section ....................................................... 8 Changes to Figure 5........................................................................... 9 Changes to Figure 7.........................................................................10 Reorganized Typical Performance Characteristics Layout ........11 Added Figure 32 through Figure 37; Renumbered Sequentially .... 15 Added Figure 38 through Figure 43..............................................16 Added Figure 44 and Figure 45 .....................................................17 Changes to Noninverting Closed-Loop Frequency Response Section, Inverting Closed-Loop Frequency Response Section, and Figure 54 Caption ....................................................................19 Changes to Thermal Considerations Section ..............................20 Added Figure 57 and Figure 58 .....................................................21 Changes to Power-Down Operation Section and Table 8 .........21 Changed Exposed Paddle Section to Exposed Pad Section ......23 Changes to Wideband Photodiode Preamp Section ..................25 Change to Table 9 ............................................................................26 Changes to Active Low Pass Filter (LPF) Section .......................28 Updated Outline Dimensions ........................................................30 Changes to Ordering Guide ...........................................................31 5/2013--Rev. A to Rev. B Changes to Figure 3 .......................................................................... 1 Changes to Figure 7 .......................................................................... 7 Updated Outline Dimensions........................................................ 24 Changes to Ordering Guide ........................................................... 25 3/2009--Rev. 0 to Rev. A Added 8-Lead SOIC Package............................................ Universal Changes to Features Section and General Description Section.. 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Figure 4 .......................................................................... 5 Changes to Figure 9, Figure 11, and Figure 12 .............................. 8 Changes to Figure 21, Figure 22, and Figure 24 .......................... 10 Changes to Figure 33 ...................................................................... 12 Added Figure 34; Renumbered Sequentially ............................... 12 Changes to Thermal Considerations Section and Power-Down Operation Section ........................................................................... 15 Changes to Capacitive Feedback Section and Figure 46 ............ 16 Added Higher Frequency Attenuation Section, Figure 47, Figure 48, and Figure 49; Renumbered Sequentially.................. 16 Updated Outline Dimensions........................................................ 24 Changes to Ordering Guide ........................................................... 25 11/2008--Revision 0: Initial Version 5/2016--Rev. B to Rev. C Changed CP-8-2 to CP-8-13 ........................................ Throughout Changes to Figure 1, Figure 2, and Figure 3 .................................. 1 Changes to Figure 5, Table 5, Figure 6, and Table 6...................... 6 Changes to Figure 7 and Table 7 ..................................................... 7 Updated Outline Dimensions ........................................................24 Changes to Ordering Guide ...........................................................25 Rev. F | Page 3 of 31 ADA4817-1/ADA4817-2 Data Sheet GENERAL DESCRIPTION The ADA4817-1 (single) and ADA4817-2 (dual) FastFETTM amplifiers are unity-gain stable, ultrahigh speed, voltage feedback amplifiers with FET inputs. These amplifiers were developed with the Analog Devices, Inc., proprietary eXtra fast complementary bipolar (XFCB) process, which allows the amplifiers to achieve ultralow noise (4 nV/Hz; 2.5 fA/Hz) as well as very high input impedances. With 1.3 pF of input capacitance, low noise (4 nV/Hz), low offset voltage (2 mV maximum), and 1050 MHz -3 dB bandwidth, the ADA4817-1/ADA4817-2 are ideal for data acquisition front ends as well as wideband transimpedance applications, such as photodiode preamps. With a wide supply voltage range from 5 V to 10 V and the ability to operate on either single or dual supplies, the ADA4817-1/ ADA4817-2 are designed to work in a variety of applications including active filtering and analog-to-digital converter (ADC) driving. The ADA4817-1 is available in a 3 mm x 3 mm, 8-lead LFCSP and 8-lead SOIC, and the ADA4817-2 is available in a 4 mm x 4 mm, 16-lead LFCSP. These packages feature a low distortion pinout that improves second harmonic distortion and simplifies circuit board layout. They also feature an exposed pad that provides a low thermal resistance path to the printed circuit board (PCB). The EPAD enables more efficient heat transfer and increases reliability. These products are rated to work over the extended industrial temperature range (-40C to +105C). Rev. F | Page 4 of 31 Data Sheet ADA4817-1/ADA4817-2 SPECIFICATIONS 5 V OPERATION TA = 25C, +VS = 5 V, -VS = -5 V, G = 1, RF = 348 for G > 1, RL = 100 to ground, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Gain Bandwidth Product Full Power Bandwidth 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Harmonic Distortion f = 1 MHz HD2 HD3 f = 10 MHz HD2 HD3 f = 50 MHz HD2 HD3 Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Test Conditions/Comments Min VOUT = 0.1 V p-p VOUT = 2 V p-p VOUT = 0.1 V p-p, G = 2 VOUT = 0.1 V p-p VIN = 3.3 V p-p, G = 2 VOUT = 2 V p-p, RL = 100 , G = 2 VOUT = 4 V step VOUT = 2 V step, G = 2 Typ 1050 200 390 410 60 60 870 9 MHz MHz MHz MHz MHz MHz V/s ns -113 -117 dBc dBc -90 -94 dBc dBc -64 -66 4 2.5 dBc dBc nV/Hz fA/Hz VOUT = 2 V p-p, RL = 1 k VOUT = 2 V p-p, RL = 1 k f = 100 kHz f = 100 kHz 0.4 TMIN to TMAX, SOIC TMIN to TMAX, LFCSP TMIN to TMAX, SOIC TMIN to TMAX, LFCSP 25 10 2 75 1 TMIN to TMAX Input Bias Offset Current TMIN to TMAX Input Common-Mode Voltage Range Common-Mode Rejection OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Output Voltage Swing High Unit VOUT = 2 V p-p, RL = 1 k Input Bias Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Max 62 Common mode Common mode Differential mode VCM = 0.5 V VCM = 0.5 V, TMIN to TMAX VCM = -4.2 V to 2.2 V, TMIN to TMAX -77 -73 -65 VIN = 2.5 V, G = 2 RL = 100 RL = 100 , TMIN to TMAX RL = 1 k Rev. F | Page 5 of 31 +VS - 1.5 +VS - 1.65 +VS - 1.1 65 2 6 4 80 50 20 135 10 110 mV mV mV V/C V/C pA pA pA pA dB 500 1.3 0.1 -VS to (+VS - 2.8) -90 G pF pF V dB dB dB 8 ns +VS - 1.3 V V V +VS - 1 ADA4817-1/ADA4817-2 Parameter Low Linear Output Current Short-Circuit Current POWER-DOWN PD Pin Voltage Turn On Time Turn Off Time Input Leakage Current POWER SUPPLY Operating Range Quiescent Current per Amplifier Powered Down Quiescent Current Positive Power Supply Rejection Negative Power Supply Rejection Data Sheet Test Conditions/Comments RL = 1 k, TMIN to TMAX RL = 100 RL = 100 , TMIN to TMAX RL = 1 k RL = 1 k, TMIN to TMAX 1% output error Sinking Sourcing Min +VS - 1.4 Enabled, TMIN to TMAX Powered down, TMIN to TMAX >+VS - 0.9 Typ Max 40 100 170 Unit V V V V V mA mA mA -VS + 1.4 -VS + 1.5 -VS + 1.65 -VS + 1.1 -VS + 1.2 0.3 1 0.3 34 V V s s A A -VS + 1 <+VS - 3.5 PD = +VS PD = -VS 3 61 5 +VS = 4.5 V to 5.5 V, -VS = -5 V +VS = 5 V, -VS = -4.5 V to -5.5 V 10 21 3 19 1.5 -72 -72 -67 -67 V mA mA dB dB 5 V OPERATION TA = 25C, +VS = 3 V, -VS = -2 V, G = 1, RF = 348 for G > 1, RL = 100 to ground, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Full Power Bandwidth 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Harmonic Distortion f = 1 MHz HD2 HD3 f = 10 MHz HD2 HD3 f = 50 MHz HD2 HD3 Input Voltage Noise Input Current Noise Test Conditions/Comments VOUT = 0.1 V p-p VOUT = 1 V p-p VOUT = 0.1 V p-p, G = 2 VIN = 1 V p-p, G = 2 VOUT = 1 V p-p, G = 2 VOUT = 2 V step VOUT = 1 V step, G = 2 Min Typ 500 160 280 95 32 320 11 VOUT = 1 V p-p, RL = 1 k -87 -88 Max Unit MHz MHz MHz MHz MHz V/s Ns dBc dBc VOUT = 1 V p-p, RL = 1 k -68 -66 dBc dBc -57 -55 4 2.5 dBc dBc nV/Hz fA/Hz VOUT = 1 V p-p, RL = 1 k f = 100 kHz f = 100 kHz Rev. F | Page 6 of 31 Data Sheet Parameter DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift ADA4817-1/ADA4817-2 Test Conditions/Comments Min TMIN to TMAX, SOIC TMIN to TMAX, LFCSP TMIN to TMAX, SOIC TMIN to TMAX, LFCSP Typ Max Unit 0.5 2.3 6.5 5 75 45 20 70 10 65 mV mV mV V/C V/C pA pA pA pA dB 25 10 2 50 1 Input Bias Current TMIN to TMAX Input Bias Offset Current TMIN to TMAX Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Output Voltage Swing High Low Linear Output Current Short-Circuit Current POWER-DOWN PD Pin Voltage Turn On Time Turn Off Time Input Leakage Current POWER SUPPLY Operating Range Quiescent Current per Amplifier Powered Down Quiescent Current Positive Power Supply Rejection Negative Power Supply Rejection 61 Common mode Common mode Differential mode VCM = 0.25 V VCM = 0.3 V, TMIN to TMAX VCM = 0.8 V, TMIN to TMAX -72 -70 -59 VIN = 1.25 V, G = 2 RL = 100 RL = 100 , TMIN to TMAX RL = 1 k RL = 1 k, TMIN to TMAX RL = 100 RL = 100 , TMIN to TMAX RL = 1 k RL = 1 k, TMIN to TMAX 1% output error Sinking sourcing +VS - 1.3 +VS - 1.4 +VS - 1.1 +VS - 1.2 Enabled, TMIN to TMAX Powered down, TMIN to TMAX >+VS - 0.9 63 500 1.3 0.1 -VS to (+VS - 2.9) -83 G pF pF V dB dB dB 13 ns +VS - 1.2 V V V V V V V V mA mA mA +VS - 1 -VS + 1 -VS + 0.9 20 40 130 <+VS - 3.5 0.2 0.7 0.2 31 PD = +VS PD = -VS 5 +VS = 4.75 V to 5.25 V, -VS = 0 V +VS = 5 V, -VS = -0.25 V to +0.25 V Rev. F | Page 7 of 31 -VS + 1.1 -VS + 1.2 -VS + 1 -VS + 1.1 -66 -63 14 1.5 -71 -69 3 53 10 16 2.8 V V s s A A V mA mA dB dB ADA4817-1/ADA4817-2 Data Sheet ABSOLUTE MAXIMUM RATINGS V V V 2 PD VS I S S OUT - OUT RL RL 2 Table 3. Rating 10.6 V See Figure 4 -VS - 0.5 V to +VS + 0.5 V VS -65C to +125C -40C to +105C 300C 150C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Consider root mean square (rms) output voltages. If RL is referenced to -VS, as in single-supply operation, the total drive power is VS x IOUT. If the rms signal levels are indeterminate, consider the worst-case scenario, when VOUT = VS/4 for RL to midsupply. PD VS I S VS /4 2 (3) RL In single-supply operation with RL referenced to -VS, the worstcase situation is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing JA. More metal directly in contact with the package leads and exposed pad from metal traces, through holes, ground, and power planes also reduces JA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the exposed paddle 8-lead LFCSP (single 94C/W), 8-lead SOIC (single 79C/W), and 16-lead LFCSP (dual 64C/W) packages on JEDEC standard 4-layer boards. JA values are approximations. THERMAL RESISTANCE Thermal performance is directly linked to PCB design and operating environment. Careful attention to PCB thermal design is required. 3.5 Table 4. JA 94 79 64 JC 29 29 14 Unit C/W C/W C/W MAXIMUM POWER DISSIPATION (W) Package Type CP-8-13 RD-8-1 CP-16-20 (2) MAXIMUM SAFE POWER DISSIPATION The maximum safe power dissipation for the ADA4817-1/ ADA4817-2 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C (which is the glass transition temperature), the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4817-1/ ADA4817-2. Exceeding a junction temperature of 150C for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality. ADA4817-2, LFCSP 2.5 ADA4817-1, SOIC 2.0 1.5 ADA4817-1, LFCSP 1.0 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 AMBIENT TEMPERATURE (C) Figure 4. Maximum Safe Power Dissipation vs. Ambient Temperature for a 4-Layer Board ESD CAUTION The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the ADA4817-1/ADA4817-2 drive at the output. The quiescent power is the voltage between the supply pins (VS) multiplied by the quiescent current (IS). PD = Quiescent Power + (Total Drive Power - Load Power) 3.0 07756-008 Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Range Differential Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature (1) Rev. F | Page 8 of 31 Data Sheet ADA4817-1/ADA4817-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADA4817-1 PD 1 8 +VS FB 2 7 OUT -IN 3 6 NIC +IN 4 5 -VS NOTES 1. NIC = NO INTERNAL CONNECTION. 2. EXPOSED PAD. CAN BE CONNECTED TO GND, -VS PLANE, OR LEFT FLOATING. 07756-005 TOP VIEW (Not to Scale) Figure 5. ADA4817-1 Pin Configuration (8-Lead LFCSP) Table 5. ADA4817-1 Pin Function Descriptions (8-Lead LFCSP) Pin No. 1 2 3 4 5 6 7 8 Mnemonic PD FB -IN +IN -VS NIC OUT +VS EPAD Description Power-Down. Do not leave floating. Feedback Pin. Inverting Input. Noninverting Input. Negative Supply. No Internal Connection. Output. Positive Supply. Exposed Pad. Can be connected to GND, -VS plane, or left floating. ADA4817-1 FB 1 8 PD -IN 2 7 +VS +IN 3 6 OUT -VS 4 5 NIC NOTES 1. NIC = NO INTERNAL CONNECTION. 2. EXPOSED PAD. CAN BE CONNECTED TO GND, -VS PLANE, OR LEFT FLOATING. 07756-006 TOP VIEW (Not to Scale) Figure 6. ADA4817-1 Pin Configuration (8-Lead SOIC) Table 6. ADA4817-1 Pin Function Descriptions (8-Lead SOIC) Pin No. 1 2 3 4 5 6 7 8 Mnemonic FB -IN +IN -VS NIC OUT +VS PD EPAD Description Feedback Pin. Inverting Input. Noninverting Input. Negative Supply. No Internal Connection. Output. Positive Supply. Power-Down. Do not leave floating. Exposed Pad. Can be connected to GND, -VS plane, or left floating. Rev. F | Page 9 of 31 ADA4817-1/ADA4817-2 Data Sheet ADA4817-2 13 OUT1 -IN1 1 12 -VS1 +IN1 2 11 NIC NIC 3 10 +IN2 9 -IN2 FB2 8 PD2 7 +VS2 6 OUT2 5 -VS2 4 NOTES 1. NIC = NO INTERNAL CONNECTION. 2. EXPOSED PAD. CAN BE CONNECTED TO GND, -VS PLANE, OR LEFT FLOATING. 07756-107 14 +VS1 16 FB1 15 PD1 TOP VIEW (Not to Scale) Figure 7. ADA4817-2 Pin Configuration (16-Lead LFCSP) Table 7. ADA4817-2 Pin Function Descriptions (16-Lead LFCSP) Pin No. 1 2 3, 11 4 5 6 7 8 9 10 12 13 14 15 16 Mnemonic -IN1 +IN1 NIC -VS2 OUT2 +VS2 PD2 FB2 -IN2 +IN2 -VS1 OUT1 +VS1 PD1 FB1 EPAD Description Inverting Input 1. Noninverting Input 1. No Internal Connection. Negative Supply 2. Output 2. Positive Supply 2. Power-Down 2. Do not leave floating. Feedback Pin 2. Inverting Input 2. Noninverting Input 2. Negative Supply 1. Output 1. Positive Supply 1. Power-Down 1. Do not leave floating. Feedback Pin 1. Exposed Pad. Can be connected to GND, -VS plane, or left floating. Rev. F | Page 10 of 31 Data Sheet ADA4817-1/ADA4817-2 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VS = 5 V, G = 1, (RF = 348 for G > 1), RL = 100 to ground, small signal VOUT = 100 mV p-p, large signal VOUT = 2 V p-p, unless otherwise noted. 6 G =2 0 G=5 -3 -6 -9 -12 100k 1M 10M 100M FREQUENCY (Hz) 1G 10G G=2 G = 1, SINGLE G = 1, DUAL 0 G=5 -3 -6 -9 -12 100k Figure 8. Small Signal Frequency Response for Various Gains (LFCSP) 6 3 1M 10M 100M FREQUENCY (Hz) 1G 10G 07756-009 3 G = 1, SINGLE NORMALIZED CLOSED-LOOP GAIN (dB) G = 1, DUAL 07756-066 NORMALIZED CLOSED-LOOP GAIN (dB) 6 Figure 11. Large Signal Frequency Response for Various Gains 6 VS = 10V, SOIC VS = 10V, LFCSP 3 VS = 5V, LFCSP CLOSED-LOOP GAIN (dB) VS = 5V, SOIC 0 -3 -6 VS = 5V -6 -9 1M 10M 100M FREQUENCY (Hz) 1G 10G VOUT = 1V p-p -12 1M 100k 07756-007 -12 100k Figure 9. Small Signal Frequency Response for Various Supplies 9 CL = 6.6pF CL = 4.4pF 10M 100M FREQUENCY (Hz) 1G 10G Figure 12. Large Signal Frequency Response for Various Supplies 9 CL = 2.2pF RF = 348 6 RF = 274 6 CLOSED-LOOP GAIN (dB) CL = 0pF 3 0 -3 -6 RF = 200 3 0 -3 -6 G=2 RF = 274 -9 100k 1M 10M 100M FREQUENCY (Hz) 1G 10G 07756-068 CLOSED-LOOP GAIN (dB) -3 07756-010 -9 VS = 10V 0 Figure 10. Small Signal Frequency Response for Various CL G=2 -9 100k 1M 10M 100M FREQUENCY (Hz) 1G Figure 13. Small Signal Frequency Response for Various RF Rev. F | Page 11 of 31 10G 07756-011 CLOSED-LOOP GAIN (dB) 3 ADA4817-1/ADA4817-2 Data Sheet 0.5 6 G = 2, SS 3 G = 2, LS 0.2 0.1 G = 1, SS 0 G = 1, LS -0.1 -0.2 -3 -6 -0.3 -9 -0.4 1M 10M 100M FREQUENCY (Hz) 10G 1G -12 100k 07756-012 10M 100M 1G 10G Figure 17. Small Signal Frequency Response vs. Temperature -20 -20 -40 DISTORTION (dBc) -40 -60 HD2, RL = 100 HD2, RL = 1k -100 HD3, RL = 100 -120 HD2, VS = 5V -80 HD3, VS = 5V -100 HD2, VS = 10V -140 100k 10M 100M FREQUENCY (Hz) HD3, VS = 10V 1M 07756-014 1M -60 -120 HD3, RL = 1k -140 100k 1M FREQUENCY (Hz) Figure 14. 0.1 dB Flatness Frequency Response vs. Gain and Output Voltage -80 TA = +25C, SINGLE TA = +25C, DUAL TA = -40C, SINGLE TA = -40C, DUAL TA = +105C, SINGLE TA = +105C, DUAL 100M 10M FREQUENCY (Hz) Figure 15. Distortion vs. Frequency for Various Loads, VOUT = 2 V p-p 07756-013 -0.5 100k DISTORTION (dBc) 0 07756-036 0.3 CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) 0.4 Figure 18. Distortion vs. Frequency for Various Supplies, VOUT = 2 V p-p -20 -20 fC = 1MHz -40 HD2, VS = 5V -60 DISTORTION (dBc) DISTORTION (dBc) -40 HD2, VS = 10V -80 -100 HD3, VS = 5V -60 -80 HD2, RL = 100 HD2, RL = 1k -100 HD3, VS = 10V -120 10M FREQUENCY (Hz) 100M -140 HD3, RL = 100 HD3, RL = 1k 0 1 2 3 4 5 OUTPUT VOLTAGE (V p-p) Figure 16. Distortion vs. Frequency for Various Supplies, G = 2, VOUT = 2 V p-p Rev. F | Page 12 of 31 Figure 19. Distortion vs. Output Voltage for Various Loads 6 07756-017 1M 07756-016 -120 -140 100k Data Sheet ADA4817-1/ADA4817-2 1.5 0.075 1.0 0.025 0 -0.025 0.5 0 -0.5 DUAL, LFCSP RF = 0 RL = 100 VS = 5V G = +1 SINGLE, CSP -1.0 07756-022 -0.050 SINGLE, SOIC -0.075 SINGLE,SOIC DUAL, LFCSP RF = 0 RL = 100 VS = 5V G = +1 07756-024 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0.050 SINGLE, CSP -1.5 TIME (5ns/DIV) TIME (5ns/DIV) Figure 20. Small Signal Transient Response vs. Package Figure 23. Large Signal Transient Response vs. Package 6 0.5 2 x VIN SETTLING TIME 0.4 4 2 SETTLING TIME (%) 0 -2 VOUT 0.2 0.1 0 -0.1 -0.2 -0.3 -4 -6 -0.4 07756-019 G=2 TIME (10ns/DIV) 07756-023 OUTPUT VOLTAGE (V) 0.3 -0.5 TIME (5ns/DIV) Figure 21. Output Overdrive Recovery 0 DUAL, CF = 0.5pF SINGLE, NO CF -10 -20 SINGLE -30 PSRR (dB) 0.05 0 -0.05 -PSRR +PSRR -50 -60 -80 -0.10 -0.15 -40 -70 DUAL 07756-021 OUTPUT VOLTAGE (V) 0.10 VS = 5V G=2 TIME (5ns/DIV) -90 -100 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 22. Small Signal Transient Response Figure 25. Power Supply Rejection Ratio (PSRR) vs. Frequency Rev. F | Page 13 of 31 07756-032 0.15 Figure 24. 0.1% Short-Term Settling Time ADA4817-1/ADA4817-2 Data Sheet -20 24 -25 22 QUIESCENT CURRENT (mA) -30 -40 -45 -50 -55 16 VS = +5V 14 10M 1G FREQUENCY (Hz) 10 -40 Figure 26. Common-Mode Rejection Ratio (CMRR) vs. Frequency -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 29. Quiescent Current vs. Temperature for Various Supply Voltages 100 OUTPUT SATURATION VOLTAGE (V) 1.6 10 1 0.1 VS = 5V RL = 100 1.5 -V-S + VOUT 1.4 1.3 +VS - VOUT +VS - VOUT 1.2 1.1 1.0 VS = +5V 0.9 07756-034 100k 07756-029 -65 10k 07756-033 12 -60 -VS + VOUT 1M 10M 100M FREQUENCY (Hz) 0.8 -40 07756-030 0.01 100k 1G 0 20 40 60 80 100 TEMPERATURE (C) Figure 30. Output Saturation Voltage vs. Temperature Figure 27. Output Impedance vs. Frequency 1000 0 70 60 OPEN-LOOP GAIN (dB) GAIN 100 10 -45 50 40 PHASE -90 30 20 10 -135 0 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 100M 07756-026 INPUT VOLTAGE NOISE (nV/ Hz) -20 -10 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 28. Input Voltage Noise vs. Frequency Figure 31. Open-Loop Gain and Phase vs. Frequency Rev. F | Page 14 of 31 -180 1G 07756-015 OUTPUT IMPEDANCE () 18 PHASE (Degrees) CMRR (dB) -35 VS = 5V 20 Data Sheet ADA4817-1/ADA4817-2 40 40 VS = 5V VS = 5V 35 PERCENT OF AMPLIFIERS 30 25 20 15 10 20 15 10 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 25 5 07756-400 5 30 07756-401 PERCENT OF AMPLIFIERS 35 OFFSET VOLTAGE (mV) OFFSET VOLTAGE (mV) Figure 35. Input Offset Voltage Histogram (VS = 5 V), SOIC Only Figure 32. Input Offset Voltage Histogram (VS = 5 V), LFCSP Only 14 14 VS = 5V VS = 5V 12 12 TA = -40C TA = +105C 6 8 6 4 4 2 2 0 -4 -3 -2 -1 0 2 1 3 0 -4 4 07756-338 NUMBER OF HITS 8 07756-335 NUMBER OF HITS 10 TA = -40C TA = +105C 10 -3 -2 -1 2 1 3 4 Figure 33. Input Offset Voltage Histogram over Temperature (VS = 5 V), LFCSP Only Figure 36. Input Offset Voltage Histogram over Temperature (VS = 5 V), LFCSP Only 24 24 VS = 5V TA = -40C TA = +105C TA = +105C 18 NUMBER OF HITS 18 15 12 9 15 12 9 6 3 3 07756-334 6 0 -6 VS = 5V TA = -40C 21 -4 -2 0 2 4 0 -6 6 VOS (mV) 07756-337 21 NUMBER OF HITS 0 VOS (mV) VOS (mV) -4 -2 0 2 4 6 VOS (mV) Figure 34. Input Offset Voltage Histogram over Temperature (VS = 5 V), SOIC Only Figure 37. Input Offset Voltage Histogram over Temperature (VS = 5 V), SOIC Only Rev. F | Page 15 of 31 ADA4817-1/ADA4817-2 Data Sheet 5 5 VS = 5V 4 4 3 3 OFFSET VOLTAGE (mV) 2 1 SOIC 0 LFCSP -1 -2 -3 2 1 SOIC 0 -1 LFCSP -2 -4 -5 -60 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 07756-343 07756-340 -3 -4 -5 -60 120 -40 100 120 VS = 5V VS = 5V 9 9 LFCSP LFCSP SOIC SOIC 8 NUMBER OF AMPLIFIERS 8 7 6 5 4 3 7 6 5 4 3 07756-336 70 60 50 40 30 20 0 10 -10 -20 -30 -40 0 70 60 50 40 20 30 0 10 -10 -20 -40 -30 -50 INPUT OFFSET VOLTAGE DRIFT (V/C) INPUT OFFSET VOLTAGE DRIFT (V/C) Figure 39. Input Offset Voltage Drift Histogram (VS = 5V) Figure 42. Input Offset Voltage Drift Histogram (VS = 5 V) 30 30 VS = 5V VS = 5V 25 NUMBER OF AMPLIFIERS TA = 25C TA = 105C 20 15 10 20 15 10 5 07556-341 5 0 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 INPUT BIAS CURRENT (pA) TA = 25C TA = 105C 0 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 INPUT BIAS CURRENT (pA) Figure 43. Input Bias Current Histogram over Temperature (VS = 5 V) Figure 40. Input Bias Current Histogram over Temperature (VS = 5 V) Rev. F | Page 16 of 31 07556-344 -70 -60 0 1 -70 1 07756-339 2 2 -60 NUMBER OF AMPLIFIERS 80 10 10 NUMBER OF AMPLIFIERS 0 20 40 60 TEMPERATURE (C) Figure 41. Offset Voltage vs. Temperature (VS = 5 V) Figure 38. Offset Voltage vs. Temperature (VS = 5 V) 25 -20 -50 OFFSET VOLTAGE (mV) VS = 5V Data Sheet ADA4817-1/ADA4817-2 1000 300 200 100 0 -100 -200 07756-342 -300 -400 2.5 2.0 1.5 1.0 0 0.5 -0.5 -1.5 -1.0 -2.5 -2.0 -3.0 -4.0 -3.5 -500 VS = 5V 800 600 400 200 0 -200 -400 -600 07756-345 400 COMMON-MODE REJECTION RATIO (V/V) VS = 5V -4.5 COMMON-MODE REJECTION RATIO (V/V) 500 -600 -1000 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) Figure 45. Common-Mode Rejection vs. Common-Mode Voltage, VS = 5 V Figure 44. Common-Mode Rejection vs. Common-Mode Voltage, VS = 5 V Rev. F | Page 17 of 31 ADA4817-1/ADA4817-2 Data Sheet TEST CIRCUITS The output feedback pins are used for ease of layout as shown in Figure 46 to Figure 51. +VS +VS 10F + 10F + RF RG 0.1F 0.1F 0.1F VIN VIN RL 49.9 0.1F VOUT VOUT RL 49.9 10F + -VS -VS Figure 49. Noninverting Gain Configuration Figure 46. G = 1 Configuration +VS +VS 10F + 49.9 AC 0.1F 07756-147 0.1F 07756-141 + 10F 0.1F VOUT VOUT RL 49.9 AC 07756-145 0.1F -VS 07756-148 + 10F RL -VS Figure 47. Positive Power Supply Rejection Figure 50. Negative Power Supply Rejection +VS +VS 10F + 10F + 1k RF 0.1F RSNUB VIN 49.9 VIN VOUT CL 0.1F 1k 0.1F RL 0.1F 1k 53.6 VOUT RL 1k 10F 0.1F -VS 07756-142 + + 10F 0.1F -VS Figure 51. Common-Mode Rejection Figure 48. Capacitive Load Configuration Rev. F | Page 18 of 31 07756-146 RG Data Sheet ADA4817-1/ADA4817-2 THEORY OF OPERATION The ADA4817-1/ADA4817-2 are voltage feedback operational amplifiers that combine new architecture for FET input operational amplifiers with the eXFCB process from Analog Devices, resulting in an outstanding combination of speed and low noise. The innovative high speed FET input stage handles commonmode signals from the negative supply to within 2.7 V of the positive rail. This stage is combined with an H-bridge to attain an 870 V/s slew rate and low distortion, in addition to 4 nV/Hz input voltage noise. The amplifier features a high speed output stage capable of driving heavy loads sourcing and sinking up to 40 mA of linear current. Supply current and offset current are laser trimmed for optimum performance. These specifications make the ADA4817-1/ADA4817-2 a great choice for high speed instrumentation and high resolution data acquisition systems. Their low noise, picoampere input current, precision offset, and high speed make them superb preamps for fast photo-diode applications. At dc, CLOSED-LOOP FREQUENCY RESPONSE Solve for closed-loop -3 dB frequency by VO RF RG VI RG The closed-loop -3 dB frequency is f 3dB fCROSSOVER VOUT A 07756-044 VE VIN Figure 52. Noninverting Configuration (6) Solving for the transfer function, 2 fCROSSOVER RF VO VI RF RG S 2 fCROSSOVER RG (7) At dc VO R F VI RG (8) f 3dB f CROSSOVER RG RF RG (9) A = (2 x fCROSSOVER )/s 80 OPEN-LOOP GAIN (A) (dB) RG RG RF RG INVERTING CLOSED-LOOP FREQUENCY RESPONSE The ADA4817-1/ADA4817-2 are classic voltage feedback amplifiers with an open-loop frequency response that can be approximated as the integrator response shown in Figure 54. Basic closed-loop frequency response for inverting and noninverting configurations can be derived from the schematics shown in Figure 52 and Figure 53. RF (5) 60 40 fCROSSOVER = 410MHz 20 RG 0 VE A VOUT 07756-045 VIN 100 1000 The closed-loop bandwidth is inversely proportional to the noise gain of the op amp circuit, (RF + RG)/RG. This simple model is accurate for noise gains above 2. The actual bandwidth of circuits with noise gains at or below 2 is higher than those predicted with this model due to the influence of other poles in the frequency response of the real op amp. NONINVERTING CLOSED-LOOP FREQUENCY RESPONSE Solving for the transfer function, where: fCROSSOVER is the frequency where the open-loop gain of the amplifier equals 0 dB. VO is the output voltage. VI is the input voltage. 10 FREQUENCY (MHz) Figure 54. Open-Loop Gain vs. Frequency Figure 53. Inverting Configuration 2 fCROSSOVER RG RF VO VI RF RG S 2 fCROSSOVER RG 1 0.1 07756-046 RF (4) Figure 55 shows the dc errors of the voltage feedback amplifier. For both inverting and noninverting configurations, VOUT (error) = R RF I b RS G RG RG RF Ib RF VOS RG where Ib is the bias current. Rev. F | Page 19 of 31 (10) ADA4817-1/ADA4817-2 Data Sheet RF In general, high speed amplifiers have a difficult time driving capacitive loads. This is particularly true in low closed-loop gains, where the phase margin is the lowest. +VOS - Ib - A VOUT Ib+ The difficulty arises because the load capacitance, CL, forms a pole with the output resistance, RO, of the amplifier. The pole can be described by the following equation: Figure 55. DC Errors of the Voltage Feedback Amplifier The voltage error due to Ib+ and Ib- is minimized if RS = RF || RG (though with the ADA4817-1/ADA4817-2 input currents in the picoamp range, this is likely not a concern). To include commonmode effects and power supply rejection effects, total VOS can be modeled by VS VCM PSR CMR (11) where: VOS is the offset voltage. VOSnom is the offset voltage specified at nominal conditions. VS is the change in power supply from nominal conditions. PSR is the power supply rejection. VCM is the change in common-mode voltage from nominal conditions. CMR is the common-mode rejection. WIDEBAND OPERATION The best performance is usually obtained in the G + 1 configuration with no feedback resistance, big output load resistors, and small board parasitic capacitances. If this pole occurs too close to the unity-gain crossover point, the phase margin degrades. Degradation is due to the additional phase loss associated with the pole. Note that such capacitance introduces significant peaking in the frequency response. Larger capacitance values can be driven but must use a small series resistor, RSNUB, at the output of the amplifier, as shown in Figure 56. Adding RSNUB creates a zero that cancels the pole introduced by the load capacitance. Typical values for RSNUB can range from 10 to 50 . The value is typically based on the circuit requirements. Figure 56 also shows another way to reduce the effect of the pole created by the capacitive load (CL) by placing a capacitor (CF) in the feedback loop parallel to the feedback resistor Typical capacitor values can range from 0.5 pF to 2 pF. Figure 59 shows the effect of adding a feedback capacitor to the frequency response. 10F + The distortion performance depends on the following variables: The closed-loop gain of the application Whether it is inverting or noninverting Amplifier loading Signal frequency and amplitude Board layout (12) +VS The ADA4817-1/ADA4817-2 provides excellent performance as a high speed buffer. Figure 52 shows the circuit used for wideband characterization for high gains. The impedance at the summing junction (RF || RG) forms a pole in the loop response of the amplifier with the input capacitance of the amplifier of 1.3 pF. This pole can cause peaking and ringing if its frequency is too low. Feedback resistances of 100 to 400 are recommended because they minimize the peaking and they do not degrade the performance of the output stage. Peaking in the frequency response can also be compensated for with a small feedback capacitor (CF) in parallel with the feedback resistor, or a series resistor in the noninverting input, as shown in Figure 56. 1 2ROCL CF RG RF 0.1F RSNUB VIN 49.9 0.1F VOUT CL RL 10F + VOS VOSnom fP 0.1F -VS 07756-143 RS 07756-047 RG VIN DRIVING CAPACITIVE LOADS Figure 56. RSNUB or CF Used to Reduce Peaking THERMAL CONSIDERATIONS With 10 V power supplies and 19 mA quiescent current, the ADA4817-1/ADA4817-2 dissipate 190 mW with no load. This implies that with the thermal resistances listed in Table 4, the junction temperature is typically almost 25C higher than the ambient temperature. The ADA4817-1/ADA4817-2 can maintain a constant bandwidth over temperature; therefore, an initial ramp up of the current consumption during warm-up is expected. VOS can change up to 0.3 mV due to warm-up effects for an ADA4817-1/ADA4817-2 on 5 V. The input bias current typically increases by a factor of 1.7 for every 10C rise in temperature. Heavy loads increase power dissipation and raise the chip junction temperature as described in the Absolute Maximum Ratings section. Take care not to exceed the rated power dissipation of the package. Rev. F | Page 20 of 31 Data Sheet ADA4817-1/ADA4817-2 POWER-DOWN OPERATION The ADA4817-1/ADA4817-2 are equipped with separate powerdown pins (PD) for each amplifier that allow the user the ability to reduce the quiescent supply current when an amplifier is inactive from 19 mA to below 2 mA. The power-down threshold levels are referenced to the +VS pin. The amplifier is enabled when the PD pin voltage is within 0.9 V of the +VS supply. The amplifier is disabled when the PD pin voltage is at least 3.5 V from the +VS supply. Table 8 shows the required thresholds for power-down with supplies of 5 V and 3 V, -2 V, over temperature. If the PD pin is not used, connect it to the positive power supply to ensure proper start-up. IN 1 2 OUT 07756-359 3 CH1 2.00V CH2 2.00V CH3 200mV Table 8. PD Pin Control CAPACITIVE FEEDBACK When the amplifier is powered down with the supplies of +3 V and -2 V, the PD pin needs to be driven below ground to ensure the power-down. This may be a problem if a microcontroller is being used to drive the PD pin. The circuit in Figure 57 can be added to ensure that the required threshold is met. +VS RF4 3.6k RF3 1k Q2 2N3906 PD_CONTROL 0V TO 3.3V 500ns TO 10s + Q1 2N3904 RF5 11k Due to package variations and pin to pin parasitics between the single and the dual models, the ADA4817-2 has a little more peaking then the ADA4817-1, especially at a gain of 2. The recommended method to tame the peaking is to place a feedback capacitor across the feedback resistor. Figure 59 shows the small signal frequency response of the ADA4817-2 at a gain of 2 vs. CF. At first, no CF was used to show the peaking; but then two other values of 0.5 pF and 1 pF were used to show how to reduce the peaking or even eliminate it. If the power consumption is a factor in the system, using a larger feedback capacitor is acceptable as long as a feedback capacitor is used across it to control the peaking, as shown in Figure 59. However, if power consumption is not an issue, a lower value feedback resistor, such as 200 , does not require any additional feedback capacitance to maintain flatness and lower peaking. PD 9 RF6 20k -V S CF = 0.5pF 07756-358 RF1 3.6k 2.48V Figure 58. Power-Down Operation +3 V, -2 V >2.1 V <-0.5 V +VS M400ms A CH1 T -516.000ms 25.0kS/s 100k POINTS NO CF 6 Figure 57. Power-Down Circuit The plot in Figure 58 shows that the PD pin is driven to the positive rail when the microcontroller logic is high, and to the negative rail when the microcontroller logic is low. The RF5 and RF6 resistors must be chosen to be sufficiently high so that minimal current is drawn by the circuit. CF = 1pF 3 0 -3 -6 RF = 348 G=2 VS = 10V VOUT = 100mV p-p RL = 100 -9 1M 10M 07756-049 5 V >4.1 V <1.5 V CLOSED-LOOP GAIN (dB) Supply Voltages Amplifier Enabled Amplifier Disabled PD 100M 1G 10G FREQUENCY (Hz) Figure 59. Small Signal Frequency Response vs. Feedback Capacitor (ADA4817-2) Rev. F | Page 21 of 31 ADA4817-1/ADA4817-2 Data Sheet There is another package variation problem between the SOIC and the LFCSP package. The SOIC package shows approximately 1 dB to 1.5 dB of additional peaking at a gain of 1, due to the parasitic capacitances in the SOIC package, which is not recommended for very high frequency parts that exceed 1 GHz. A good approach to reduce the peaking is to place a resistor, RS, in series with the noninverting input, which creates a first-order pole formed by RS and CIN, the common-mode input capacitance. Figure 60 shows the higher frequency attenuation, which reduces the peaking but also reduces the -3 dB bandwidth. 6 RS = 75 2pF R 120 Figure 61. RLC Circuit The R in parallel to the series LC forms a notch that can be shaped to compensate for the peaking produced by the amplifier. The result is a smooth 1 GHz -3 dB bandwidth, 250 MHz 0.1 dB flatness, and less than 1 dB of peaking. Place this circuit in the path of the noninverting input when the ADA4817-1/ADA4817-2 are used at a gain of 1. The RLC values may need adjustment depending on the source impedance and the flatness and bandwidth required. Figure 62 shows the frequency response after the RLC circuit is in place. 6 NO RLC RS = 0 3 RS = 100 -3 -6 -9 RL = 100 VS = 5V VOUT = 0.1V p-p G=1 1M 10M 100M FREQUENCY (Hz) 1G 0 RLC -3 -6 10G -9 Figure 60. Small Signal Frequency Response for Various RS (SOIC) RL = 100 VS = 10V VOUT = 100mV p-p G=1 1M As shown in Figure 60, the peaking dropped by almost 2 dB when RS = 0 to RS = 100 , and in return, the -3 dB bandwidth dropped from 1 GHz to 700 MHz. To maintain the -3 dB bandwidth and to reduce peaking, an RLC circuit is recommended instead of RS, as shown in Figure 61. Rev. F | Page 22 of 31 10M 07756-249 CLOSED-LOOP GAIN (dB) 0 07756-247 CLOSED-LOOP GAIN (dB) 10nH RS = 50 3 C L 07756-248 HIGHER FREQUENCY ATTENUATION 100M FREQUENCY (Hz) 1G Figure 62. Frequency Response with RLC Circuit 10G Data Sheet ADA4817-1/ADA4817-2 LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS Laying out the PCB is usually the last step in the design process and often proves to be one of the most critical. A good design can be rendered useless because of poor layout. Because the ADA4817-1/ADA4817-2 can operate into the radio frequency (RF) spectrum, high frequency board layout considerations must be taken into account. The PCB layout, signal routing, power supply bypassing, and grounding all must be addressed to ensure optimal performance. SIGNAL ROUTING The ADA4817-1/ADA4817-2 feature a low distortion pinout with a dedicated feedback pin that allows a compact layout. The dedicated feedback pin reduces the distance from the output to the inverting input, which greatly simplifies the routing of the feedback network. When laying out the ADA4817-1/ADA4817-2 as a unity-gain amplifier, it is recommended to place a short but wide trace between the dedicated feedback pins and the inverting input to the amplifier to minimize stray parasitic inductance. To minimize parasitic inductances, use ground planes under high frequency signal traces. However, remove the ground plane from under the input and output pins to minimize the formation of parasitic capacitors, which degrades phase margin. Run signals are susceptible to noise pickup on the internal layers of the PCB, which can provide maximum shielding. POWER SUPPLY BYPASSING Power supply bypassing is a critical aspect of the PCB design process. For best performance, properly bypass the ADA4817-1/ ADA4817-2 power supply pins. A parallel connection of capacitors from each of the power supply pins to ground works best. Paralleling different values and sizes of capacitors helps ensure that the power supply pins see a low ac impedance across a wide band of frequencies, which is important for minimizing the coupling of noise into the amplifier. Starting directly at the power supply pins, place the smallest value and sized component on the same side of the board as the amplifier, and as close as possible to the amplifier, and connect it to the ground plane. Repeat this process for the next largest value capacitor. It is recommended to use a 0.1 F ceramic, 0508 case for the ADA4817-1/ADA4817-2. The 0508 case offers low series inductance and excellent high frequency performance. The 0.1 F provides low impedance at high frequencies. Place a 10 F electrolytic capacitor in parallel with the 0.1 F. The 10 F electrolytic capacitor provides low ac impedance at low frequencies. Smaller values of electrolytic capacitors can be used depending on the circuit requirements. Additional smaller value capacitors help provide a low impedance path for unwanted noise out to higher frequencies but are not always necessary. Placement of the capacitor returns (grounds) is also important. Returning the grounds of the capacitor close to the amplifier load is critical for distortion performance. Keeping the distance of the capacitors short, but equal from the load, is optimal for performance. In some cases, bypassing between the two supplies can help to improve PSRR and to maintain distortion performance in crowded or difficult layouts. Bypassing is another option to improve performance. Minimizing the trace length and widening the trace from the capacitors to the amplifier reduces the trace inductance. A series inductance with the parallel capacitance can form a tank circuit, which can introduce high frequency ringing at the output. This additional inductance can also contribute to increased distortion due to high frequency compression at the output. Minimize the use of vias in the direct path to the amplifier power supply pins because vias can introduce parasitic inductance, which can lead to instability. When required to use vias, choose multiple large diameter vias because this lowers the equivalent parasitic inductance. GROUNDING The use of ground and power planes is encouraged as a method of providing low impedance returns for power supply and signal currents. Ground and power planes can also help to reduce stray trace inductance and to provide a low thermal path for the amplifier. Do not use ground and power planes under any of the pins. The mounting pads and the ground or power planes can form a parasitic capacitance at the input of the amplifier. Stray capacitance on the inverting input and the feedback resistor form a pole, which degrades the phase margin, leading to instability. Excessive stray capacitance on the output also forms a pole, which degrades phase margin. EXPOSED PAD The ADA4817-1/ADA4817-2 feature an exposed pad, which lowers the thermal resistance by 25% compared to a standard SOIC plastic package. The exposed pad of the ADA4817-1/ ADA4817-2 floats internally, which provides the maximum flexibility and ease of use. It can be connected to the ground plane or to the negative power supply plane. In cases where thermal heating is not an issue, the exposed pad can be left floating. The use of thermal vias or heat pipes can also be incorporated into the design of the mounting pad for the exposed pad. These additional vias help to lower the overall junction to ambient temperature (JA). Using a heavier weight copper on the surface to which the exposed paddle of the amplifier is soldered can greatly reduce the overall thermal resistance seen by the ADA4817-1/ADA4817-2. Rev. F | Page 23 of 31 ADA4817-1/ADA4817-2 Data Sheet LEAKAGE CURRENTS INPUT CAPACITANCE Poor PCB layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias current of the ADA4817-1/ADA4817-2. Any voltage differential between the inputs and nearby runs sets up leakage currents through the PCB insulator, for example, 1 V/ 100 G = 10 pA. Similarly, any contaminants, such as skin oils on the board, can create significant leakage. To reduce leakage significantly, put a guard ring (shield) around the inputs and input leads that are driven to the same voltage potential as the inputs. This way there is no voltage potential between the inputs and surrounding area to set up any leakage currents. For the guard ring to be completely effective, it must be driven by a relatively low impedance source and it must completely surround the input leads on all sides (above and below) when using a multilayer board. Along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. A few picofarads of capacitance reduces the input impedance at high frequencies, in turn increasing the gain of the amplifier, causing peaking of the frequency response or even oscillations if severe enough. It is recommended to place the external passive components connected to the input pins as close as possible to the inputs to avoid parasitic capacitance. The ground and power planes must be kept at a small distance from the input pins on all layers of the board. Another effect that can cause leakage currents is the charge absorption of the insulator material itself. Minimizing the amount of material between the input leads and the guard ring helps to reduce the absorption. In addition, low absorption materials, such as Teflon(R) or ceramic, can be necessary in some instances. INPUT-TO-INPUT/OUTPUT COUPLING To minimize capacitive coupling between the inputs and outputs, ensure that the output signal traces are not parallel with the inputs. In addition, ensure that the input traces are not close to each other. A minimum of 7 mils between the two inputs is recommended. Rev. F | Page 24 of 31 Data Sheet ADA4817-1/ADA4817-2 APPLICATIONS INFORMATION LOW DISTORTION PINOUT The ADA4817-1/ADA4817-2 feature a low distortion pinout from Analog Devices. The new pinout provides two advantages over the traditional pinout. The first advantage is improved second harmonic distortion performance, which is accomplished by the physical separation of the noninverting input pin and the negative power supply pin. The second advantage is the simplification of the layout due to the dedicated feedback pin and easy routing of the gain set resistor back to the inverting input pin. This pinout allows a compact layout, which helps to minimize parasitics and increase stability. The designer does not need to use the dedicated feedback pin to provide feedback for the ADA4817-1/ADA4817-2. The output pin of the ADA4817-1/ADA4817-2 can still be used to provide feedback to the inverting input of the ADA4817-1/ADA4817-2. WIDEBAND PHOTODIODE PREAMP The wide bandwidth and low noise of the ADA4817-1/ ADA4817-2 make it an ideal choice for transimpedance amplifiers, such as those used for signal conditioning with high speed photodiodes. Figure 63 shows a current to voltage converter with an electrical model of a photodiode. The basic transfer function is The CF value that produces f(45) is shown to be (13) 1 sCF RF CS C M C D 2 RF fCR Figure 64 shows the preamplifier output noise over frequency. f1 = 1 2 RF (CF + CS + CM + CD) f2 = 1 2 RFCF VOLTAGE NOISE (nV/ Hz) CF RF IPHOTO RSH = CS CM CD VB f3 = fCR (CF + CS + CM + CD)/CF RF NOISE VEN (CF + CS + CM + CD)/CF f3 f2 f1 VOUT 07756-048 CM (15) The frequency response shows less peaking if larger CF values are used. where: IPHOTO is the output current of the photodiode. RF and CF are the parallel combination that sets the signal bandwidth. 1011 (14) where: fCR is the amplifier crossover frequency. RF is the feedback resistor. CS is the source capacitance including the photodiode and the board parasitic. CM is the common-mode capacitance of the amplifier. CD is the differential capacitance of the amplifier. CF I PHOTO RF fCR 2 RF (CS C M CD ) f(45) Figure 63. Wideband Photodiode Preamp VEN NOISE DUE TO AMPLIFIER FREQUENCY (Hz) Figure 64. Photodiode Voltage Noise Contributions Rev. F | Page 25 of 31 07756-043 VOUT The stable bandwidth attainable with this preamp is a function of RF, the gain bandwidth product of the amplifier, and the total capacitance at the summing junction of the amplifier, including the photodiode capacitance (CS) and the amplifier input capacitance. RF and the total capacitance produce a pole in the loop transmission of the amplifier that can result in peaking and instability. Adding CF creates a zero in the loop transmission that compensates for the effect of the pole and reduces the signal bandwidth. It can be shown that the signal bandwidth obtained with a 45 phase margin (f(45)) is defined by ADA4817-1/ADA4817-2 Data Sheet 45 The loop transmission zero introduced by CF limits the amplification. The noise gain bandwidth extends past the preamp signal bandwidth and is eventually rolled off by the decreasing loop gain of the amplifier. The current equivalent noise from the inverting terminal is typically negligible for most applications. The innovative architecture used in the ADA4817-1/ADA4817-2 makes balancing both inputs unnecessary, as opposed to traditional FET input amplifiers. Therefore, minimizing the impedance seen from the noninverting terminal to ground at all frequencies is critical for optimal noise performance. 40 35 MAGNITUDE (dB) 30 25 20 15 10 5 07756-051 G = 63V/V R = 100 0 V L = 10V S VOUT = 6V p-p -5 0.1 1 10 100 1000 FREQUENCY (MHz) Figure 65. Photodiode Preamp Frequency Response The pole in the loop transmission translates to a zero in the noise gain of the amplifier, leading to an amplification of the input voltage noise over frequency. Integrating the square of the output voltage noise spectral density over frequency and then taking the square root allows the user to obtain the total rms output noise of the preamp. Table 9 summarizes approximations for the amplifier and feedback and source resistances. Noise components for an example preamp with RF = 50 k, CS = 30 pF, and CF = 0.5 pF (bandwidth of about 6.4 MHz) are also listed. VEN is the equivalent voltage noise and IEN is the equivalent current noise. Table 9. RMS Noise Contributions of Photodiode Preamp Contributor RF VEN Amp IEN Amp Expression RMS Noise with RF = 50 k, CS = 30 pF, CF = 0.5 pF 94 V 4kT RF f 2 1.57 VEN CS C M C D C F IEN RF CF f 3 1.57 777.5 V 0.4 V f 2 1.57 Total 783 V Rev. F | Page 26 of 31 Data Sheet ADA4817-1/ADA4817-2 The system bandwidth for G = 1 is 400 MHz. For gains higher than 2, the bandwidth is set by the preamp, and it can be approximated by HIGH SPEED JFET INPUT INSTRUMENTATION AMPLIFIER Figure 66 shows an example of a high speed instrumentation amplifier with a high input impedance using the ADA4817-1/ ADA4817-2. The dc transfer function is 2R VOUT VN VP 1 F RG In-amp-3 dB = (fCR x RG)/(2 x RF) The match of resistor ratios, R1:R2 to R3:R4, primarily determine the common-mode rejection of the in-amp and it is estimated by (16) VO 1 2 VCM 1 1 2 For G = 1, it is recommended that the feedback resistors for the two preamps be set to 0 and the gain resistor be open. (17) The summing junction impedance for the preamps is equal to RF || 0.5(RG). Keep this value relatively low to improve the bandwidth response like in the previous example. VCC 0.1F 10F RS1 VN R2 350 ADA4817-2 U1 0.1F VCC 10F VEE 0.1F R1 350 10F RF = 500 VO ADA4817-1 RG R3 350 RF = 500 0.1F 10F VCC R4 350 0.1F VEE 10F ADA4817-2 U2 0.1F VP 10F 07756-050 RS2 VEE Figure 66. High Speed Instrumentation Amplifier Rev. F | Page 27 of 31 Data Sheet ADA4817-1/ADA4817-2 Resistor values are kept low for minimal noise contribution, offset voltage, and optimal frequency response. Due to the low capacitance values used in the filter circuit, the PCB layout and minimization of parasitics is critical. A few picofarads can detune the corner frequency, fC, of the filter. The capacitor values shown in Figure 68 actually incorporate some stray PCB capacitance. ACTIVE LOW-PASS FILTER (LPF) Active low-pass filters are used in many applications such as antialiasing filters and high frequency communication intermediate frequency (IF) strips. With a 410 MHz gain bandwidth product and high slew rate, the ADA4817-1/ADA4817-2 is an ideal candidate for active filters. Moreover, thanks to the low input bias current provided by the FET stage, the ADA4817-1/ADA4817-2 eliminate any dc errors. Figure 67 shows the frequency response of 90 MHz and 45 MHz LPFs. In addition to the bandwidth requirements, the slew rate must be capable of supporting the full power bandwidth of the filter. In this case, a 90 MHz bandwidth with a 2 V p-p output swing requires at least 870 V/s. This performance is achievable at 90 MHz only because of the wide bandwidth and high slew rate of the ADA4817-1/ADA4817-2. The circuit shown in Figure 68 is a 4-pole, Sallen-Key LPF. The filter comprises two identical cascaded Sallen-Key LPF sections, each with a fixed gain of G = 2. The net gain of the filter is equal to G = 4 or 12 dB. The actual gain shown in Figure 67 is 12 dB. This gain does not take into account the output voltage being divided in half by the series matching termination resistor, RT, and the load resistor. Setting the resistors equal to each other greatly simplifies the design equations for the Sallen-Key filter. To achieve 90 MHz, set the R value to 182 . However, if the R value is doubled, the corner frequency is cut in half to 45 MHz, which is a straightforward approach to tune the filter by multiplying the R value (182 ) by the ratio of 90 MHz and the new corner frequency in megahertz. Figure 67 shows the output of each stage of the filter and the two different filters corresponding to R = 182 and R = 365 . It is not recommended to increase the corner frequency beyond 90 MHz due to bandwidth and slew rate limitations, unless unity-gain stages are acceptable. 15 12 9 6 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 100k OUT2, f = 90MHz OUT1, f = 90MHz OUT1, f = 45MHz OUT2, f = 45MHz 1M C3 3.9pF 10F +5V RT 49.9 U1 R 0.1F R C2 5.6pF 10F 10F OUT1 U2 R C4 5.6pF 0.1F RT 49.9 10F OUT2 0.1F 0.1F -5V R2 348 -5V R1 348 R4 348 Figure 68. 4-Pole, Sallen-Key LPF (ADA4817-2) Rev. F | Page 28 of 31 R3 348 07756-054 +IN1 R 100M Figure 67. Low-Pass Filter Response C1 3.9pF +5V 10M FREQUENCY (Hz) 1G 07756-062 MAGNITUDE (dB) Capacitor selection is critical for optimal filter performance. Capacitors with low temperature coefficients, such as NPO ceramic capacitors and silver mica, are good choices for filter elements. Data Sheet ADA4817-1/ADA4817-2 1.2 0.15 0.10 0.8 90MHz 90MHz 45MHz 45MHz 0.4 0 -0.05 -0.4 -0.10 -0.8 -0.15 TIME (5ns/DIV) -1.2 TIME (5ns/DIV) Figure 70. Large Signal Transient Response (Low-Pass Filter) Figure 69. Small Signal Transient Response (Low-Pass Filter) Rev. F | Page 29 of 31 07756-064 VOLTAGE (V) 0 07756-063 VOLTAGE (V) 0.05 ADA4817-1/ADA4817-2 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 SQ 2.90 DETAIL A (JEDEC 95) 1.84 1.74 1.64 0.50 BSC 8 5 PIN 1 INDEX AREA 1.55 1.45 1.35 EXPOSED PAD 0.50 0.40 0.30 BOTTOM VIEW 0.30 0.25 0.20 PKG-003886 SEATING PLANE FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SIDE VIEW PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 02-10-2017-A 0.80 0.75 0.70 1 4 TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-229-WEED-4 Figure 71. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-8-13) Dimensions shown in millimeters 5.00 4.90 4.80 2.29 0.356 6.20 6.00 5.80 5 4.00 3.90 3.80 2.29 0.457 4 1 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. BOTTOM VIEW 1.27 BSC 3.81 REF TOP VIEW 1.65 1.25 1.75 1.35 SEATING PLANE 0.51 0.31 0.50 0.25 0.10 MAX 0.05 NOM COPLANARITY 0.10 8 0 45 0.25 0.17 1.04 REF 1.27 0.40 COMPLIANT TO JEDEC STANDARDS MS-012-A A Figure 72. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] (RD-8-1) Dimensions shown in millimeters Rev. F | Page 30 of 31 06-02-2011-B 8 Data Sheet ADA4817-1/ADA4817-2 DETAIL A (JEDEC 95) PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 16 13 1 12 *2.40 EXPOSED PAD 2.35 SQ 2.30 4 9 0.80 0.75 0.70 SIDE VIEW PKG-004024 SEATING PLANE 5 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WGGC-3 WITH EXCEPTION TO THE EXPOSED PAD. 03-30-2017-B TOP VIEW 0.50 0.40 0.30 Figure 73.16-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body and 0.75 mm Package Height (CP-16-20) Dimensions shown in millimeters ORDERING GUIDE Model1 ADA4817-1ACPZ-RL ADA4817-1ACPZ-R7 ADA4817-1ARDZ ADA4817-1ARDZ-RL ADA4817-1ARDZ-R7 ADA4817-2ACPZ-RL ADA4817-2ACPZ-R7 ADA4817-2ACP-EBZ 1 Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C Package Description 8-Lead Lead Frame Chip Scale Package [LFCSP] 8-Lead Lead Frame Chip Scale Package [LFCSP] 8-Lead Standard Small Outline Package with Exposed Pad 8-Lead Standard Small Outline Package with Exposed Pad 8-Lead Standard Small Outline Package with Exposed Pad 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board for 16-Lead LFCSP Z = RoHS Compliant Part. (c)2008-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07756-0-6/18(F) Rev. F | Page 31 of 31 Package Option CP-8-13 CP-8-13 RD-8-1 RD-8-1 RD-8-1 CP-16-20 CP-16-20 Ordering Quantity 5000 1500 1 2500 1000 5000 1500 Marking Code H1F H1F Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: ADA4817-1ACP-EBZ ADA4817-1ARD-EBZ EVAL-CN0273-EB1Z