MCP6N11 500 kHz, 800 A Instrumentation Amplifier Features Description * Rail-to-Rail Input and Output * Gain Set by 2 External Resistors * Minimum Gain (GMIN) Options: 1, 2, 5, 10 or 100 V/V * Common Mode Rejection Ratio (CMRR): 115 dB (typical, GMIN = 100) * Power Supply Rejection Ratio (PSRR): 112 dB (typical, GMIN = 100) * Bandwidth: 500 kHz (typical, Gain = GMIN) * Supply Current: 800 A/channel (typical) * Single Channel * Enable/VOS Calibration pin: (EN/CAL) * Power Supply: 1.8V to 5.5V * Extended Temperature Range: -40C to +125C Microchip Technology Inc. offers the single MCP6N11 instrumentation amplifier (INA) with Enable/VOS Calibration pin (EN/CAL) and several minimum gain options. It is optimized for single-supply operation with rail-to-rail input (no common mode crossover distortion) and output performance. Typical Applications Typical Application Circuit * * * * High Side Current Sensor Wheatstone Bridge Sensors Difference Amplifier with Level Shifting Power Control Loops Two external resistors set the gain, minimizing gain error and drift-over temperature. The reference voltage (VREF) shifts the output voltage (VOUT). The supply voltage range (1.8V to 5.5V) is low enough to support many portable applications. All devices are fully specified from -40C to +125C. These parts have five minimum gain options (1, 2, 5, 10 and 100 V/V). This allows the user to optimize the input offset voltage and input noise for different applications. 10 VDD VBAT +1.8V to +5.5V IDD U1 MCP6N11 Design Aids * Microchip Advanced Part Selector (MAPS) * Demonstration Board * Application Notes VFG VOUT RF 200 k RG 10 k VREF Block Diagram Package Types VOUT VOUT RF RG VREF VIP VIM VDD VSS RM4 I4 VFG VREF GM2 I2 I1 VIP VIM GM1 POR I3 GM3 VTR MCP6N11 SOIC MCP6N11 2x3 TDFN * VFG 1 8 EN/CAL VFG 1 VIM 2 7 VDD VIM 2 VIP 3 VSS 4 6 VOUT 5 VREF VSS 4 VIP 3 8 EN/CAL EP 9 7 VDD 6 VOUT 5 VREF * Includes Exposed Thermal Pad (EP); see Table 3-1. Low Power VOS Calibration EN/CAL (c) 2011 Microchip Technology Inc. DS25073A-page 1 MCP6N11 Minimum Gain Options Table 1 shows key specifications that differentiate between the different minimum gain (GMIN) options. See Section 1.0 "Electrical Characteristics", Section 6.0 "Packaging Information" and Product Identification System for further information on GMIN. TABLE 1: KEY DIFFERENTIATING SPECIFICATIONS Part No. GMIN VOS VOS/TA CMRR (dB) PSRR (dB) (V/V) (mV) (V/C) Min. Nom. Max. Typ. VDD = 5.5V Min. MCP6N11-001 1 MCP6N11-002 MCP6N11-005 eni Eni (VP-P) (nV/Hz) Nom. Nom. (f = 0.1 to 10 Hz) (f = 10 kHz) VDMH (V) Max. GBWP (MHz) Nom. 0.50 570 950 3.0 90 70 62 2.70 2 2.0 45 78 68 1.35 1.0 285 475 5 0.85 18 80 75 0.54 2.5 114 190 MCP6N11-010 10 0.50 9.0 81 81 0.27 5.0 57 95 MCP6N11-100 100 0.35 2.7 88 86 0.027 35 18 35 DS25073A-page 2 (c) 2011 Microchip Technology Inc. MCP6N11 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings VDD - VSS .......................................................................6.5V Current at Input Pins ...............................................2 mA Analog Inputs (VIP and VIM) ..... VSS - 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS - 0.3V to VDD + 0.3V Difference Input Voltage....................................... |VDD - VSS| Output Short Circuit Current ................................ Continuous Current at Output and Supply Pins ............................30 mA Storage Temperature ...................................-65C to +150C Max. Junction Temperature ........................................ +150C ESD protection on all pins (HBM, CDM, MM) . 2 kV, 1.5 kV, 300V 1.2 Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. See Section 4.2.1.2 "Input Voltage Limits" and Section 4.2.1.3 "Input Current Limits". Specifications TABLE 1-1: DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL and GDM = GMIN; see Figure 1-6 and Figure 1-7. Parameters Sym Min Typ Max Units GMIN Conditions Input Offset Input Offset Voltage, Calibrated Input Offset Voltage Trim Step Input Offset Voltage Drift Power Supply Rejection Ratio Note 1: 2: 3: 4: 5: 6: 7: VOS VOSTRM VOS/TA PSRR -3.0 -- +3.0 mV 1 -2.0 -- +2.0 mV 2 -0.85 -- +0.85 mV 5 -0.50 -- +0.50 mV 10 -0.35 -- +0.35 mV 100 -- 0.36 -- mV 1 -- 0.21 -- mV 2 -- 0.077 -- mV 5 -- 0.045 -- mV 10 -- 0.014 -- mV 100 -- 90/GMIN -- -- 2.7 -- (Note 2) V/C 1 to 10 TA= -40C to +125C (Note 3) 100 V/C 62 82 -- dB 1 68 88 -- dB 2 75 96 -- dB 5 81 102 -- dB 10 86 112 -- dB 100 VCM = (VIP + VIM) / 2, VDM = (VIP - VIM) and GDM = 1 + RF/RG. The VOS spec limits include 1/f noise effects. This is the input offset drift without VOS re-calibration; toggle EN/CAL to minimize this effect. These specs apply to both the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (VREF takes VCM's place). This spec applies to the VIP, VIM, VREF and VFG pins individually. Figure 2-11 and Figure 2-19 show the VIVR and VDMR variation over temperature. See Section 1.5 "Explanation of DC Error Specs". (c) 2011 Microchip Technology Inc. DS25073A-page 3 MCP6N11 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL and GDM = GMIN; see Figure 1-6 and Figure 1-7. Parameters Sym Min Typ Max Units GMIN Conditions -- 10 -- pA all -- 80 -- pA TA= +85C TA= +125C Input Current and Impedance (Note 4) Input Bias Current IB Across Temperature Across Temperature Input Offset Current IOS 0 2 5 nA -- 1 -- pA Across Temperature -- 5 -- pA TA= +85C Across Temperature -1 0.05 +1 nA TA= +125C Common Mode Input Impedance ZCM -- 1013||6 -- ||pF Differential Input Impedance ZDIFF -- 1013||3 -- ||pF Input Common Mode Voltage (VCM or VREF) (Note 4) Input Voltage Range Common Mode Rejection Ratio Common Mode Non-Linearity Note 1: 2: 3: 4: 5: 6: 7: VIVL -- -- VSS - 0.2 V VIVH VDD + 0.15 -- -- V CMRR 62 79 -- 69 87 -- 75 101 79 INLCM all (Note 5, Note 6) dB 1 dB 2 VCM = VIVL to VIVH, VDD = 1.8V -- dB 5 107 -- dB 10 86 119 -- dB 100 70 94 -- dB 1 78 100 -- dB 2 80 108 -- dB 5 81 114 -- dB 10 88 115 -- dB 100 -1000 115 +1000 ppm 1 -570 27 +570 ppm 2 -230 11 +230 ppm 5 -125 6 +125 ppm 10 -50 2 +50 ppm 100 -400 42 +400 ppm 1 -220 10 +220 ppm 2 -100 4 +100 ppm 5 -50 2 +50 ppm 10 -30 1 +30 ppm 100 VCM = VIVL to VIVH, VDD = 5.5V VCM = VIVL to VIVH, VDM = 0V, VDD = 1.8V (Note 7) VCM = VIVL to VIVH, VDM = 0V, VDD = 5.5V (Note 7) VCM = (VIP + VIM) / 2, VDM = (VIP - VIM) and GDM = 1 + RF/RG. The VOS spec limits include 1/f noise effects. This is the input offset drift without VOS re-calibration; toggle EN/CAL to minimize this effect. These specs apply to both the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (VREF takes VCM's place). This spec applies to the VIP, VIM, VREF and VFG pins individually. Figure 2-11 and Figure 2-19 show the VIVR and VDMR variation over temperature. See Section 1.5 "Explanation of DC Error Specs". DS25073A-page 4 (c) 2011 Microchip Technology Inc. MCP6N11 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL and GDM = GMIN; see Figure 1-6 and Figure 1-7. Parameters Sym Min Typ Max Units GMIN Conditions all Input Differential Mode Voltage (VDM) (Note 4) Differential Input Voltage Range VDML -2.7/GMIN -- -- V VDMH -- -- +2.7/GMIN V VREF = (VDD - GDMVDM)/2 (Note 6) VDM = VDML to VDMH, Differential Gain Error gE -1 0.13 +1 % Differential Gain Drift gE/TA -- 0.0006 -- %/C Differential Non-Linearity DC Open-Loop Gain INLDM AOL VREF = (VDD - GDMVDM)/2 -500 30 +500 ppm 1 -800 40 +800 ppm 2, 5 (Note 7) -2000 100 +2000 ppm 10, 100 61 84 -- dB 1 VDD = 1.8V, VOUT = 0.2V to 1.6V 68 90 -- dB 2 76 98 -- dB 5 78 104 -- dB 10 86 116 -- dB 100 70 94 -- dB 1 VDD = 5.5V, 77 100 -- dB 2 VOUT = 0.2V to 5.3V 84 108 -- dB 5 90 114 -- dB 10 97 125 -- dB 100 -- -- VSS + 15 mV all -- -- VSS + 25 mV VDM = -VDD/(2GDM), VDD = 5.5V, VREF = VDD/2 - 1V VDD - 15 -- -- mV VDM = VDD/(2GDM), VDD = 1.8V, VREF = VDD/2 + 1V VDD - 25 -- -- mV VDM = VDD/(2GDM), VDD = 5.5V, VREF = VDD/2 + 1V -- 8 -- mA VDD = 1.8V -- 30 -- mA VDD = 5.5V VDD 1.8 -- 5.5 V IQ 0.5 0.8 1.1 mA VPRL 1.1 1.4 -- V VPRH -- 1.4 1.7 V Output Minimum Output Voltage Swing Maximum Output Voltage Swing Output Short Circuit Current VOL VOH ISC VDM = -VDD/(2GDM), VDD = 1.8V, VREF = VDD/2 - 1V Power Supply Supply Voltage Quiescent Current per Amplifier POR Trip Voltage Note 1: 2: 3: 4: 5: 6: 7: all IO = 0 VCM = (VIP + VIM) / 2, VDM = (VIP - VIM) and GDM = 1 + RF/RG. The VOS spec limits include 1/f noise effects. This is the input offset drift without VOS re-calibration; toggle EN/CAL to minimize this effect. These specs apply to both the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (VREF takes VCM's place). This spec applies to the VIP, VIM, VREF and VFG pins individually. Figure 2-11 and Figure 2-19 show the VIVR and VDMR variation over temperature. See Section 1.5 "Explanation of DC Error Specs". (c) 2011 Microchip Technology Inc. DS25073A-page 5 MCP6N11 TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = 25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. Parameters Sym Min Typ -- 0.50 GMIN -- 35 Max Units GMIN -- MHz 1 to 10 -- MHz 100 Conditions AC Response Gain Bandwidth Product GBWP Phase Margin PM -- 70 -- all Open-Loop Output Impedance ROL -- 0.9 -- k 1 to 10 -- 0.6 -- k 100 -- 94 -- dB all Power Supply Rejection Ratio PSRR Common Mode Rejection Ratio CMRR -- 104 -- dB -- 94 -- dB -- 3 -- V/s -- 9 -- V/s -- 2 -- V/s f < 10 kHz 1 to 10 f < 10 kHz 100 f < 10 kHz Step Response Slew Rate SR 1 to 10 VDD = 1.8V VDD = 5.5V 100 VDD = 1.8V -- 6 -- V/s Overdrive Recovery, Input Common Mode tIRC -- 10 -- s VDD = 5.5V Overdrive Recovery, Input Differential Mode tIRD -- 5 -- s VDM = VDML - (0.5V)/GMIN (or VDMH + (0.5V)/GMIN) to 0V, VREF = (VDD - GDMVDM)/2, 90% of VOUT change Overdrive Recovery, Output tOR -- 8 -- s GDM = 2GMIN, GDMVDM = 0.5VDD to 0V, VREF = 0.75VDD (or 0.25VDD), 90% of VOUT change Eni -- 570/GMIN -- VP-P -- 18 -- VP-P -- 950/GMIN -- nV/Hz 1 to 10 f = 100 kHz -- 35 -- nV/Hz 100 -- 1 -- fA/Hz all all VCM = VSS - 1V (or VDD + 1V) to VDD/2, GDMVDM = 0.1V, 90% of VOUT change Noise Input Noise Voltage Input Noise Voltage Density eni Input Current Noise Density ini DS25073A-page 6 1 to 10 f = 0.1 Hz to 10 Hz 100 f = 1 kHz (c) 2011 Microchip Technology Inc. MCP6N11 TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = 25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. Parameters Sym Min Typ Max Units GMIN Conditions EN/CAL Low Specifications EN/CAL Logic Threshold, Low VIL VSS -- 0.2 VDD V EN/CAL Input Current, Low IENL -- -0.1 -- nA EN/CAL = 0V -7 -2.5 -- A EN/CAL = 0V, VDD = 5.5V -- 10 -- nA EN/CAL = 0V VDD V GND Current ISS Amplifier Output Leakage IO(LEAK) all EN/CAL High Specifications EN/CAL Logic Threshold, High VIH 0.8 VDD EN/CAL Input Current, High IENH -- -0.01 -- nA all EN/CAL = VDD EN/CAL Dynamic Specifications EN/CAL Input Hysteresis VHYST -- 0.2 -- V EN/CAL Low to Amplifier Output High-Z Turn-off Time tOFF -- 3 10 s EN/CAL = 0.2VDD to VOUT = 0.1(VDD/2), VDMGDM = 1 V, VL = 0V EN/CAL High to Amplifier Output On Time tON 12 20 28 ms EN/CAL = 0.8VDD to VOUT = 0.9(VDD/2), VDMGDM = 1 V, VL = 0V EN/CAL Low to tENLH EN/CAL High low time Amplifier On to tENOL EN/CAL Low Setup Time POR Dynamic Specifications VDD to Output Off tPHL 100 -- -- s Minimum time before externally releasing EN/CAL (Note 1) -- 100 -- s -- 10 -- s VDD to Output On 140 250 360 ms Note 1: tPLH all all VL = 0V, VDD = 1.8V to VPRL - 0.1V step, 90% of VOUT change VL = 0V, VDD = 0V to VPRH + 0.1V step, 90% of VOUT change For design guidance only; not tested. TABLE 1-4: TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = 1.8V to 5.5V, VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 -- +125 C Operating Temperature Range TA -40 -- +125 C Storage Temperature Range TA -65 -- +150 C Thermal Resistance, 8L-SOIC JA -- 150 -- C/W Thermal Resistance, 8L-TDFN (2x3) JA -- 53 -- C/W Conditions Temperature Ranges (Note 1) Thermal Package Resistances Note 1: Operation must not cause TJ to exceed the Absolute Maximum Junction Temperature specification (+150C). (c) 2011 Microchip Technology Inc. DS25073A-page 7 MCP6N11 1.3 Timing Diagrams tENLH VDM (1V)/GDM EN/CAL tENOL tOFF VCM VOUT tIRC FIGURE 1-5: High-Z tON EN/CAL Timing Diagram. VOUT FIGURE 1-1: Common Mode Input Overdrive Recovery Timing Diagram. VCM VDD/2 VDM tIRD VOUT FIGURE 1-2: Differential Mode Input Overdrive Recovery Timing Diagram. VCM VDD/2 VDM tOR VOUT FIGURE 1-3: Timing Diagram. Output Overdrive Recovery 1.8V VPRL - 0.1V VDD tPHL VOUT FIGURE 1-4: DS25073A-page 8 High-Z VPRH + 0.1V 0V tPLH POR Timing Diagram. (c) 2011 Microchip Technology Inc. MCP6N11 1.4 1.4.1 DC Test Circuits 1.4.2 INPUT OFFSET TEST CIRCUIT Figure 1-6 is used for testing the INA's input offset errors and input voltage range (VE, VIVL and VIVH; see Section 1.5.1 "Input Offset Related Errors" and Section 1.5.2 "Input Offset Common Mode Nonlinearity"). U2 is part of a control loop that forces VOUT to equal VCNT; U1 can be set to any bias point. VDD VCM 2.2 F VL 100 nF VOUT RL 1 k 1 k Figure 1-7 is used for testing the INA's differential gain error, non-linearity and input voltage range (gE, INLDM, VDML and VDMH; see Section 1.5.3 "Differential Gain Error and Non-linearity"). RF and RG are 0.01% for accurate gain error measurements. VDD VL VCM + VDM/2 2.2 F 1 k 100 nF MCP6N11 MCP6N11 VFG VCM - VDM/2 VM MCP6H01 63.4 k FIGURE 1-7: Mode. RCNT 63.4 k CCNT 10 nF 100 nF VCNT 6.34 k + VM - Test Circuit for Differential EQUATION 1-2: G DM = 1 + RF RG V OUT = V REF + G DM ( 1 + g E ) ( V DM + VE ) V M = VOUT - VREF When MCP6N11 is in its normal range of operation, the DC output voltages are (where VE is the sum of input offset errors and gE is the gain error): = G DM ( 1 + g E ) ( VDM + V E ) To keep VREF, VFG and VOUT within their ranges, set: EQUATION 1-1: EQUATION 1-3: G DM = 1 + R F R G V REF = ( V DD - G DM V DM ) 2 V OUT = V CNT V M = V REF + G DM ( 1 + g E )V E Table 1-5 gives the recommended RF and RG values for different GMIN options. SELECTING RF AND RG Table 1-6 shows the recommended RF and RG. They produce a 10 k load; VL can usually be left open. TABLE 1-6: GMIN (V/V) Nom. SELECTING RF AND RG RF () Nom. GMIN (V/V) Nom. RF () Nom. RG () Nom. GDM (V/V) Nom. GDMVOS (V) Max. BW (kHz) Nom. 1 100k 499 201.4 0.60 2.5 0.40 5.0 5 100k 100 1001 0.85 2.5 10 10 0.50 5.0 100 10.0k 100 0.35 35 2 5 100 nF The output voltages are (where VE is the sum of input offset errors and gE is the gain error): FIGURE 1-6: Test Circuit for Common Mode (Input Offset). TABLE 1-5: RG 0.01% 6.34 k VREF U2 12.7 k VOUT RF 0.01% RG RF RL U1 1 k U1 VREF DIFFERENTIAL GAIN TEST CIRCUIT (c) 2011 Microchip Technology Inc. RG () Nom. GDM (V/V) Nom. 1 0 Open 1.000 2 4.99k 4.99k 2.000 8.06k 2.00k 5.030 9.09k 1.00k 10.09 100 101.0 DS25073A-page 9 MCP6N11 1.5 Explanation of DC Error Specs 1.5.1 Based on the measured VE data, we obtain the following linear fit: INPUT OFFSET RELATED ERRORS The input offset error (VE) is extracted from input offset measurements (see Section 1.4.1 "Input Offset Test Circuit"), based on Equation 1-1: EQUATION 1-6: V CM - VDD 2 V E_LIN = VOS + ----------------------------------CMRR Where: EQUATION 1-4: VOS = V 2 V3 - V1 1 ----------------- = -----------------------------CMRR V IVH - VIVL V M - V REF V E = --------------------------------G DM ( 1 + g E ) VE has several terms, which assume a linear response to changes in VDD, VSS, VCM, VOUT and TA (all of which are in their specified ranges): The remaining error (VE) is described by the Common Mode Non-Linearity spec: EQUATION 1-7: EQUATION 1-5: V DD - V SS V CM V REF V E = V OS + --------------------------------- + ----------------- + ----------------PSRR CMRR CMRR V OUT V OS + ----------------- + T A ------------A OL TA Where: PSRR, CMRR and AOL are in units of V/V TA is in units of C Where: VE = VE - VE_LIN The same common mode behavior applies to VE when VREF is swept, instead of VCM, since both input stages are designed the same: EQUATION 1-8: VDM = 0 VREF - V DD 2 VE_LIN = V OS + ------------------------------------CMRR max V E INL CM = -----------------------------VIVH - V IVL Equation 1-2 shows how VE affects VOUT. 1.5.2 max V E INL CM = -----------------------------VIVH - V IVL INPUT OFFSET COMMON MODE NON-LINEARITY The input offset error (VE) changes non-linearly with VCM. Figure 1-8 shows VE vs. VCM, as well as a linear fit line (VE_LIN) based on VOS and CMRR. The op amp is in standard conditions (VOUT = 0, VDM = 0, etc.). VCM is swept from VIVL to VIVH. The test circuit is in Section 1.4.1 "Input Offset Test Circuit" and VE is calculated using Equation 1-4. VE, VE_LIN (V) VE_LIN V3 1.5.3 DIFFERENTIAL GAIN ERROR AND NON-LINEARITY The differential errors are extracted from differential gain measurements (see Section 1.4.2 "Differential Gain Test Circuit"), based on Equation 1-2. These errors are the differential gain error (gE) and the input offset error (VE, which changes non-linearly with VDM): EQUATION 1-9: VE G DM = 1 + RF RG V2 VM = G DM ( 1 + g E ) ( V DM + VE ) V1 These errors are adjusted for the expected output, then referred back to the input, giving the differential input error (VED) as a function of VDM: VE VIVL VCM (V) VDD/2 VIVH FIGURE 1-8: Input Offset Error vs. Common Mode Input Voltage. DS25073A-page 10 EQUATION 1-10: VM V ED = ------------ - V DM G DM (c) 2011 Microchip Technology Inc. MCP6N11 Figure 1-9 shows VED vs. VDM, as well as a linear fit line (VED_LIN) based on VE and gE. The op amp is in standard conditions (VOUT = 0, etc.). VDM is swept from VDML to VDMH. VED, VED_LIN (V) VED_LIN V3 VED V2 V1 VED VDML VDM (V) 0 VDMH FIGURE 1-9: Differential Input Error vs. Differential Input Voltage. Based on the measured VED data, we obtain the following linear fit: EQUATION 1-11: VED_LIN = ( 1 + g E )VE + g E V DM Where: V3 - V 1 g E = ----------------------------------- - 1 V DMH - V DML V2 VE = ---------------1 + gE Note that the VE value measured here is not as accurate as the one obtained in Section 1.5.1 "Input Offset Related Errors". The remaining error (VED) is described by the Differential Mode Non-Linearity spec: EQUATION 1-12: max V ED INL DM = ----------------------------------VDMH - V DML Where: VED = V ED - VED_LIN (c) 2011 Microchip Technology Inc. DS25073A-page 11 MCP6N11 NOTES: DS25073A-page 12 (c) 2011 Microchip Technology Inc. MCP6N11 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. DC Voltages and Currents 25% 20% GMIN = 1 GMIN = 2 to 10 15% 10% 5% No VOS Re-calibration 330 Samples p GMIN = 1 to 10 VDD = 5.5V RTO 15% 10% 5% 330 Samples GMIN = 100 TA = +25C VDD = 1.8V and 5.5V RTO 12% 10% 8% 6% 4% 2% 600 500 300 400 4 200 2 0 100 -100 200 -2 FIGURE 2-3: Normalized Input Offset Voltage Drift, with GMIN = 1 to 10. 18% Perce entage of Occ currenc ces 16% 14% 12% No VOS Re-calibration 330 Samples p GMIN = 100 VDD = 5.5V RTO 10% 8% 6% 4% 2% FIGURE 2-2: Normalized Input Offset Voltage, with GMIN = 100. (c) 2011 Microchip Technology Inc. 1200 1 800 600 400 0 200 -200 -400 -600 1000 1 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 Normalized Input Offset Voltage; GMINVOS (mV) -1 1000 0% 0% -1 1200 P Percent tage off Occurrences 14% -300 2.0 0 1.6 6 1.2 2 0.8 8 0.4 4 0.0 0 -0.4 4 -0.8 8 -1.2 2 -1.6 6 -2.0 0 Normalized Input Offset Voltage Drift; GMIN(VOS/TA) (V/C) Normalized Input Offset Voltage; GMINVOS (mV) FIGURE 2-1: Normalized Input Offset Voltage, with GMIN = 1 to 10. 400 -4 0% 0% -500 25% 20% -600 30% 330 Samples TA = +25C VDD = 1.8V and 5.5V RTO Perce entage of Occ currenc ces Percenttage off Occurrence P es 35% -800 2.1 Normalized Input Offset Voltage Drift; GMIN(VOS/TA) (V/C) FIGURE 2-4: Normalized Input Offset Voltage Drift, with GMIN = 100. DS25073A-page 13 MCP6N11 2.5 Normalized d Input Offset Voltage; GMINVOS (mV) 2.0 1.5 1.0 0.5 0.0 -0.5 -40C +25C +85C +125C -1.0 -1.5 Representative Part VCM = VSS GMIN = 1 to 10 RTO -2.0 10 Representative Part VCM = VDD GMIN = 100 RTO 8 6 4 2 0 -2 -4 -40C +25C +85C +125C -6 -8 Power Supply Voltage 25 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.0 Normalized d Input Offset Voltage; GMINVOS (mV) Norm malized d Inputt Offse et Volta age; GMINVOS (mV) 2.5 Power Supply Voltage FIGURE 2-8: Normalized Input Offset Voltage vs. Power Supply Voltage, with VCM = VDD and GMIN = 100. FIGURE 2-5: Normalized Input Offset Voltage vs. Power Supply Voltage, with VCM = 0V and GMIN = 1 to 10. 20 15 10 5 0 -5 -10 -40C 25C 85C 125C -15 -20 Representative Part VCM = VSS GMIN = 100 RTO 1.5 1.0 0.5 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0 4 -0.4 -0.6 -0.8 -1.0 -1.2 -0.5 -1.0 -1.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) FIGURE 2-9: Normalized Input Offset Voltage vs. Output Voltage, with GMIN = 1 to 10. Normalized d Input Offset Voltage; GMINVOS (mV) Representative Part VCM = VDD GMIN = 1 to 10 RTO FIGURE 2-7: Normalized Input Offset Voltage vs. Power Supply Voltage, with VCM = VDD and GMIN = 1 to 10. DS25073A-page 14 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -40C +25C +85C +125C Power Supply Voltage VDD = 5.5V 0.0 Power Supply Voltage FIGURE 2-6: Normalized Input Offset Voltage vs. Power Supply Voltage, with VCM = 0V and GMIN = 100. VDD = 1.8V Representative Part GMIN = 1 to 10 RTO -2.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -25 Normalized d Input Offset Voltage; GMINVOS (mV) 2.0 1.5 0.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0 -10 -2.5 0.5 Normalized d Input Offset Voltage; GMINVOS (mV) Note: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. 6 5 4 3 2 1 0 -1 2 -2 -3 -4 -5 -6 VDD = 1.8V Representative Part GMIN = 100 RTO VDD = 5.5V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) FIGURE 2-10: Normalized Input Offset Voltage vs. Output Voltage, with GMIN = 100. (c) 2011 Microchip Technology Inc. MCP6N11 0.4 VIVH - VDD 1 Wafer Lot 0.3 0.2 0.1 VDD = 1.8V VDD = 5.5V 00 0.0 -0.1 02 -0.2 -0.3 -0.4 VIVL - VSS -0.5 1.0 0.5 0.0 -0.5 +125C +85 +85C +25C -40C -1.0 -1.5 2.0 1.0 0.5 0.0 -0.5 +125C +85C +25C -40C -1.0 -1.5 15 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VDD = 5.5V Representative Part GMIN = 100 RTO 10 5 0 -5 +125C +85C +25C -40C -10 5 0 -5 +125C +85C +25C -40C 2.5 FIGURE 2-13: Normalized Input Offset Voltage vs. Common Mode Voltage, with VDD = 1.8V and GMIN = 100. (c) 2011 Microchip Technology Inc. 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 Input Common Mode Voltage (V) FIGURE 2-15: Normalized Input Offset Voltage vs. Common Mode Voltage, with VDD = 5.5V and GMIN = 100. 110 105 100 CMRR / GMIN, VDD = 1.8V: GMIN = 1, 1 100 GMIN = 2 to 10 CMRR / GMIN, VDD = 5.5V: GMIN = 1 to 10 GMIN = 100 95 90 85 80 75 70 PSRR / GMIN: GMIN = 1 to 10 GMIN = 100 65 60 0.0 0.5 1.0 1.5 2.0 Input Common Mode Voltage (V) 1.0 0.5 -0.5 2.5 VDD = 1.8V Representative Part GMIN = 100 RTO 10 -15 -0.5 15 -15 0.0 0.5 1.0 1.5 2.0 Input Common Mode Voltage (V) FIGURE 2-12: Normalized Input Offset Voltage vs. Common Mode Voltage, with VDD = 1.8V and GMIN = 1 to 10. -10 Input Common Mode Voltage (V) FIGURE 2-14: Normalized Input Offset Voltage vs. Common Mode Voltage, with VDD = 5.5V and GMIN = 1 to 10. Normalized CM N MRR, P PSRR; CMRR / GMIN, PS SRR / GMIN (dB B) -2.0 -0.5 0.0 125 VDD = 1.8V Representative Part GMIN = 1 to 10 RTO 1.5 -0.5 0 25 50 75 100 Ambient Temperature (C) Normalized d Input Offset Voltage; GMINVOS (mV) -25 FIGURE 2-11: Input Common Mode Voltage Headroom vs. Ambient Temperature. Normalized d Input Offset Voltage; GMINVOS (mV) VDD = 5.5V Representative Part GMIN = 1 to 10 RTO 1.5 -2.0 -50 Normalized d Input Offset Voltage; GMINVOS (mV) 2.0 0.0 Input Volttage Ra ange H Headroo om (V V) 0.5 Normalized d Input Offset Voltage; GMINVOS (mV) Note: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. -50 -25 0 25 50 75 100 Ambient Temperature (C) 125 FIGURE 2-16: Normalized CMRR and PSRR vs. Ambient Temperature. DS25073A-page 15 MCP6N11 5 110 105 Normalized Differential Input Errror; GMINVED (mV) Norm malized d DC O Open-Lo oop Ga ain; AOL / GM MIN (dB)) Note: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. VDD = 5.5V VDD = 1.8V 100 95 90 85 80 75 GMIN = 1 to 10 GMIN = 100 70 65 3 2 0 -1 VDD = 5.5V -2 2 -3 -4 -5 -5 -50 -25 0 25 50 75 100 Ambient Temperature (C) 125 FIGURE 2-17: Normalized DC Open-Loop Gain vs. Ambient Temperature. 6.0 5.5 5.0 4.5 40 4.0 3.5 30 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -4 -3 -2 -1 0 1 2 3 4 Normalized Differential Input Voltage; GMINVDM (V) 5 FIGURE 2-20: Normalized Differential Input Error vs. Differential Voltage, with GMIN = 1. 5 Normal N ized Diifferenttial Inp put Errror; GM MINVED (mV) Representative Part VDD = 5.5V GDM = 100 GDM = 1 VIM = -0.20V VIM = VDD + 0.15V Representative Part VED = (VOUT - VREF)/GDM - VDM GMIN = 2 to 100 RTO 4 3 2 1 0 -1 -2 2 -3 -4 4 Non-inverting Input Voltage; VIP (V) FIGURE 2-18: The MCP6N11 Shows No Phase Reversal vs. Common Mode Voltage. 3.8 3.6 5.0 4.5 3.4 3.2 30 3.0 2.8 2.6 2.4 Note: For GMIN = 1, VDMH = minimum of plot value and VDD -50 -25 0 25 50 Axis Title 75 100 125 FIGURE 2-19: Normalized Differential Mode Voltage Range vs. Ambient Temperature. DS25073A-page 16 Representative Part VDD = 5.5V VREF = (VDD - GDMVDM)/2 4.0 3.5 3.0 2.5 2.0 1.5 1.0 2.0 5 5.5 1 Wafer Lot GMINVDMH = -GMINVDML RTO 2.2 -4 -3 -2 -1 0 1 2 3 4 Normalized Differential Input Voltage; GMINVDM (V) FIGURE 2-21: Normalized Differential Input Error vs. Differential Voltage, with GMIN = 2 to 100. Outtput Voltage (V) 4.0 -5 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -5 -1.0 Outtput Vo oltage (V) VDD = 1.8V 1 60 No ormalizzed Diffferentiial Inpu ut Vo oltage Range e; GMINVDMH (V V) Representative Part VED = (VOUT - VREF)/GDM - VDM GMIN = 1 RTO 4 0.5 0.0 GMIN = 1 GMIN = 2 GMIN = 5 GMIN = 10 GMIN = 100 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 Differential Input Voltage (V) 5 6 7 FIGURE 2-22: The MCP6N11 Shows No Phase Reversal vs. Differential Voltage, with VDD = 5.5V. (c) 2011 Microchip Technology Inc. MCP6N11 Note: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. 2.5 1.E-08 10n Input Bias s, Offset Currents (nA) Input Bias s, Offset Currents (A) VDD = 5.5V VCM = VDD 1.E-09 1n IB 1.E-10 100p 1.E-11 10p | IOS | IOS 10 -1.0 -1.5 -2.0 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 125 Common Mode Input Voltage (V) FIGURE 2-26: Input Bias and Offset Currents vs. Common Mode Input Voltage, with TA = +125C. 1000 Output Voltage H Headro oom (m mV) Input Cu urrent Magnitude (A) 0.0 -0.5 1.0 65 85 105 Ambient Temperature (C) 1m 1.E-03 100 1.E-04 10 1.E-05 1 1.E-06 100n 1.E-07 +125C +85C +25C -40 C -40 10n 1.E-08 1n 1 E 09 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) FIGURE 2-24: Input Bias Current vs. Input Voltage (below VSS). 100 VOL - VSS 10 0.1 Outpu ut Head droom (mV) 20 0 IOS -40 -60 8 5 4 2 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 FIGURE 2-25: Input Bias and Offset Currents vs. Common Mode Input Voltage, with TA = +85C. (c) 2011 Microchip Technology Inc. VDD = 1.8V 3 1 Common Mode Input Voltage (V) VDD = 5.5V 6 -80 1.5 10 VDD - VOH 7 -100 1.0 1 Output Current Magnitude (mA) 9 IB 0.5 VDD - VOH 10 40 -20 VDD = 5.5V VDD = 1.8V 1 8V FIGURE 2-27: Output Voltage Headroom vs. Output Current. Representative Part TA = +85C VDD = 5.5V 0.0 Input Bias s, Offset Currents (pA) IB 0.5 0.5 45 FIGURE 2-23: Input Bias and Offset Currents vs. Ambient Temperature, with VDD = +5.5V. 60 1.0 0.0 25 80 1.5 -2.5 1.E-12 1p 100 Representative Part TA = +125C VDD = 5.5V 2.0 VOL - VSS -50 -25 0 25 50 75 Ambient Temperature (C) 100 125 FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. DS25073A-page 17 MCP6N11 Power Supply Voltage (V) 1100 1000 900 800 700 600 500 400 6.0 5.5 5.0 Common Mode Input Voltage (V) FIGURE 2-31: Supply Current vs. Common Mode Input Voltage. 6.5 6.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 300 200 100 0 5.5 +125C +85C +25C 40 -40C 0.0 Supply Current (A) FIGURE 2-29: Output Short Circuit Current vs. Power Supply Voltage. 4.5 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 -50 4.0 -40 3.5 -30 3.0 -20 2.5 -10 VDD = 1.8V 2.0 +125C +85C +25C -40C 0 1.5 10 VDD = 5.5V 1.0 20 -0.5 Supply Cu urrent (A) 30 1100 1000 900 800 700 600 500 400 300 200 100 0 0.5 40 0.0 50 0.0 Output Sho ort Circuit Current (mA) Note: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. Power Supply Voltage (V) FIGURE 2-30: Supply Voltage. DS25073A-page 18 Supply Current vs. Power (c) 2011 Microchip Technology Inc. MCP6N11 Note: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. 100 VDD = 5.5V Normaliized Ga N ain Ban ndwith h Productt; GBW WP/GMINN (MHz)) 90 80 60 50 40 GMIN = 1 GMIN = 2 GMIN = 5 GMIN = 10 GMIN = 100 30 20 10 0 1k 1.E+03 10k 100k 1.E+04 1.E+05 Frequency (Hz) FIGURE 2-32: 0.20 120 110 GMIN = 1 GMIN = 2 GMIN = 5 GMIN = 10 GMIN = 100 GBWP 100 90 PM 0.15 80 0.10 70 0.05 60 50 -50 -25 0 25 50 75 100 Ambient Temperature (C) 125 GMIN = 1 to 10 GDM/GMIN = 10 GMIN = 100 1.E+02 1 E+02 100 10k 100k 1.E+04 1.E+05 Frequency (Hz) 1M 1.E+06 -90 AOL/GMIN 80 60 -120 -150 | AOL/GMIN | -180 20 210 -210 0 -240 GMIN = 1 GMIN = 2 GMIN = 5 GMIN = 10 GMIN = 100 100k 1M 1.E+5 1.E+6 Frequency (Hz) -270 -300 -330 GDM/GMIN = 1 10k 1.E+04 100k 1M 1.E+05 1.E+06 Frequency (Hz) 10M 1.E+07 7 -360 10M 1.E+7 FIGURE 2-34: Normalized Open-Loop Gain vs. Frequency. (c) 2011 Microchip Technology Inc. 1.E+01 1 E+01 10 1k 1.E+03 FIGURE 2-36: Closed-Loop Output Impedance vs. Frequency. PSRR vs. Frequency. -60 -80 10k 1.E+4 0 25 0.25 1.E+03 1k 100 -60 0.30 1.E+04 10k VDD = 5.5V 120 -40 130 0 35 0.35 FIGURE 2-35: Normalized Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. CMRR vs. Frequency. No ormalizzed Op pen-Loo op Gain Pha ase; AO OL/GMIN () No ormalizzed Op pen-Loo op Gain Magnittude; AOL/GMINN (dB) M FIGURE 2-33: -20 140 0.40 1M 1.E+06 PSRR R (dB) 120 110 100 90 80 70 60 50 40 GMIN = 1 30 GMIN = 2 GMIN = 5 20 G = 10 10 G MIN= 100 MIN 0 1k 1.E+03 40 150 0.45 0.00 Clos sed-Loo op Outtput Im mpedan nce () CMRR (dB) 70 0.50 Ph hase Ma argin () Frequency Response 6 Gain Peak king (dB) 2.2 5 GMIN = GDM = 1 =2 =5 = 10 = 100 GMIN = 10 GDM = 20 = 50 4 3 GMIN = 100 GDM = 200 = 500 2 1 0 10p 100p 1n 1.E+1 1.E+2 1.E+3 Normalized Capacitive Load; CL(GMIN/GDM) (F) FIGURE 2-37: Gain Peaking vs. Normalized Capacitive Load. DS25073A-page 19 MCP6N11 Note: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. 2.3 Noise 0.5 RTO 100 100 GMIN = 100 10 10 10 GMIN = 10 GMIN = 5 GMIN = 2 GMIN = 1 1 1 0.3 02 0.2 0.1 00 0.0 -0.1 -0.2 -0.3 -0.5 0 2.0 12 15 1.5 GMIN = 100 GMIN = 10 GMIN = 5 GMIN = 2 GMIN = 1 8 6 Norma alized Input N Noise; GMINeni(tt) (mV)) 14 10 VDD = 1.8V VDD = 5.5V 4 2 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 10 15 20 Time (min) 25 30 35 Representative Part GMIN = 100 RTO Analog NPBW = 0.1 Hz Sample p Rate = 4 SPS 1.0 0.5 00 0.0 -0.5 -1.0 -1.5 f = 100 Hz RTO 0 5 FIGURE 2-41: Normalized Input Noise Voltage vs. Time, with GMIN = 1 to 10. FIGURE 2-38: Normalized Input Noise Voltage Density vs. Frequency. -0.5 Analog NPBW = 0.1 Hz Sample p Rate = 4 SPS -0.4 100n 0.1 0.1 1.E+0 1 1.E+1 10 1.E+2 100 1.E+3 1k 1.E+4 10k 1.E+5 100k 1.E+6 1M 1.E-1 Frequency (Hz) Norm malized Input Noise Voltage De ensity;; GMINeni (V/ Hz) Representative Part GMIN = 1 to 10 RTO 0.4 Norma alized Input N Noise; GMINeni(tt) (mV)) Norrmalize ed Inpu ut Noise e Volta age Densitty; GMINeni (V//Hz) 1000 1m Common Mode Input Voltage (V) FIGURE 2-39: Normalized Input Noise Voltage Density vs. Input Common Mode Voltage, with f = 100 Hz. -2.0 0 5 10 15 20 Time (min) 25 30 35 FIGURE 2-42: Normalized Input Noise Voltage vs. Time, with GMIN = 100. 35 3.5 3.0 GMIN = 100 GMIN = 10 GMIN = 5 GMIN = 2 GMIN = 1 2.5 20 2.0 1.5 VDD = 1.8V VDD = 5.5V 1.0 05 0.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.0 0.5 0.0 1.5 f = 10 kHz RTO 0.0 -0.5 Norm malized Input Noise Voltage De ensity;; GMINeni (V/ Hz) 4.0 Common Mode Input Voltage (V) FIGURE 2-40: Normalized Input Noise Voltage Density vs. Input Common Mode Voltage, with f = 10 kHz. DS25073A-page 20 (c) 2011 Microchip Technology Inc. MCP6N11 Note: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. Time Response GMIN = 1 to 10 GMIN = 100 0 2 4 FIGURE 2-43: Response. 6 8 10 12 Time (s) 16 18 4.5 4.0 3.5 3.0 GMIN = 1 to 10 GMIN = 100 2.5 VDD = 1.8V 1 GMIN = 1 to 10 GMIN = 100 0 10k 1.E+4 2.0 1.5 1.0 0.5 1000 VDD = 5.5V 100 VDD = 1.8V 10 GMIN = 100 GMIN = 10 GMIN = 1 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Time (s) FIGURE 2-44: Response. 1M 1.E+6 GDMVDM = 1V 1 0.0 Large Signal Step 10 Normalized Gain; GDM/GMIN 100 FIGURE 2-47: Common Mode Input Overdrive Recovery Time vs. Normalized Gain. 10 Inp put Diffe erentia al Mode e Volta age Ov verdriv ve Reco overy; tIRD (s s) 1000 9 8 Sle ew Ratte (V/s s) 100k 1.E+5 Frequency (Hz) FIGURE 2-46: Maximum Output Voltage Swing vs. Frequency. VDD = 5.5V GDM = GMIN RF + RG = 10 k 5.0 VDD = 5.5V 20 Small Signal Step 5.5 Output O Voltage V e (10 m mV/div)) 14 10 Max ximum Output Voltage Swing (VP-P) O Output Voltage (10 m mV/div)) VDD = 5.5V GDM = GMIN RF + RG = 10 k Inp put Co ommon n Mode Voltag ge Ov verdriv ve Reco overy; tIRC (s s) 2.4 7 6 5 GMIN = 1 tto 10 GMIN = 100 4 VDD = 5.5V 5 5V VDD = 1.8V 3 2 1 VDD = 5.5V 100 VDD = 1.8V 10 GMIN = 100 GMIN = 10 GMIN = 1 1 0 -50 -25 FIGURE 2-45: Temperature. 0 25 50 75 Ambient Temperature (C) 100 Slew Rate vs. Ambient (c) 2011 Microchip Technology Inc. 125 1 10 Normalized Gain; GDM/GMIN 100 FIGURE 2-48: Differential Input Overdrive Recovery Time vs. Normalized Gain. DS25073A-page 21 MCP6N11 Note: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. 4 GDM = 2GMIN VREF = 0.75VDD VDD = 5.5V 100 GMIN = 1 VDD = 1.8V GMIN = 10 10 GMIN = 100 1 In nput, O Output Voltag ges (V) Output Overdrive Recovery; tOR (s) 1000 VDD = 5.5V VIP 3 2 VOUT, GMIN = 1 VOUT, GMIN = 100 1 0 -1 -2 -3 VIM -4 1 10 Normalized Gain; GDM/GMIN 100 FIGURE 2-49: Output Overdrive Recovery Time vs. Normalized Gain. 0 10 20 30 40 50 60 Time (s) 70 80 90 100 FIGURE 2-51: The MCP6N11 Shows No Phase Reversal vs. Differential Input Overdrive, with VDD = 5.5V. Inp put Common Mode,, Outpu ut Voltage V es (V) 6 VDD = 5.5V GDMVDM = +0.1V 0.1V f = 10 kHz VCM 5 4 3 2 VOUT, GMIN = 1 VOUT, GMIN = 100 1 0 -1 0 10 20 30 40 50 60 Time (s) 70 80 90 100 FIGURE 2-50: The MCP6N11 Shows No Phase Reversal vs. Common Mode Input Overdrive, with VDD = 5.5V. DS25073A-page 22 (c) 2011 Microchip Technology Inc. MCP6N11 Note: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. Enable/Calibration and POR Responses 30 VDD = 1.8V VL = 0V 1.8 1.6 1.4 Calibration Starts 1.2 1.0 INA turns off INA turns on 0.8 0.6 0.4 EN/CAL 0.2 VOUT 0.0 VDD = 5.5V 20 VDD = 1.8V 15 10 5 0 -0.2 0 10 20 30 40 50 60 Time (ms) 70 80 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 EN/CAL INA turns off INA turns on VOUT -25 0 25 50 75 Ambient Temperature (C) 100 125 FIGURE 2-55: EN/CAL Turn On Time vs. Ambient Temperature. Powe er Supply, Ou utput V Voltage e (V) EN/CAL, Output Voltage (V) VDD = 5.5V VL = 0V Calibration Starts -50 90 100 FIGURE 2-52: EN/CAL and Output Voltage vs. Time, with VDD = 1.8V. 1.8 VL = 0V 1.6 1.4 12 1.2 1.0 On 08 0.8 0.6 VDD VOUT 0.4 0.2 Off 0.0 Off Calibrating -0.2 0 10 20 30 40 50 60 Time (ms) 70 80 90 100 0.60 0.55 0.50 0.45 0.40 0.35 0 30 0.30 0.25 0.20 0 20 0.15 0.10 0.05 0.00 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Time (s) FIGURE 2-56: Power Supply On and Off and Output Voltage vs. Time. POR Trip Voltages (V) FIGURE 2-53: EN/CAL and Output Voltage vs. Time, with VDD = 5.5V EN/CA AL Hys steresis (V) 25 VDD = 5.5V VDD = 1.8V 1.7 0.18 1.6 0.16 1.5 0.14 1.4 0.12 VPRH - VPRL 1.3 0.10 1.2 0.08 VPRH 11 1.1 0 06 0.06 1.0 0.04 0.9 0.02 VPRL 0.8 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125 FIGURE 2-54: EN/CAL Hysteresis vs. Ambient Temperature. (c) 2011 Microchip Technology Inc. POR R Hysteresis (V) EN/CAL, Output Voltage (V) 2.0 EN//CAL Turn On n Time;; tON (m ms) 2.5 0.00 -50 -25 0 25 50 75 100 Ambient Temperature (C) 125 FIGURE 2-57: POR Trip Voltages and Hysteresis vs. Temperature. DS25073A-page 23 MCP6N11 Note: Unless otherwise indicated, TA = +25C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. EN/CAL = 0V 1.E-07 100n Ou utput L Leakag ge Currrent (A A) Negative P Power S Supply y Curre ent; ISS ( A) 0.0 EN/CAL = 0V VDD = 5.5V 1.E-08 10n -0.5 1.E-09 1n -1.0 +125C +85C 1.E-10 100p -1.5 +125C +85C +85 C +25C -40C -2.0 -2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V) FIGURE 2-58: Quiescent Current in Shutdown vs. Power Supply Voltage. DS25073A-page 24 1.E-11 10p +25C 25C 1.E-12 1p 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Output Voltage (V) FIGURE 2-59: Output Voltage. Output Leakage Current vs. (c) 2011 Microchip Technology Inc. MCP6N11 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6N11 SOIC TDFN Symbol Description 1 1 VFG Feedback Input 2 2 VIM Inverting Input 3 3 VIP Non-inverting Input 4 4 VSS Negative Power Supply 5 5 VREF Reference Input 6 6 VOUT Output 7 7 VDD Positive Power Supply 8 8 EN/CAL -- 9 EP 3.1 Enable/VOS Calibrate Digital Input Exposed Thermal Pad (EP); must be connected to VSS Analog Signal Inputs The non-inverting and inverting inputs (VIP, and VIM) are high-impedance CMOS inputs with low bias currents. 3.2 Analog Feedback Input The analog feedback input (VFG) is the inverting input of the second input stage. The external feedback components (RF and RG) are connected to this pin. It is a high-impedance CMOS input with low bias current. 3.3 Analog Reference Input The analog reference input (VREF) is the non-inverting input of the second input stage; it shifts VOUT to its desired range. The external gain resistor (RG) is connected to this pin. It is a high-impedance CMOS input with low bias current. 3.4 Analog Output The analog output (VOUT) is a low-impedance voltage output. It represents the differential input voltage (VDM = VIP - VIM), with gain GDM and is shifted by VREF. The external feedback resistor (RF) is connected to this pin. 3.5 Power Supply Pins The positive power supply (VDD) is 1.8V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply; VDD will need bypass capacitors. 3.6 Digital Enable and VOS Calibration Input This input (EN/CAL) is a CMOS, Schmitt-triggered input that controls the active, low power and VOS calibration modes of operation. When this pin goes low, the part is placed into a low power mode and the output is high-Z. When this pin goes high, the amplifier's input offset voltage is corrected by the calibration circuitry, then the output is re-connected to the VOUT pin, which becomes low impedance, and the part resumes normal operation. 3.7 Exposed Thermal Pad (EP) There is an internal connection between the Exposed Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit Board (PCB). This pad can be connected to a PCB ground plane to provide a larger heat sink. This improves the package thermal resistance (JA). (c) 2011 Microchip Technology Inc. DS25073A-page 25 MCP6N11 NOTES: DS25073A-page 26 (c) 2011 Microchip Technology Inc. MCP6N11 4.0 APPLICATIONS The MCP6N11 instrumentation amplifier (INA) is manufactured using Microchip's state of the art CMOS process. It is low cost, low power and high speed, making it ideal for battery-powered applications. 4.1 Basic Performance 4.1.1 STANDARD CIRCUIT Figure 4-1 shows the standard circuit configuration for these INAs. When the inputs and output are in their specified ranges, the output voltage is approximately: The input offset voltage (VOS) is corrected by the voltage VTR. Each time a VOS Calibration event occurs, VTR is updated to the best value (at that moment). These events are triggered by either powering up (monitored by the POR) or by toggling the EN/CAL pin high. The current out of GM3 (I3) is constant and very small (assumed to be zero in the following discussion). The input signal is applied to GM1. Equation 4-2 shows the relationships between the input voltages (VIP and VIM) and the common mode and differential voltages (VCM and VDM). EQUATION 4-2: V IP = VCM + V DM 2 EQUATION 4-1: VIM = V CM - VDM 2 VOUT VREF + GDMVDM VCM = ( VIP + V IM ) 2 Where: V DM = V IP - V IM GDM = 1 + RF / RG VDD The negative feedback loop includes GM2, RM4, RF and RG. These blocks set the DC open-loop gain (AOL) and the nominal differential gain (GDM): U1 MCP6N11 VIP VOUT VIM RF VFG A OL = G M2 R M4 G DM = 1 + R F R G RG VREF FIGURE 4-1: Standard Circuit. For normal operation, keep: * VIP, VIM, VREF and VFG between VIVL and VIVH * VIP - VIM (i.e., VDM) between VDML and VDMH * VOUT between VOL and VOH 4.1.2 ARCHITECTURE Figure 4-2 shows the block diagram for these INAs. VOUT VOUT RF RG VREF VIP VIM VDD VSS RM4 I4 VFG VREF GM2 I2 I1 VIP VIM GM1 POR EQUATION 4-3: AOL is very high, so I4 is very small and I1 + I2 0. This makes the differential inputs to GM1 and GM2 equal in magnitude and opposite in polarity. Ideally, this gives: EQUATION 4-4: ( VFG - V REF ) = V DM V OUT = V DM G DM + V REF For an ideal part, changing VCM, VSS or VDD produces no change in VOUT. VREF shifts VOUT as needed. The different GMIN options change GM1, GM2 and the internal compensation capacitor. This results in the performance trade-offs shown in Table 1. I3 GM3 VTR Low Power VOS Calibration EN/CAL FIGURE 4-2: MCP6N11 Block Diagram. (c) 2011 Microchip Technology Inc. DS25073A-page 27 MCP6N11 4.1.3 DC ERRORS EQUATION 4-6: Section 1.5 "Explanation of DC Error Specs" defines some of the DC error specifications. These errors are internal to the INA, and can be summarized as follows: EQUATION 4-5: VOUT = V REF + GDM ( 1 + g E ) ( V DM + V ED ) I OS V IP = - I BP R IP = - I B - ------- R 2 IP I OS V IM = - IBM R IM = - I B + ------- R 2 IM V IP + V IM V CM = -------------------------------- + G DM ( 1 + g E ) ( VE + V E ) Where: VDD - V SS VCM V REF V E = VOS + --------------------------------- + ----------------- + ----------------PSRR CMRR CMRR V OUT VOS + ----------------- + T A ------------A OL TA V ED INLDM ( VDMH - VDML ) V E INLCM ( VIVH - V IVL ) CMRR is in units of V/V The best design results when RIP and RIM are equal and small: PSRR, CMRR and AOL are in units of V/V TA is in units of C The non-linearity specs (INLCM and INLDM) describe errors that are non-linear functions of VCM and VDM, respectively. They give the maximum excursion from linear response over the entire common mode and differential ranges. The input bias current and offset current specs (IB and IOS), together with a circuit's external input resistances, give an additional DC error. Figure 4-3 shows the resistors that set the DC bias point. VIP RIP VDD U1 MCP6N11 IBM IBF RIM RF VFG RR IBR RG VREF FIGURE 4-3: EQUATION 4-7: V OUT G DM V DM G DM ( 2I B RTOL - I OS )R IP Where: RIP = RIM RTOL = tolerance of RIP and RIM The resistors at the feedback input (RR, RF and RG) and its input bias currents (IBR and IBF) give the following changes in the INA's bias voltages: EQUATION 4-8: VOUT VIM V OUT I OS = I B ( - R IP + R IM ) - -------- ( RIP + RIM ) 2 V CM = G DM V DM + ----------------- CMRR Where: Where: IBP V DM 2 R - I OS - R IP + R IM IP + R IM = - I B ------------------------- + ----------- ---------------------------- 2 2 2 = V IP - VIM DC Bias Resistors. The resistors at the main input (RIP and RIM) and its input bias currents (IBP and IBM) give the following changes in the INA's bias voltages: I OS2 V REF = - I BR R R = - IB2 - ---------- R R 2 due to high AOL VFG V REF, IOS2 V OUT I B2 ( R F - G DM R R ) + ---------- ( RF + G DM R R ) 2 Where: IB2 meets the IB spec, but is not equal to IB IOS2 meets the IOS spec, but is not equal to IOS The best design results when GDMRR and RF are equal and small: EQUATION 4-9: V OUT ( ( 2I B2 RTOL + I OS2 ) )RF Where: GDMRR = RF RTOL = tolerance of RR, RF and RG DS25073A-page 28 (c) 2011 Microchip Technology Inc. MCP6N11 4.1.4 AC PERFORMANCE The bandwidth of these amplifiers depends on GDM and GMIN: EQUATION 4-10: f GBWP f BW --------------G DM ( 0.50 MHz ) ( G MIN G DM ), ( 0.35 MHz ) ( G MIN G DM ), Where: GMIN = 1, ..., 10 GMIN = 100 fBW = -3 dB bandwidth fGBWP = Gain bandwidth product The bandwidth at the maximum output swing is called the Full Power Bandwidth (fFPBW). It is limited by the Slew Rate (SR) for many amplifiers, but is close to fBW for these parts: EQUATION 4-11: SR f FPBW --------- VO fBW , Where: Functional Blocks 4.2.1 RAIL-TO-RAIL INPUTS Each input stage uses one PMOS differential pair at the input. The output of each differential pair is processed using current mode circuitry. The inputs show no crossover distortion vs. common mode voltage. With this topology, the inputs (VIP and VIM) operate normally down to VSS - 0.2V and up to VDD + 0.15V at room temperature (see Figure 2-11). The input offset voltage (VOS) is measured at VCM = VSS - 0.2V and VDD + 0.15V (at +25C), to ensure proper operation. 4.2.1.1 for these parts VOH - VOL CMRR is constant from DC to about 1 kHz. NOISE PERFORMANCE As shown in Figures 2-41 and 2-42, the 1/f noise causes an apparent wander in the DC output voltage. Changing the measurement time or bandwidth has little effect on this noise. We recommend re-calibrating VOS periodically, to reduce 1/f noise wander. For example, VOS could be re-calibrated at least once every 15 minutes; more often when temperature or VDD change significantly. Phase Reversal The input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figures 2-18 and 2-50 show an input voltage exceeding both supplies with no phase inversion. The input devices also do not exhibit phase inversion when the differential input voltage exceeds its limits; see Figures 2-22 and 2-51. 4.2.1.2 VO = Maximum output voltage swing 4.1.5 4.2 Input Voltage Limits In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the input pins (see Section 1.1 "Absolute Maximum Ratings "). This requirement is independent of the current limits discussed later on. The ESD protection on the inputs can be depicted as shown in Figure 4-4. This structure was chosen to protect the input transistors against many (but not all) overvoltage conditions, and to minimize input bias current (IB). VDD Bond Pad VIP Bond Pad Input Stage of INA Input Bond V IM Pad VSS Bond Pad FIGURE 4-4: Structures. (c) 2011 Microchip Technology Inc. Simplified Analog Input ESD DS25073A-page 29 MCP6N11 VDD U1 D1 MCP6N11 V1 D2 V2 FIGURE 4-5: Protecting the Analog Inputs Against High Voltages. 4.2.1.3 Input Current Limits In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents into the input pins (see Section 1.1 "Absolute Maximum Ratings "). This requirement is independent of the voltage limits previously discussed. 4.2.1.4 Input Voltage Ranges Figure 4-7 shows possible input voltage values (VSS = 0V). Lines with a slope of +1 have constant VDM (e.g., the VDM = 0 line). Lines with a slope of -1 have constant VCM (e.g., the VCM = VDD/2 line). For normal operation, VIP and VIM must be kept within the region surrounded by the thick blue lines. The horizontal and vertical blue lines show the limits on the individual inputs. The blue lines with a slope of +1 show the limits on VDM; the larger GMIN is, the closer they are to the VDM = 0 line. The input voltage range specs (VIVL and VIVH) change with the supply voltages (VSS and VDD, respectively). The differential input range specs (VDML and VDMH) change with minimum gain (GMIN). Temperature also affects these specs. To take full advantage of VDML and VDMH, set VREF (see Figure 1-6 and Figure 1-7) so that the output (VOUT) is centered between the supplies (VSS and VDD). VIP VIVH VDD DM = V Figure 4-6 shows one approach to protecting these inputs. The resistors R1 and R2 limit the possible current in or out of the input pins (and into D1 and D2). The diode currents will dump onto VDD. A significant amount of current can flow out of the inputs (through the ESD diodes) when the common mode voltage (VCM) is below ground (VSS); see Figure 2-25. H In some applications, it may be necessary to prevent excessive voltages from reaching the op amp inputs. Figure 4-5 shows one approach to protecting these inputs. D1 and D2 may be small signal silicon diodes, Schottky diodes for lower clamping voltages or diodeconnected FETs for low leakage. It is also possible to connect the diodes to the left of the resistor R1 and R2. In this case, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIP and VIM) should be very small. D M The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow overvoltage (beyond VDD) events. Very fast ESD events (that meet the spec) are limited so that damage does not occur. VC V VDD M 0 = V V D2 DM D H M = /2 D VD MCP6N11 V1 R1 = U1 D1 VIM R2 0 VIVL FIGURE 4-7: VIVH VDD 0 VIVL VSS - min(V1, V2) min(R1, R2) > 2 mA max(V1, V2) - VDD min(R1, R2) > 2 mA V D M V2 Input Voltage Ranges. FIGURE 4-6: Protecting the Analog Inputs Against High Currents. DS25073A-page 30 (c) 2011 Microchip Technology Inc. MCP6N11 4.2.2 ENABLE/VOS CALIBRATION (EN/CAL) These parts have a Normal mode, a Low Power mode and a VOS Calibration mode. When the EN/CAL pin is high and the internal POR (with delay) indicates that power is good, the part operates in its Normal mode. When the EN/CAL pin is low, the part operates in its Low Power mode. The quiescent current (at VSS) drops to -2.5 A (typical), the amplifier output is put into a high-impedance state. Signals at the input pins can feed through to the output pin. When the EN/CAL pin goes high and the internal POR (with delay) indicates that power is good, the amplifier internally corrects its input offset voltage (VOS) with the internal common mode voltage at mid-supply (VDD/2) and the output tri-stated (after tOFF). Once VOS Calibration is completed, the amplifier is enabled and normal operation resumes. The EN/CAL pin does not operate normally when left floating. Either drive it with a logic output, or tie it high so that the part is always on. 4.2.3 POR WITH DELAY The internal POR makes sure that the input offset voltage (VOS) is calibrated whenever the supply voltage goes from low voltage (< VPRL) to high voltage (> VPRH). This prevents corruption of the VOS trim registers after a low-power event. After the POR goes high, the internal circuitry adds a fixed delay (tPLH), before telling the VOS Calibration circuitry (see Figure 4-2) to start. If the EN/CAL pin is toggled during this time, the fixed delay is restarted (takes an additional time tPLH). 4.2.4 Applications Tips 4.3.1 MINIMUM STABLE GAIN There are different options for different Minimum Stable Gains (1, 2, 5, 10 and 100 V/V; see Table 1-1). The differential gain (GDM) needs to be greater than or equal to GMIN in order to maintain stability. Picking a part with higher GMIN has the advantages of lower Input Noise Voltage Density (eni), lower Input Offset Voltage (VOS) and increased Gain Bandwidth Product (GBWP); see Table 1. The Differential Input Voltage Range (VDMR) is lower for higher GMIN, but the output voltage range would limit VDMR anyway, when GDM 2. 4.3.2 CAPACITIVE LOADS Driving large capacitive loads can cause stability problems for amplifiers. As the load capacitance increases, the feedback loop's phase margin decreases, and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. Lower gains (GDM) exhibit greater sensitivity to capacitive loads. When driving large capacitive loads with these instrumentation amps (e.g., > 100 pF), a small series resistor at the output (RISO in Figure 4-8) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. V1 VDD U1 MCP6N11 RAIL-TO-RAIL OUTPUT The Minimum Output Voltage (VOL) and Maximum Output Voltage (VOH) specs describe the widest output swing that can be achieved under the specified load conditions. RISO VOUT PARITY DETECTOR A parity error detector monitors the memory contents for any corruption. In the rare event that a parity error is detected (e.g., corruption from an alpha particle), a POR event is automatically triggered. This will cause the input offset voltage to be re-corrected, and the op amp will not return to normal operation for a period of time (the POR turn on time, tPLH). 4.2.5 4.3 V2 VFG RF CL RG VREF FIGURE 4-8: Output Resistor, RISO stabilizes large capacitive loads. Figure 4-9 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL GMIN/GDM), where GDM is the circuit's differential gain (1 + RF / RG) and GMIN is the minimum stable gain. The output can also be limited when VIP or VIM exceeds VIVL or VIVH, or when VDM exceeds VDML or VDMH. (c) 2011 Microchip Technology Inc. DS25073A-page 31 MCP6N11 In this data sheet, RF + RG = 10 k for most gains (0 for GDM = 1); see Table 1-6. This choice gives good Phase Margin. In general, RF (Figure 4-10) needs to meet the following limits to maintain stability: Reco ommended RISO () 1.E+04 10k EQUATION 4-12: 1.E+03 1k For GDM = 1: RF = 0 GMIN = 1 to 10 GMIN = 100 1.E+02 100 100p 1.E-10 1n 10n 100n 1.E-09 1.E-08 1.E-07 Normalized Load Capacitance; CL GMIN/GDM (F) 1 1.E-06 2 FIGURE 4-9: Recommended RISO Values for Capacitive Loads. After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot on the bench. Modify RISO's value until the response is reasonable. 4.3.3 Figure 4-10 shows a simple gain circuit with the INA's input capacitances at the feedback inputs (VREF and VFG). These capacitances interact with RG and RF to modify the gain at high frequencies. The equivalent capacitance acting in parallel to RG is CG = CDM + CCM plus any board capacitance in parallel to RG. CG will cause an increase in GDM at high frequencies, which reduces the phase margin of the feedback loop (i.e., reduce the feedback loop's stability). V1 G DM R F < -----------------------------2 f GBWP C G Where: 0.25 GDM GMIN fGBWP = Gain Bandwidth Product CG = CDM + CCM + (PCB stray capacitance) GAIN RESISTORS VDD For GDM > 1: U1 4.3.4 SUPPLY BYPASS With these INAs, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good high frequency performance. Surface mount, multilayer ceramic capacitors, or their equivalent, should be used. These INAs require a bulk capacitor (i.e., 1.0 F or larger) within 100 mm, to provide large, slow currents. This bulk capacitor can be shared with other nearby analog parts as long as crosstalk through the supplies does not prove to be a problem. MCP6N11 VOUT V2 RF VFG CCM CDM CCM RG VREF FIGURE 4-10: Simple Gain Circuit with Parasitic Capacitances. DS25073A-page 32 (c) 2011 Microchip Technology Inc. MCP6N11 4.4 4.4.1 Typical Applications 4.4.3 HIGH INPUT IMPEDANCE DIFFERENCE AMPLIFIER Figure 4-11 shows the MCP6N11 used as a difference amplifier. The inputs are high impedance and give good CMRR performance. VDD U1 Figure 4-13 shows the MCP6N11 INA used as to detect and amplify the high side current in a battery powered design. The INA gain is set at 21 V/V, so VOUT changes 210 mV for every 1 mA of IDD current. The best GMIN option to pick would be a gain of 10 (MCP6N11-010). 10 VDD MCP6N11 VIP HIGH SIDE CURRENT DETECTOR IDD U1 MCP6N11 VOUT VIM RF VFG RF 200 k VFG RG 4.4.2 VREF Difference Amplifier. DIFFERENCE AMPLIFIER FOR VERY LARGE COMMON MODE SIGNALS Figure 4-12 shows the MCP6N11 INA used as a difference amplifier for signals with a very large common mode component. The input resistor dividers (R1 and R2) ensure that the voltages at the INA's inputs are within their range of normal operation. The capacitors C1, with the parasitic capacitances C2 (the resistors' parasitic capacitance plus the INA's input common mode capacitance, CCM), set the same division ratio, so that high-frequency signals (e.g., a step in voltage) have the same gain. Select the INA gain to compensate for R1 and R2's attenuation. Select R1 and R2's tolerances for good CMRR. V1 = (10 ) (VOUT - VREF) (10 ) (21.0 V/V) FIGURE 4-13: 4.4.4 High Side Current Detector. WHEATSTONE BRIDGE Figure 4-14 shows the MCP6N11 single instrumentation amp used to condition the signal from a Wheatstone bridge (e.g., strain gage). The overall INA gain is set at 201 V/V. The best GMIN option to pick, for this gain, is 100 V/V (MCP6N11-100). VDD R2 RW1 RW2 C1 C2 RW2 RW1 VDD U 1 C2 R1 R2 MCP6N11 VOUT RF 200 k RG 1 k VOUT C1 U1 VFG MCP6N11 V2 (VBAT - VDD) IDD = R1 VFG VOUT RG 10 k VREF FIGURE 4-11: VBAT +1.8V to +5.5V RF VREF FIGURE 4-14: Amplifier. RG Wheatstone Bridge VREF FIGURE 4-12: Difference Amplifier with Very Large Common Mode Component. (c) 2011 Microchip Technology Inc. DS25073A-page 33 MCP6N11 NOTES: DS25073A-page 34 (c) 2011 Microchip Technology Inc. MCP6N11 5.0 DESIGN AIDS Microchip provides the basic design aids needed for the MCP6N11 instrumentation amplifiers. 5.1 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/maps, the MAPS is an overall selection tool for Microchip's product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool, a customer can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase and Sampling of Microchip parts. 5.2 Analog Demonstration Board Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help customers achieve faster time to market. For a complete listing of these boards and their corresponding user's guides and technical information, visit the Microchip web site at www.microchip.com/analog tools. 5.3 Application Notes The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. * AN884: "Driving Capacitive Loads With Op Amps", DS00884 * AN990: "Analog Sensor Conditioning Circuits - An Overview", DS00990 * AN1228: "Op Amp Precision Design: Random Noise", DS01228 Some of these application notes, and others, are listed in the design guide: * "Signal Chain Design Guide", DS21825 (c) 2011 Microchip Technology Inc. DS25073A-page 35 MCP6N11 NOTES: DS25073A-page 36 (c) 2011 Microchip Technology Inc. MCP6N11 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead SOIC (150 mil) (MCP6N11) Example 6N11001E e3 1121 SN^^ 256 NNN Note: 8-Lead TDFN (2x3) (MCP6N11) Example Device Legend: XX...X Y YY WW NNN e3 * Note: Code MCP6N11-001 AAQ MCP6N11-002 AAR MCP6N11-005 AAS MCP6N11-010 AAT MCP6N11-100 AAU Note: The example is for a MCP6N11-001 part. AAQ 121 25 Applies to 8-Lead 2x3 TDFN Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2011 Microchip Technology Inc. DS25073A-page 37 MCP6N11 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25073A-page 38 (c) 2011 Microchip Technology Inc. MCP6N11 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2011 Microchip Technology Inc. DS25073A-page 39 MCP6N11 & !"#$% ! "# $% &"' "" ($ ) % *++&&&! !+ $ DS25073A-page 40 (c) 2011 Microchip Technology Inc. MCP6N11 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2011 Microchip Technology Inc. DS25073A-page 41 MCP6N11 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25073A-page 42 (c) 2011 Microchip Technology Inc. MCP6N11 & ' ( )*+,--./ !"0'(% ! "# $% &"' "" ($ ) % *++&&&! !+ $ (c) 2011 Microchip Technology Inc. DS25073A-page 43 MCP6N11 NOTES: DS25073A-page 44 (c) 2011 Microchip Technology Inc. MCP6N11 APPENDIX A: REVISION HISTORY Revision A (October 2011) * Original Release of this Document. (c) 2011 Microchip Technology Inc. DS25073A-page 45 MCP6N11 NOTES: DS25073A-page 46 (c) 2011 Microchip Technology Inc. MCP6N11 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X X /XX Device Gain Option Temperature Range Package Device: MCP6N11 Single Instrumentation Amplifier MCP6N11T Single Instrumentation Amplifier (Tape and Reel) Gain Option: 001 002 005 010 100 Temperature Range: E Package: MNY SN = = = = = Examples: a) b) MCP6N11T-001E/MNY: Tape and Reel, Minimum gain = 1, Extended temperature, 8LD 2x3 TDFN. MCP6N11-002E/SN: Minimum gain = 2, Extended temperature, 8LD SOIC. Minimum gain of 1 V/V Minimum gain of 2 V/V Minimum gain of 5 V/V Minimum gain of 10 V/V Minimum gain of 100 V/V = -40C to +125C = 2x3 TDFN, 8-lead * = Plastic SOIC (150mil Body), 8-lead * Y = nickel palladium gold manufacturing designator. Only available on the TDFN package. (c) 2011 Microchip Technology Inc. DS25073A-page 47 MCP6N11 NOTES: DS25073A-page 48 (c) 2011 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-685-3 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2011 Microchip Technology Inc. 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