© Semiconductor Components Industries, LLC, 2014
December, 2014 − Rev. 1 1Publication Order Number:
NCV7349/D
NCV7349
High Speed Low Power CAN
Transceiver
Description
The NCV7349 CAN transceiver is the interface between
a controller area network (CAN) protocol controller and the physical
bus. The transceiver provides differential transmit capability to the bus
and differential receive capability to the CAN controller.
The NCV7349 is a new addition to the CAN high−speed transceiver
family complementing NCV734x CAN family and previous generations
of CAN transceivers such as AMIS42665, AMIS3066x, etc.
Due to the wide common−mode voltage range of the receiver inputs
and other design features, the NCV7349 is able to reach outstanding
levels of electromagnetic susceptibility (EMS). Similarly, very low
electromagnetic emission (EME) is achieved by the excellent
matching of the output signals.
Features
•Compatible with the ISO 11898−5 Standard
•High Speed (up to 1 Mbps)
•VIO Pin on NCV7349−3 Version Allowing Direct Interfacing with
3 V to 5 V Microcontrollers
•Very Low Current Standby Mode with Wake−up via the Bus
•Low Electromagnetic Emission (EME) and Extremely High
Electromagnetic Immunity
•Very Low EME without Common−mode (CM) Choke
•No Disturbance of the Bus Lines with an Un−powered Node
•Transmit Data (TxD) Dominant Time−out Function
•Under All Supply Conditions the Chip Behaves Predictably
•Very High ESD Robustness of Bus Pins, >10 kV System ESD Pulses
•Thermal Protection
•Bus Pins Short Circuit Proof to Supply Voltage and Ground
•Bus Pins Protected Against Transients in an Automotive
•These are Pb−Free Devices
Quality
•NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
Typical Applications
•Automotive
•Industrial Networks
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NCV7349D10R2G
(Top View)
5
6
7
8
1
2
3
4
TxD
RxD
STB
GND
CANL
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
VCC
NC
CANH
PIN ASSIGNMENT
MARKING
DIAGRAM
1
8
SOIC−8
CASE 751AZ
NV7349−x = Specific Device Code
x = 0 or 3
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
NV7349−x
ALYW G
G
1
8
NV7349−0
ALYWG
G
NCV7349D13R2G
(Top View)
5
6
7
8
1
2
3
4
TxD
RxD
STB
GND
CANL
VCC
VIO
CANH
NV7349−3
ALYWG
G
(Note: Microdot may be in either location)
NCV7349
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Table 1. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES
Symbol Parameter Conditions Min Max Unit
VCC Power supply voltage (Note 1) 4.75
(4.5) 5.25
(5.5) V
VUV Undervoltage detection voltage on pin Vcc 2 4 V
VCANH DC voltage at pin CANH 0 < VCC < 5.5 V; no time limit −50 +50 V
VCANL DC voltage at pin CANL 0 < VCC < 5.5 V; no time limit −50 +50 V
VCANH,Lmax DC voltage at pin CANH and CANL during load
dump condition 0 < VCC < 5.5 V, less than one second − +58 V
VESD Electrostatic discharge voltage IEC 61000−4−2 at pins CANH and CANL −15 15 kV
VO(dif)(bus_dom) Differential bus output voltage in dominant state 45 W < RLT < 65 W1.5 3 V
CM−range Input common−mode range for comparator Guaranteed differential receiver thresh-
old and leakage current −35 +35 V
Cload Load capacitance on IC outputs − 15 pF
tpd0 Propagation delay (NCV7349−0 version) See Figure 7 − 245 ns
tpd3 Propagation delay (NCV7349−3 version) See Figure 7 − 250 ns
TJJunction temperature −40 150 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. In the range of 4.5 V to 4.75 V and from 5.25 V to 5.5 V the chip is fully functional; some parameters may be outside of the specification.
BLOCK DIAGRAM
Figure 1. Block Diagram
Mode &
Wake−up
control
Wake−up
Filter
NCV7349
STB
GND
RxD
2
3
7
6
COMP
COMP
5
Timer
TxD 1
Driver control
Thermal
shutdown
8
4
CANH
CANL
VIO
VIO
VIO (*) VCC
*On NCV7349−0 version pin 5 is not connected. VIO supply is provided by VCC.
NCV7349
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TYPICAL APPLICATION
Micro−
controller
NC
VBAT
GND
2
5
CANH
CANL
3
6
7
CAN
BUS
5 V − reg
GND
STB
RxD
TxD 1
4
8
NCV7349−0
IN OUT
Figure 2. Application Diagram, NCV7349−0
VCC VCC
RLT = 60 W
RLT = 60 W
5 V − reg
Micro−
controller
VBAT
GND
2
5
CANH
CANL
3
6
7
CAN
BUS
3 V − reg
GND
STB
RxD
TxD 1
4
8
NCV7349−3
IN OUT
IN OUT
Figure 3. Application Diagram, NCV7349−3
VCC
VIO
RLT = 60 W
RLT = 60 W
Table 2. PIN FUNCTION DESCRIPTION
Pin Name Description
1 TxD Transmit data input; low input Ù Driving dominant on bus; internal pull−up current
2 GND Ground
3 VCC Supply voltage
4 RxD Receive data output; bus in dominant Ù low output
5
5NC
VIO
Not connected. On NCV7349−0 only.
Input / Output pins supply voltage. On NCV7349−3 only
6 CANL Low−level CAN bus line (low in dominant mode)
7 CANH High−level CAN bus line (high in dominant mode)
8 STB Standby mode control input; internal pull−up current
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FUNCTIONAL DESCRIPTION
NCV7349 has two versions which differ from each other
only by function of pin 5.
NCV7349−0: Pin 5 is not connected. (see Figure 2)
NCV7349−3: Pin 5 is VIO pin, which is supply pin for
transceiver digital inputs/output (supplying pins TxD, RxD,
STB) The VIO pin should be connected to microcontroller
supply pin. By using VIO supply pin shared with
microcontroller the I/O levels between microcontroller and
transceiver are properly adjusted. This adjustment allows in
applications with microcontroller supply down to 3 V to
easy communicate with the transceiver. (See Figure 3)
Operating Modes
NCV7349 provides two modes of operation as illustrated
in Table 3. These modes are selectable through pin STB.
Table 3. OPERATING MODES
Pin
STB Mode
Pin RxD
Low High
Low Normal Bus dominant Bus recessive
High Standby W ake−up request
detected No wake−up
request detected
Normal Mode
In the normal mode, the transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxD and
RxD. The slopes on the bus lines outputs are optimized to
give low EME.
Standby Mode
In standby mode both the transmitter and receiver are
disabled and a very low−power differential receiver
monitors the bus lines for CAN bus activity. The bus lines
are terminated to ground and supply current is reduced to a
minimum, typically 10 mA. When a wake−up request is
detected by the low−power differential receiver, the signal
is first filtered and then verified as a valid wake signal after
a time period of twake, the RxD pin is driven low by the
transceiver to inform the controller of the wake−up request.
VIO Supply pin
The VIO pin available only on NCV7349−3 version
should be connected to microcontroller supply pin. By using
VIO supply pin shared with microcontroller the I/O levels
between microcontroller and transceiver are properly
adjusted. See Figure 3. Pin VIO on NCV7349−3 does not
provide the internal supply voltage for low−power
differential receiver of the transceiver. Detection of
wake−up request is not possible when there is no supply
voltage on pin VCC.
Wake−up
When a valid wake−up (dominant state longer than twake)
is received during the standby mode the RxD pin is driven
low. The wake−up detection is not latched: RxD returns to
High state after tdwakedr when the bus signal is released back
to recessive – see Figure 4.
Figure 4. NCV7349 Wake−up Behavior
CANH
CANL
STB
RxD1
time
normal standby
>tWake <tWake
tdwakerd tdwakedr
tWake(RxD)
NCV7349
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Over−temperature Detection
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds a value of approximately 170°C. Because the
transmitter dissipates most of the power, the power
dissipation and temperature of the IC is reduced. All other
IC functions continue to operate. The transmitter off−state
resets when the temperature decreases below the shutdown
threshold and pin TxD goes high. The thermal protection
circuit is particularly needed when a bus line short circuits.
TxD Dominant Time−out Function
A TxD dominant time−out timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
internal timer value tdom(TxD), the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
This TxD dominant time−out time (tdom(TxD)) defines the
minimum possible bit rate to 15 kbps.
Fail Safe Features
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
Undervoltage on VCC pin prevents the chip sending data
on the bus when there is not enough VCC supply voltage.
After supply is recovered TxD pin must be first released to
high to allow sending dominant bits again. Recovery time
from undervoltage detection is equal to td(stb−nm) time.
VIO supply dropping below VUVDVIO undervoltage
detection level will cause the transmitter to disengage from
the bus (no bus loading) until the VIO voltage recovers
(NCV7349−3 version only).
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
Figure 7). Pins TxD and STB are pulled high internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
VIO supply be removed.
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ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (pin 2). Positive currents flow into the IC. Sinking current means the current is flowing
into the pin; sourcing current means the current is flowing out of the pin.
ABSOLUTE MAXIMUM RATINGS
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Conditions Min. Max. Unit
VSUP Supply voltage VCC, VIO −0.3 +6 V
VCANH DC voltage at pin CANH 0 < VCC < 5.5 V; no time limit −50 +50 V
VCANL DC voltage at pin CANL 0 < VCC < 5.5 V; no time limit −50 +50 V
VIO DC voltage at pin TxD, RxD, STB −0.3 6 V
Vesd Electrostatic discharge voltage at all pins (Note 2)
(Note 3) −6
500 6
500 kV
V
Electrostatic discharge voltage at CANH and CANL pins (Note 4) −10 10 kV
Vschaff Transient voltage (Note 5) −150 100 V
Latch−up Static latch−up at all pins (Note 6) 150 mA
Tstg Storage temperature −55 +150 °C
TAAmbient temperature −40 +125 °C
TJMaximum junction temperature −40 +170 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
2. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor.
3. Standardized charged device model ESD pulses when tested according to ESD−STM5.3.1−1999.
4. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 150 pF capacitor through a 330 W resistor
referenced to GND.
5. Pulses 1, 2a, 3a and 3b according to ISO 7637 part 3. Indicative values based on structural similarity to NCV7340 where results were verified
by external test house.
6. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78.
Table 5. THERMAL CHARACTERISTICS
Symbol Parameter Conditions Value Unit
RqJA_1 Thermal Resistance Junction−to−Air, 1S0P PCB (Note 7) Free air 125 K/W
RqJA_2 Thermal Resistance Junction−to−Air, 2S2P PCB (Note 8) Free air 75 K/W
7. Test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage
8. Test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage
NCV7349
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ELECTRICAL CHARACTERISTICS
Table 6. CHARACTERISTICS (VCC = 4.75 V to 5.25 V; VIO = 2.8 V to 5.5 V (NCV7349−3 only); TJ = −40 to +150°C; RLT = 60 W
unless specified otherwise. On chip versions without VIO pin, reference voltage for all digital inputs and outputs is VCC instead of VIO.)
Symbol Parameter Conditions Min Typ Max Unit
SUPPLY (Pin VCC)
ICC Supply current Dominant; VTxD = 0 V
Recessive; VTxD = VIO − 48
675
10 mA
ICCS Supply current in standby mode TJ ≤ 100°C, (Note 9) − 10 15 mA
VUVDVCC Undervoltage detection voltage on VCC
pin 2 3 4 V
SUPPLY (pin VIO) on NCV7349−3 Version Only
VIO Supply voltage on pin VIO 2.8 − 5.5 V
IIOS Supply current on pin VIO in standby
mode Standby mode − 1 − mA
IIONM Supply current on pin VIO in normal
mode Dominant; VTxD = 0 V
Recessive; VTxD = VIO
For VIO ≤ VCC
− − 1
0.2 mA
VUVDVIO Undervoltage detection voltage on VIO
pin 1.3 − 2.7 V
TRANSMITTER DATA INPUT (Pin TxD)
VIH High−level input voltage Output recessive 2.0 − VIO V
VIL Low−level input voltage Output dominant −0.3 − +0.8 V
IIH High−level input current VTxD = VIO −5 0 +5 mA
IIL Low−level input current VTxD = 0 V −350 −200 −mA
CiInput capacitance (Note 9) − 5 10 pF
TRANSMITTER MODE SELECT (Pin STB)
VIH High−level input voltage Standby mode 2.0 − VIO V
VIL Low−level input voltage Normal mode −0.3 − +0.8 V
IIH High−level input current VSTB = VIO −5 0 +5 mA
IIL0 Low−level input current, NCV7349−0 VSTB = 0 V −10 −4 −1 mA
IIL3 Low−level input current, NCV7349−3 VSTB = 0 V −40 −20 −4 mA
CiInput capacitance (Note 9) − 5 10 pF
RECEIVER DATA OUTPUT (Pin RxD)
IOH High−level output current Normal mode, VRxD = VIO –
0.4 V −1 −0.4 −0.1 mA
IOL Low−level output current VRxD = 0.4 V 1.6 6 12 mA
VOH High−level output voltage,
Weaker RxD pin in Standby mode is on
NCV7349−0 version only
Standby mode, IRxD = −100 mAVCC − 1.1 VCC − 0.7 VCC − 0.4 V
BUS LINES (Pins CANH and CANL)
Vo(reces) (norm) Recessive bus voltage on pins CANH
and CANL VTxD = VIO; no load;
normal mode 2.0 2.5 3.0 V
Vo(reces) (stby) Recessive bus voltage on pins CANH
and CANL VTxD = VIO; no load;
standby mode −100 0 100 mV
Io(reces) (CANH) Recessive output current at pin CANH −35 V < VCANH < +35 V;
0 V < VCC < 5.25 V −2.5 − +2.5 mA
Io(reces) (CANL) Recessive output current at pin CANL −35 V < VCANL < +35 V;
0 V < VCC < 5.25 V −2.5 − +2.5 mA
9. Values based on design and characterization, not tested in production
NCV7349
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Table 6. CHARACTERISTICS (VCC = 4.75 V to 5.25 V; VIO = 2.8 V to 5.5 V (NCV7349−3 only); TJ = −40 to +150°C; RLT = 60 W
unless specified otherwise. On chip versions without VIO pin, reference voltage for all digital inputs and outputs is VCC instead of VIO.)
Symbol UnitMaxTypMinConditionsParameter
BUS LINES (Pins CANH and CANL)
ILI(CANH) Input leakage current to pin CANH 0 W < R(VCC to GND) < 1 MW
VCANL = VCANH = 5 V −10 0 10 mA
ILI(CANL) Input leakage current to pin CANL 0 W < R(VCC to GND) < 1 MW
VCANL = VCANH = 5 V −10 0 10 mA
Vo(dom) (CANH) Dominant output voltage at pin CANH VTxD = 0 V 3.0 3.6 4.25 V
Vo(dom) (CANL) Dominant output voltage at pin CANL VTxD = 0 V 0.5 1.4 1.75 V
Vo(dif) (bus_dom) Differential bus output voltage
(VCANH − VCANL)VTxD = 0 V; dominant;
45 W < RLT < 65 W1.5 2.25 3.0 V
Vo(dif) (bus_rec) Differential bus output voltage
(VCANH − VCANL)VTxD = VIO; recessive; no load −120 0 +50 mV
Io(sc) (CANH) Short circuit output current at pin CANH VCANH = 0 V; VTxD = 0 V −100 −70 −45 mA
Io(sc) (CANL) Short circuit output current at pin CANL VCANL = 36 V; VTxD = 0 V 45 70 100 mA
Vi(dif)R (th) Differential receiver threshold voltage –
Dominant to Recessive (see Figure 6) −2 V < VCANL < +7 V;
−2 V < VCANH < +7 V 0.5 0.6 0.7 V
Vi(dif)D (th) Differential receiver threshold voltage –
Recessive to Dominant (see Figure 6) −2 V < VCANL < +7 V;
−2 V < VCANH < +7 V 0.7 0.8 0.9 V
VihcmR(dif) (th) Differential receiver threshold voltage –
Dominant to Recessive (see Figure 6) −35 V < VCANL < +35 V;
−35 V < VCANH < +35 V 0.4 − 0.8 V
VihcmD(dif) (th) Differential receiver threshold voltage –
Recessive to Dominant (see Figure 6) −35 V < VCANL < +35 V;
−35 V < VCANH < +35 V 0.6 − 1 V
VihcmD12(dif) (th) Differential receiver threshold voltage –
Both transitions (see Figure 6) −12 V < VCANL < +12 V;
−12 V < VCANH < +12 V 0.5 − 0.9 V
Vi(dif) (hys) Differential receiver input voltage hys-
teresis −2 V < VCANL < +7 V;
−2 V < VCANH < +7 V 100 200 300 mV
Vi(dif)
(th)_STDBY Differential receiver threshold voltage
in standby mode −12 V < VCANL < +12 V;
−12 V < VCANH < +12 V 0.4 0.8 1.15 V
Ri(cm) (CANH) Common−mode input resistance at pin
CANH 15 26 37 kW
Ri(cm) (CANL) Common−mode input resistance at pin
CANL 15 26 37 kW
Ri(cm) (m) Matching between pin CANH and pin
CANL common mode input resistance VCANH = VCANL −3 0 +3 %
Ri(dif) Differential input resistance 25 50 75 kW
Ci(CANH) Input capacitance at pin CANH VTxD = VIO; (Note 9) − − 30 pF
Ci(CANL) Input capacitance at pin CANL VTxD = VIO; (Note 9) − − 30 pF
Ci(dif) Differential input capacitance VTxD = VIO; (Note 9) − 3.75 10 pF
THERMAL SHUTDOWN
TJ(sd) Shutdown junction temperature Junction temperature rising 150 170 185 °C
TIMING CHARACTERISTICS (see Figure 5 and Figure 8)
td(TxD−BUSon) Delay TxD to bus active Ci = 100 pF between CANH to
CANL − 50 − ns
td(TxD−BUSoff) Delay TxD to bus inactive Ci = 100 pF between CANH to
CANL − 60 − ns
td(BUSon−RxD) Delay bus active to RxD CRxD = 15 pF − 60 − ns
td(BUSoff−RxD) Delay bus inactive to RxD CRxD = 15 pF − 60 − ns
9. Values based on design and characterization, not tested in production
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Table 6. CHARACTERISTICS (VCC = 4.75 V to 5.25 V; VIO = 2.8 V to 5.5 V (NCV7349−3 only); TJ = −40 to +150°C; RLT = 60 W
unless specified otherwise. On chip versions without VIO pin, reference voltage for all digital inputs and outputs is VCC instead of VIO.)
Symbol UnitMaxTypMinConditionsParameter
TIMING CHARACTERISTICS (see Figure 5 and Figure 8)
tpd Propagation delay TxD to RxD
(NCV7349−0 version) Ci = 100 pF between CANH to
CANL − 125 245 ns
Propagation delay TxD to RxD
(NCV7349−3 version) Ci = 100 pF between CANH to
CANL − 130 250 ns
td(stb−nm) Delay standby mode to normal mode 5 8 20 ms
twake Dominant time for wake−up via bus 0.5 2.5 5 ms
tdwakerd Delay to flag wake event (recessive to
dominant transitions) (See Figure 4) Valid bus wake−up event,
CRxD = 15 pF 1 4.5 10 ms
tdwakedr Delay to flag wake event (dominant to
recessive transitions) (See Figure 4) Valid bus wake−up event,
CRxD = 15 pF 0.5 3.3 7 ms
twake(RxD) Minimum pulse width on RxD
(See Figure 4) 5 ms tWAKE, CRxD = 15 pF 0.5 − − ms
tdom(TxD) TxD dominant time for time−out VTxD = 0 V 1.2 2.6 4 ms
9. Values based on design and characterization, not tested in production
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
MEASUREMENT SETUPS AND DEFINITIONS
dominant
0.9 V
0.5 V
recessive
50%
recessive
50%
TxD
CANH
CANL
RxD
Figure 5. Transceiver Timing Diagram
tpd
0.7 x VCC (*)
td(BUSoff−RXD)
0.3 x VCC (*)
tpd
td(BUSon−RXD)
td(TxD−BUSoff)
td(TxD−BUSon)
Vi(dif) =
VCANH − VCANL
*On NCV7349−3 VCC is replaced by VIO
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High
Low
0.5 0.9
Hysteresis
Figure 6. Hysteresis of the Receiver
VRxD
Vi(dif)(hys)
NCV7349
GND
2
3CANH
CANL
5
6
7
STB
8
RxD 4
TxD 1
100 nF
+5 V
15 pF
1 nF
1 nF
Transient
Generator
Figure 7. Test Circuit for Automotive Transients
VCC
NCV7349
GND
2
3CANH
CANL
5
6
7
STB
8
RxD 4
TxD 1
100 pF
100 nF
+5 V
15 pF
Figure 8. Test Circuit for Timing Characteristics
VCC
CLT
RLT
60 W
DEVICE ORDERING INFORMATION
Part Number Description Temperature
Range Package Shipping †
NCV7349D10R2G High Speed Low Power CAN Transceiver
for the Japanese Market −40°C to +125°CSOIC 150 8 GREEN
(Matte Sn, JEDEC
MS−012)
(Pb−Free)
3000 / Tape &
Reel
NCV7349D13R2G High Speed Low Power CAN Transceiver
for the Japanese Market with VIO pin
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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UBLICATION ORDERING INFORMATION
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Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
NCV7349/D
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