GENERAL DESCRIPTION
The DS1337 serial real-time clock is a low-power
clock/calendar with two programmable time-of-day
alarms and a programmable square-wave output.
Address and data are transferred serially through an
I2C bus. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year
information. The date at the end of the month is
autom atically adjuste d for months with few er than 31
days, including corrections for leap year. The clock
operates in either the 24-hour or 12-hour format with
AM/PM indicat or .
The device is fully accessible through the serial
interface while VCC is between 1.8V and 5.5V. I2C
operation is not guaranteed below 1.8V.
Tim ekeeping operat ion is m aintained with VCC as low
as 1.3V.
APPLICATIONS
Handhelds (GPS, POS Terminal, MP3 Player)
Consumer Electronics (Set-Top Box, VCR/Digital
Recording)
Office Equipment (Fax/Printer, Copier)
Medical (Glucometer, Medicine Dispenser)
Telecommunications (Router, Switch, Server)
Other (Utility Meter, Vending Machine, Thermostat,
Modem)
TYPICAL OPERATING CIRCUIT
BENEFITS AND FEATURES
• Completely Manages All Timekeeping
Functions
o Real-Time Clock (RTC) Counts Seconds,
Minutes, Hours, Day, Date, Month, and
Year with Leap-Year Compensation Valid
Up to 2100
o Two Time-of-Day Alarms
o Programmable Square-Wave Output
Defaults to 32kHz on Power-Up
o Oscillator Stop Flag
• Interfa ces with Most Microc ontrol le rs
o I2C Serial Interface
• Surface-Mount Package with an Integrated
Crystal (DC1337C) Saves Additional Space
and Simplifies Design
-40
°
C to +85
°
C Industrial Temperature Range
Supports Operation in a Wide Range of
Applications
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE TOP
MARK†
DS1337+ -40°C to +85°C 8 DIP (300 mils) DS1337
DS1337S+
-40°C to +85°C
8 SO (150 mils)
DS1337
DS1337U+ -40°C to +85°C
8
µ
SOP
1337
DS1337C#
-40°C to +85°C
16 SO (300 mils)
DS1337C
+ Denotes a lead(Pb)-free/RoHS-compliant dev ic e.
# Denotes a RoHS-compliant device that may include lead that is
exempt under the RoHS requirements. The lead finish is JESD97
category e3, and is compatible with both lead-bas ed and lead-free
soldering proc ess es.
† A “+” anywhere on the top mark denotes a lead-free device. A
“#” denotes a RoHS-compliant device.
Pin Configurations appear at end of data sheet.
19-4652; 4/15
DS1337
I
2
C Serial Real-Time Clock
1 of 16
Note: Some revisi ons of this device may incorporate deviations from published specificati ons known as errata. Multipl e revisi ons of any device
may be simultaneously avail abl e through various sal es channels. For information about device errata, go to: www.maxim-ic.com/errata.
DS1337 I2C Serial Real-Time Clock
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground…………………………………………………………...…-0.3V to +6.0V
Operating Temperature Range (Noncondensing)………………………………………………………….-40°C to +85°C
Storage Temperature Range………………………………………………………………………………..-55°C to +125°C
Soldering Temperature…………………………………………………………See IPC/JEDEC J-STD-020 Specific atio n
Stresses beyond those listed under “Abs ol ute Maximum Ratings” may caus e permanent damage to the device. These are stress ratings only,
and functional operat i on of the device at these or any other conditions beyond those i ndicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40°C to +85°C)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC Suppl y Voltage VCC Full operation 1.8 3.3 5.5 V
VCCT
Timekeeping (Note
5)
1.3 1.8 V
Logic 1 VIH SCL, SD A 0.7 x VCC VCC + 0.3 V
INTA, SQW/INTB 5.5
Logic 0 VIL -0.3 +0.3 x VCC V
DC ELECTRICAL CHARACTERISTICS—Full Operation
(VCC = 1.8V to 5.5V, TA = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Leakage ILI (Note 2) -1 +1 µA
I/O Leakage ILO (Note 3) -1 +1 µA
Logic 0 Output (VOL = 0.4V) IOL (Note 3) 3 mA
Active Supply Current ICCA (Note 4) 150 µA
Standby Current ICCS (Notes 5, 6) 1.5 µA
DC ELECTRICAL CHARACTERISTICS--Timekeeping
(VCC = 1.3V to 1.8V, TA = -40°C to +85°C .) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Timekeeping Current
(Osc illator En abled) ICCTOSC (Notes 5, 7, 8, 9) 425 600 nA
Data-Retention Current
(Oscillator Disabled) ICCTDDR (Notes 5, 9) 100 nA
2 of 16
DS1337 I2C Serial Real-Time Clock
AC ELECTRICAL CHARACTERISTICS
(VCC = 1.8V to 5.5V, TA = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency fSCL
100
400
kHz
0
100
Bus Free Time Between a
STOP and START Condition tBUF Fast mode 1.3 µs
Standard mode 4.7
Hold Time (Repeated)
START Condition (Note 10) tHD:STA Fast mode 0.6 µs
Standard mode 4.0
LOW Period of SCL Clock tLOW Fast mode 1.3 µs
Standard mode 4.7
HIGH Period of SCL Clock tHIGH
0.6
µs
4.0
Setup Time for a Repeated
START Condition tSU:STA
0.6
µs
4.7
Data Hold Time
(Notes 11, 12)
tHD:DAT
0
0.9
µs
0
Data Setup Time (Note 13) tSU:DAT
100
ns
250
Rise Time of Both SDA and
SCL Signals (Note 14)
tR
20 + 0.1CB
300
ns
20 + 0.1CB
1000
Fall Time of Both SDA and
SCL Signals (Note 14) tF
20 + 0.1CB
300
ns
20 + 0.1CB
300
Setup Time for STOP
Condition
tSU:STO
0.6
µs
4.0
Capacitive Load for Each Bus
Line
CB (Note 14) 400 pF
I/O Capacitance (SDA, SCL) CI/O (Note 15) 10 pF
Oscillator Stop Flag (OSF)
Delay
tOSF 100 ms
Note 1:
Limi ts at -40°C are guaranteed by design and are not production tested.
Note 2:
SCL only.
Note 3:
SDA,
INTA
, and SQW/
INTB
.
Note 4:
ICCA—SCL clocking at max frequency = 400kHz, VIL = 0.0V, VIH = V CC.
Note 5:
Specified with the I2C bus inacti ve , VIL = 0 .0 V, VIH = VCC.
Note 6:
SQW enabled.
Note 7:
Specified with the SQW function disabled by setti ng INTCN = 1.
Note 8:
Using recommended crystal on X1 and X2.
Note 9:
The device is fully accessibl e when 1.8 ≤ VCC ≤ 5.5V. Time and date are maintained when 1.3V ≤ VCC ≤ 1.8V.
Note 10:
After this period, t he first clock puls e is generat ed
Note 11: A device must internall y provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to
bridge the undefined region of the fall i ng edge of SCL.
Note 12:
The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 13: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 25 0ns must then be met. This is
automatical l y the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL
line is released.
Note 14:
CB—total capacitance of one bus line in pF.
Note 15:
Guaranteed by design. Not production t ested.
3 of 16
DS1337 I2C Serial Real-Time Clock
Note 16: The parameter tOSF is the period of time that the oscillator must be stopped for the OSF bit to be set over the
voltage range of VCC(MIN) ≤ VCC ≤ VCC(MAX)..
TYPICAL OPERATING CHARACTERISTICS
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
I
CCA
vs. V
CC
0
25
50
75
100
125
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
V
CC
(V)
I
CC
(uA )
I
CC
vs. V
CC
300
400
500
600
700
800
900
1000
1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
V
CC
(V)
I
CC
(nA )
INTCN = 0
(Squarewave on)
INTCN = 1
(Squarewave off)
ICCTOSC
ICCS
I
CCS
vs. Temper at ur e
350
400
450
500
550
600
650
700
-40.0 -20.0 0.0 20.0 40.0 60.0 80.0
VCC (V)
I
CC
(nA )
INTCN = 0
(Squarewave on)
VCC = 3.0V
INTCN = 1
(Squarewave off)
OSCILLATOR FREQUENCY vs. V
CC
32768
32768.05
32768.1
32768.15
32768.2
32768.25
32768.3
32768.35
1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8
V
CC
(V)
FREQUENCY (Hz)
4 of 16
DS1337 I2C Serial Real-Time Clock
PIN DESCRIPTION
PIN
NAME FUNCTION
8
16
1 — X1 Connections for a Standard 32.768kHz Quartz Crystal. The internal
oscillator circuitry is designed for operation with a crystal having a specified
load capacitance (CL) of 6pF. For more information about crystal selection
and cry stal lay out considerations, refer to App licat io n Note 58: Cry s tal
Consider at ions w ith Dallas Real-Time Clocks. An external 32.768kHz
oscillator can also drive the DS1337. In this configuration, the X1 pin is
connected to the external oscillator signal and the X2 pin is floated.
2 — X2
3 14 INTA
Interrupt Output. When enabled, INTA is asserted low w hen the
time/day/date matches the values set in the alarm registers. This pin is an
open-drain output and requires an external pullup resistor. The pull up
voltage may be up to 5.5V, regardless of the voltage on VCC. If not used, this pin
may be left floating.
4 15 GND Ground. DC power is provided to the device on this pin.
5 16 SDA Serial Data Input/Output. SDA is the input/output pin for the I
2
C serial
interface. The SDA pin is open-drain output and requires an external pullup
resistor.
6 1 SCL
Serial Clock Input. SCL is used to synchronize data movement on the serial
interface.
7 2 SQW/INTB
Square-Wave/Interrupt Output. Programmable square-wave or interrupt
output signal. It is an open-drain output and requires an external pullup
resistor. The pull up voltage may be up to 5.5V, regardless of the voltage on VCC.
If not used, this pin may be left floating.
8 3 VCC DC Power. DC power is provided to the device on this pin.
— 4–13 N.C. No Connect. These pins are not connected internally, but must be
grounded for proper operation.
TIMING DIAGRAM
5 of 16
DS1337 I2C Serial Real-Time Clock
BLOCK DIAGRAM
DETAILED DESCRIPTION
The Block Diagram sho ws the m ain elements of the DS1337. As shown, com munic ations to and f rom the D S1337
occur serially over an I2C bus. The DS1337 operates as a slave device on the serial bus. Access is obtained by
implementing a START condition and providing a device identification code, followed by data. Subsequent
registers can be accessed sequentiall y until a ST OP condition is executed. T he device is fully accessible thr ough
the I2C interf ac e whenever VCC is between 5 . 5V and 1.8V. I2C oper at ion is no t gua r antee d whe n V CC is be lo w 1.8V .
The DS1337 maintains the time and date when VCC is as low as 1.3V.
OSCILLATOR CIRCUIT
The DS1337 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or
capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. The Block Diagram
shows a functional schem atic of the oscillator circuit. The startup time is usually less than 1 second when using a
crystal with the specified characteristics.
Table 1. Crystal Specifications*
PARAMETER SYMBOL MIN TYP MAX UNITS
Nominal Frequency f
O
32.768 kHz
Series Resistance ESR 50 kΩ
Load Capacitance CL 6 pF
*The crystal, t races, and crystal input pins should be isolated from RF generating signals. Refer to
Applic ation Note 58: Crystal Considerati ons for Dallas Real-Time Cloc ks for additional specifications.
6 of 16
DS1337 I2C Serial Real-Time Clock
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between
the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal
frequency drift caused by temperature shifts creates additional error. External circuit noise coupled into the
oscillator circuit can result in the clock running fast. Figure 1 shows a typical PC board layout for isolating the
crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time
Clocks for detailed information.
Figure 1. Typical PC Board Layout for Crystal
DS1337C ONLY
The DS133 7C integra tes a standar d 32,768H z crysta l in the pack age. Typical ac curac y at nominal VCC and +25°C
is approximately +10ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature.
OPERATING MODES
The amount of current consumed by the DS1337 is determined, in part, by the I2C interface and oscillator
operation. The following table shows the relationship between the operating mode and the corresponding ICC
parameter.
Operating Mode
VCC
Power
I
2
C Interface Active
1.8V ≤ VCC ≤ 5.5V
ICC Active (ICCA)
I
2
C Interface Inactive
1.8V ≤ VCC ≤ 5.5V
ICC Standby (ICCS)
I
2
C Interface Inactive
1.3V ≤ VCC ≤ 1.8V
Timekeeping (ICCTOSC)
I2C Interface Inactive
Oscillator Disabled
1.3V ≤ VCC ≤ 1.8V
Data Retention
(ICCTDDR)
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
X1
X2
GND
NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED
AREA (UPPER LEFT-HAND QUADRANT) OF THE PACKAGE
UNL ESS THERE IS A GR OUND PLAN E BETWEEN TH E SIGNAL
LINE AND THE PA CK AGE.
7 of 16
DS1337 I2C Serial Real-Time Clock
ADDRESS MAP
Table 2 shows the address map for the DS1337 registers. During a multibyte access, when the address pointer
reaches th e end of the regi ster spac e (0Fh) it wraps a round to location 00 h. On a n I2C ST ART, STO P, or addres s
pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time
information is read from these secondary registers, while the clock may continue to run. This eliminates the need
to re-read the registers in case of an update of the main registers during a read.
Table 2. Timekeep er R eg ist ers
ADDRESS BIT 7 BIT 6 BIT 5 B IT 4 BIT 3 BI T 2 BIT 1 B IT 0 FUNCTION RANGE
00H 0 10 Seconds Seconds Seconds 00–59
01H 0 10 Minutes Minutes Minutes 00–59
02H 0 12/24 AM/PM 10 Hour Hour Hours
1–12
+AM/PM
00–23
10 Hour
03H 0 0 0 0 0 Day Day 1–7
04H 0 0 10 Date Date Date 01–31
05H Century 0 0 10 Month Month
Month/
Century
01–12 +
Century
06H 10 Year Year Year 00–99
07H A1M1 10 Seconds Seconds Alarm 1
Seconds 00–59
08H A1M2 10 Minutes Minutes
Alarm 1
Minutes
00–59
09H A1M3 12/24 AM/PM 10 Hour Hour Ala rm 1
Hours
1–12 +
AM/PM
00–23
10 Hour
0AH A1M4 DY/DT 10 Date Day
Alarm 1
Day
1–7
Date
Alarm 1
Date
01–31
0BH A2M2 10 Minutes Minutes
Alarm 2
Minutes
00–59
0CH A2M3 12/24 AM/PM 10 Hour Hour Ala rm 2
Hours
1–12 +
AM/PM
00–23
10 Hour
0DH A2M4 DY/DT 10 Date Day
Alarm 2
Day
1–7
Date
Alarm 2
Date
01–31
0EH EOSC 0 0 RS2 RS1 INTCN A2IE A1IE Control —
0FH OSF 0 0 0 0 0 A2F A1F Status —
Note: U nless otherwise s pecifi ed, the state of the regi sters is not defined when power is first appl ied or VCC falls below th e VOSC.
I2C INTERFACE
The I2C interface is accessible whenever VCC is at a valid level. If a microcontroller connected to the DS1337 resets
while reading from the DS1337 during an I2C read, the two could become unsynchronized. The microcontroller must
terminate the last byte read with a Not-Acknowledge (NACK) to properly terminate the read. When the microcontroller
resets, the DS1337 I2C interface may be placed into a known state by toggling SCL until SDA is observed to be at a
high level. At that point the microcontroller should pull SDA low while SCL is high, generating a START condition.
8 of 16
DS1337 I2C Serial Real-Time Clock
CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. The RTC registers are
illustrated in Table 2. The time and calendar are set or initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the binary-coded decimal (BCD) format.
The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but
must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries
result in undefined operation.
W hen reading or wr iting th e time and date regis ters, sec ondary (user ) buff ers are used t o prevent er rors when the
internal registers update. When reading the time and date registers, the user buffers are synchronized to the
internal registers on any start or stop and when the register pointer rolls over to zero.
The count down chain is reset whene ver the secon ds register is written. W rite trans fers occur on the acknowledg e
pulse from the device. To avoid rollover issues, once the countdown chain is reset, the remaining time and date
registers must be written within 1 s econd. The 1H z square-wa ve output, if ena ble, trans itions high 5 00ms after the
seconds data transfer, provided the oscillator is already running.
The DS1337 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or
24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). All hours values,
including the alarms, must be reinitialized whenever the 12/24-hour mode bit is changed. The century bit (bit 7 of
the month register) is toggled when the years register overflows from 99–00.
ALARMS
The DS1337 contains two time-of-day/date alarms. Alarm 1 can be set by writing to registers 07h–0Ah. Alarm 2
can be set by writing to registers 0Bh–0Dh. The alarms can be programmed (by the INTCN bit of the control
register) t o operate in two different modes—each a larm c an drive its own s eparate interrupt output or b oth alarms
can drive a com mon interrupt outp ut. Bit 7 of each of the tim e-of-day/date alarm registers are mask bits (Table 2).
When all of the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping
registers 00h–06h match the values stored in the time-of-day/date alarm registers. The alarms can also be
programmed to repeat every second, minute, hour, day, or date. Table 3 shows the possible settings.
Configurations not listed in the table result in illogical operation.
The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0–5 of that
register reflects the da y of the week or the date of t he m onth. If DY/DT is written t o log ic 0, the alar m is the result of
a match with date of the month. If DY/DT is written to logic 1, the alarm is the result of a match with day of the
week.
When the RTC register values match alarm register settings, the corresponding alarm flag (A1F or A2F) bit is set
to logic 1. The bit(s) will remain at a logic 1 until written to a logic 0 by the user. If the corresponding alarm
interrupt en able ( A1IE or A 2IE) is also s et to log ic 1, t he alarm condition ac tiv ates one of the interr upt out put ( INTA
or SQW/INTB) signals. The match is tested on the once-per-second update of the time and date registers.
9 of 16
DS1337 I2C Serial Real-Time Clock
Table 3. Alarm Mask Bits
DY/
DT
ALARM 1 REGISTER MASK BITS
(BIT 7)
ALARM RATE
A1M4
A1M3
A1M2
A1M1
X
1
1
1
1
Alarm once per second
X
1
1
1
0
Alarm when seconds match
X
1
1
0
0
Alarm when minutes and seconds match
X
1
0
0
0
Alarm when hours, minutes, and seconds match
0 0 0 0 0 Alarm when date, hours, minutes, and seconds
match
1
0
0
0
0
Alarm when day, hours, minutes, and seconds match
DY/
DT
ALARM 2 REGISTER MASK BITS
(BIT 7)
ALARM RATE
A2M4
A2M3
A2M2
X
1
1
1
Alarm once per minute (00 seconds of every minute)
X
1
1
0
Alarm when minutes match
X
1
0
0
Alarm when hours and minutes match
0
0
0
0
Alarm when date, hours, and minutes match
1
0
0
0
Alarm when day, hours, and minutes match
SPECIAL-PURPOSE REGISTERS
The DS1337 has two additional registers (control and status) that control the RTC, alarms, and square-wave
output.
Control Register (0 Eh)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EOSC 0 0 RS2 RS1 INTCN A2IE A1IE
Bit 7:
Enable Os cillat o r
(EOSC
). This active-low bit when s et t o l ogic 0 s t ar ts th e os cil lator. When this bit is s et to
logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequenc y of the square-wave output when the
square wave has bee n enabled. The table be lo w sh o ws the squar e-wave f r equ en c ies that c an be s el ect ed wi th the
RS bits. These bits are both set to logic 1 (32kHz) when power is first applied.
SQW/
INTB
Output
INTCN RS2 RS1 SQW/
INTB
OUTPUT
A2IE
0
0
0
1Hz
X
0
0
1
4.096kHz
X
0
1
0
8.192kHz
X
0
1
1
32.768kHz
X
1
X
X
A2F
1
Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output
pins. W hen the INTCN bit is set to logic 1, a match between the tim ek eeping registers and the alarm 1 registers l
activates the INTA pin ( pr o vided that the alar m is enabled) and a match bet ween the t imekeeping reg is ters and t he
alarm 2 registers activates the SQW/INTB pin (provided that the alarm is enabled). When the INTCN bit is set to
logic 0, a square wave is output on the SQW/INTB pin. This bit is set to logic 0 when power is first applied.
10 of 16
DS1337 I2C Serial Real-Time Clock
Bit 1: Alarm 2 Interrupt Enable (A2IE). W hen s et to l ogic 1, this bi t per mits the alar m 2 flag (A2F) b it i n th e s tatus
register to assert INTA (when INTCN = 0) or t o assert SQW /INTB (when INT CN = 1). W hen the A2IE bit is set to
logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first
applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). W hen s et to l ogic 1 , th is bi t per mits the alar m 1 flag (A1F) b it i n th e s tatus
register to as sert INTA. W hen the A1IE bit is s et to logic 0, the A1F bit does not init iate the INTA signal. The A1I E
bit is disabled (logic 0) when power is first applied.
Status Register (0Fh)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OSF 0 0 0 0 0 A2F A1F
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in th is bi t i ndicates that the osci llator eith er is s to ppe d or was s to pped
for s om e perio d of time and may be us ed to j udg e t he va lid ity of the c loc k and c a l endar data. T his bit is set to l og ic
1 anytime that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on VCC is insufficient to support oscillation.
3) The EOSC bit is turned off.
4) External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers.
This f lag can be use d to generate an interru pt on eithe r INTA or SQW /INTB depen ding on the s tatus of the INT CN
bit in the control register. If the INTCN bit is set to logic 0 and A2F is at logic 1 (and A2IE bit is also logic 1), the
INTA pin go es lo w. If the INT CN bit is s et to logic 1 and A2F is logic 1 ( and A2I E bit is also log ic 1), the SQ W/INTB
pin goes low. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to
logic 1 leaves the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If
the A1IE bit is also logic 1, the INTA pin goes low. A1F is cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
11 of 16
DS1337 I2C Serial Real-Time Clock
I2C SERIAL DATA BUS
The DS13 37 s u pports the I2C bus protoc ol. A de vice that se nds d ata ont o the bus is def in ed as a t ra ns mitter and a
device rec eiving data as a receiver . The devic e that controls the m essage is call ed a mas ter. The devices that are
controlled by the m aster are refer red to as slaves . A master device that gen erates the ser ial clock (SCL), controls
the bus ac cess , and gener ates the START and STO P conditi ons m ust control the bus . T he DS13 37 oper at es as a
slave on the I2C bus. Within the bus specifications a standard mode (100kHz maximum clock rate) and a fast mode
(400kHz maximum clock rate) are defined. The DS1337 works in both modes. Connections to the bus are made
through the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 2):
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change i n the state of the data line, fr om HI GH to LOW , while the cl ock is HIGH, def ines a
START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable
for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per bit of data.
Each data tra nsfer is init iated with a ST ART condition and ter minated with a ST OP condition. T he number of data
bytes trans fer red bet ween ST ART and ST OP cond itio ns are not lim ited, and are determ ined b y the m as ter dev ice.
The information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Acknowledge: Each receivi ng device, when addr essed, is o bl iged to genera te a n ac knowledge af ter th e r e cept ion
of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that
the SDA l ine is stable LOW dur ing the HIGH peri od of the ack nowledge-relat ed clock pulse. Of course, set up and
hold times must be taken into account. A master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been c lock ed out of the s lave. In this c ase, the sla ve m ust leave the data
line HIGH to enable the master to generate the STOP condition.
12 of 16
DS1337 I2C Serial Real-Time Clock
Figure 2. Data Transfer on I2C Serial Bus
Depending upon the state of the R/W bit, two types of data transfer are possible:
1) Data transfer from a mas ter transmitter to a slave receiver. The first byte transmitted by the master is the
slave addres s. Next f ollows a num ber of data bytes. T he slave returns an ack nowledge bit af ter each rec eived
byte. Data is transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave
address). The slave then returns an acknowledge bit, followed by the slave transmitting a number of data
bytes. T he master retur ns an acknowledge b it af ter al l rec eived b ytes oth er than th e last byte. At the e nd of th e
last recei ved byte, a “not a cknowledge” is ret urned. The m aster device generat es all of the s erial clock puls es
and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START
condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not
released. Data is transferred with the most significant bit (MSB) first.
The DS1337 can operate in the following two modes:
1) Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each
byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the
slave address and direction bit (Figure 3). The slave address byte is the first byte received after the master
generates the START condition. The slave address byte contains the 7-bit DS1337 address, which is 1101000,
followed b y the direct ion bi t ( R/W), which, f or a wri te, i s 0. Af ter rec eiving and d ecodi ng the sl ave a ddress b yte
the device outputs an acknowledge on the SDA line. After the DS1337 acknowledges the slave address +
write bit, the mas ter transm its a register address to the D S1337. T his sets the r egister pointer on th e DS1337 .
The master ma y then transmit zero or more bytes of data, with the D S 13 37 acknowledgi ng eac h byte receive d.
The addres s poin ter will increm ent af ter eac h data byte is transferred. T he m as ter generates a ST O P c ond itio n
to terminate the data write.
2) Slave T ransmitter Mode (Read M ode): The first byte is r eceived and handled as in the slave receiver m ode.
However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is
transmitted on SDA by the DS1337 while the serial clock is input on SCL. START and STOP conditions are
recognize d as the be gi nn in g an d end of a s erial transf er (Figure 4 and Figure 5). The s lav e a ddres s byte is t he
first byte received after the master generates a START condition. The slave address byte contains the 7-bit
DS1337 addr ess, which is 1101000, f ollowed b y th e direction b it (R/W), which, for a read, is 1. After rec eiving
and decoding the slave address byte the device outputs an acknowledge on the SDA line. The DS1337 then
begins to transmit data starting with the register address pointed to by the register pointer. If the register
pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in
the register pointer. The DS1337 must receive a “not acknowledge” to end a read.
13 of 16
DS1337 I2C Serial Real-Time Clock
Figure 3. Data Wr ite—Slave Receiver Mode
Figure 4. Data Read (from Current Pointer Location)—Slave Transmitter Mode
Figure 5. Data Read (Write Pointer, Then Read)—Slave Receive and Transmit
...
AXXXXXXXX
A
S0XXXXXXXX AXXXXXXXX AXXXXXXXX AP
S - Sta rt
A - Acknowl edge ( ACK)
P - Sto p
<R/W>
DATA TRANSFERRED
(X+1 BYTES + ACKNOWLEDGE)
1101000
<Slave Address> <Word Address (n)> <Data(n)> <Data(n+1)> <Data(n+X)>
Master to slave
Slave to master
...AXXXXXXXXA1101000S 1 XXXXXXXX AXXXXXXXX XXXXXXXX AP
<Data(n+2)> <Data(n+X)>
A
S - Sta rt
A - Acknowl edge ( ACK)
P - Sto p
A - Not Acknowledge (NACK)
<RW>
DATA TRANSFERRED
(X+1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK
<Slave Address> <Data(n)> <Data(n+1)>
Master to slave
Slave to master
...AXXXXXXXX XXXXXXXX AXXXXXXXX AXXXXXXXX AP
S - Sta rt
Sr - Repeated Start
A - Acknowl edge ( ACK)
P - Sto p
A - Not Acknowledge (NACK)
DATA TRANSFERRED
(X+1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK
AXXXXXXXXA1101000
S 0
<RW>
<Word Address (n)>
A
1101000Sr 1
<RW>
<Slave Address>
<Data(n)> <Data(n+1)> <Data(n+2)> <Data(n+X)>
Master to slave
Slave to master
14 of 16
DS1337 I2C Serial Real-Time Clock
HANDLING, PC BOARD LAYOUT, AND ASSEMBLY
The DS1337C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but
precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning should be avoided
to prevent damage to the crystal.
Avoid running signal traces under the package, unless a ground plane is placed between the package and the
signal line. All N.C. (no connect) pins must be connected to ground.
Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package
label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for
moisture-sensi tive device (MSD) classifications.
PIN CONFIGURATIONS
CHIP INFORMATION
TRANSISTOR COUNT: 10,950
PROCESS: CMOS
THERMAL INFORMATION
PACKAGE THETA-JA
(°C/W) THETA-JC
(°C/W)
8 DIP
110
40
8 SO
170
40
8 μSOP
229
39
16 SO
73
23
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
8 PDIP P8+8
21-0043
8 SO S8+2
21-0041
8 µMAX U8+1
21-0036
16 SO W16-H2
21-0042
TOP VIEW
DIP
INTA
X1
X2
GND
VCC
SCL
SDA
SQW/INTB
DS1337
SO, µSOP
X1
X2
GND
VCC
SCL
SDA
SQW/INTB
INTA
DS1337
SQW/INTB
SCL
SDA
GND
INTA
VCC
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DS1337C
SO (300 mils)
15 of 16
DS1337 I2C Serial Real-Time Clock
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
080508
Added device access details to General Description section.
1
Removed leaded ordering numbers from the Ordering Information table.
1
Added Note 5 to Timekeeping VCC EC table range.
2
Added “Full Operation” and “Timekeeping” to headers to clarify table usage. 2
Added OSF parameter to EC table.
3
Updated Pin Description to indicate max input voltage and that unused outputs
may be left open.
5
Added oscillator circuit and show open-drain transistors on Block Diagram.
6
Added Op erat ing Mod e section with details on operating mode and
corresponding Icc parameter. 7
Added I
2
C Interface section explaining how to synchronize a microcontroller and
the RTC. 8
Corrected legend in figure 5 for not-acknowledge (add overbar to symbol).
14
071609
Removed conflicting SDA/SCL input bias statement in Pin Description.
5
042315
Revised Benefits and Features section
1
16 of 16
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 160 Rio Robles, San Jose, CA 95134 408-601-1000
© 2015 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc.