Vishay Siliconix
DG417B, DG418B, DG419B
Document Number: 72107
S09-1261-Rev. D, 13-Jul-09
www.vishay.com
1
Precision Monolithic Quad SPST CMOS Analog Switches
DESCRIPTION
The DG417B, DG418B, DG419B monolithic CMOS analog
switches were designed to provide high performance
switching of analog signals. Combining low power, low
leakages, high speed, low on-resistance and small physical
size, the DG417B series is ideally suited for portable and
battery powered industrial and military applications requiring
high performance and efficient use of board space.
To achieve high-voltage ratings and superior switching
performance, the DG417B series is built on Vishay
Siliconix’s high voltage silicon gate (HVSG) process. Break-
before-make is guaranteed for the DG419B, which is an
SPDT configuration. An epitaxial layer prevents latchup.
Each switch conducts equally well in both directions when
on, and blocks up to the power supply level when off.
The DG417B and DG418B respond to opposite control logic
levels as shown in the Truth Table.
FEATURES
• ± 15 V analog signal range
• On-resistance - RDS(on): 15 Ω
• Fast switching action - tON: 110 ns
• TTL and CMOS compatible
• MSOP-8 and SOIC-8 package
• Compliant to RoHS directive 2002/95/EC
BENEFITS
• Widest dynamic range
• Low signal errors and distortion
• Break-before-make switching action
• Simple interfacing
• Reduced board space
• Improved reliability
APPLICATIONS
• Precision test equipment
• Precision instrumentation
• Battery powered systems
• Sample-and-hold circuits
• Military radios
• Guidance and control systems
• Hard disk drivers
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Logic "0" ≤ 0.8 V
Logic "1" ≥ 2.4 V
Logic "0" ≤ 0.8 V
Logic "1" ≥ 2.4 V
* Pb containing terminations are not RoHS compliant, exemptions may apply
1
Dual-In-Line, SOIC-8 and MSOP-8
S D
V-
GND IN
V+V
L
2
3
4
8
7
6
5
To
p
View
D
G
417B
No connect TRUTH TABLE
Logic DG417B DG418B
0 ON OFF
1OFFON
1
Dual-In-Line, SOIC-8 and MSOP-8
DS
2
S1V-
GNDIN
V+VL
2
3
4
8
7
6
5
Top View
DG419B
TRUTH TABLE - DG419B
Logic SW1SW2
0 ON OFF
1OFFON
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Document Number: 72107
S09-1261-Rev. D, 13-Jul-09
Vishay Siliconix
DG417B, DG418B, DG419B
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC board.
c. Derate 5.3 mW/°C above 75 °C.
d. Derate 4 mW/°C above 70 °C.
e. Derate 8 mW/°C above 75 °C.
ORDERING INFORMATION
Temp Range Package Part Number
DG417B, DG418B
- 40 °C to 85 °C
8-Pin Plastic MiniDIP
DG417BDJ
DG417BDJ-E3
DG418BDJ
DG418BDJ-E3
8-Pin Narrow SOIC
DG417BDY
DG417BDY-E3
DG417BDY-T1
DG417BDY-T1-E3
DG418BDY
DG418BDY-E3
DG418BDY-T1
DG418BDY-T1-E3
8-Pin MSOP DG417BDQ-T1-E3
DG418BDQ-T1-E3
DG419B
- 40 °C to 85 °C
8-Pin Plastic MiniDIP DG419BDJ
DG419BDJ-E3
8-Pin Narrow SOIC
DG419BDY
DG419BDY-E3
DG419BDY-T1
DG419BDY-T1-E3
8-Pin MSOP DG419BDQ-T1-E3
ABSOLUTE MAXIMUM RATINGS
Parameter Limit Unit
V- - 20
V
V+ 20
GND 25
VL(GND - 0.3) to (V+) + 0.3
Digital Inputsa, VS, VD
(V-) - 2 V to (V+) + 2
or 30 mA, whichever occurs first
Current, (Any Terminal) Continuous 30 mA
Current (S or D) Pulsed at 1 ms, 10 % Duty Cycle 100
Storage Temperature - 65 to 150 °C
Power Dissipation (Package)b
8-Pin Plastic MiniDIPc400
mW
8-Pin Narrow SOICc400
8-Pin MSOPd400
8-Pin CerDIPe600
Document Number: 72107
S09-1261-Rev. D, 13-Jul-09
www.vishay.com
3
Vishay Siliconix
DG417B, DG418B, DG419B
SCHEMATIC DIAGRAM Typical Channel
Figure 1.
Level
Shift/
Drive
V
IN
V
L
S
V+
GND
V -
D
V -
V+
SPECIFICATIONSa
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 15 V
VL = 5 V, VIN = 2.4 V, 0.8 VfTemp.b Typ.c
A Suffix
- 55 °C to 125 °C
D Suffix
- 40 °C to 85 °C
Unit Min.d Max.dMin.d Max.d
Analog Switch
Analog Signal RangeeVANALOG Full - 15 15 - 15 15 V
Drain-Source
On-Resistance RDS(on)
IS = - 10 mA, VD = ± 12.5 V
V+ = 13.5 V, V- = - 13.5 V
Room
Full 15 25
34
25
29 Ω
Switch Off Leakage Current
IS(off)
V+ = 16.5, V- = - 16.5 V
VD = ± 15.5 V, VS = ± 15.5 V
Room
Full - 0.1 - 0.25
- 20
0.25
20
- 0.25
- 5
0.25
5
nA
ID(off)
DG417B
DG418B
Room
Full - 0.1 - 0.25
- 20
0.25
20
- 0.25
- 5
0.25
5
DG419B Room
Full - 0.1 - 0.75
- 60
0.75
60
- 0.75
- 12
0.75
12
Channel On Leakage Current ID(on) V+ = 16.5 V, V- = - 16.5 V
VS = VD = ± 15.5 V
DG417B
DG418B
Room
Full - 0.4 - 0.4
- 40
0.4
40
- 0.4
- 10
0.4
10
DG419B Room
Full - 0.4 - 0.75
- 60
0.75
60
- 0.75
- 12
0.75
12
Digital Control
Input Current, VIN Low IIL Full - 0.5 0.5 - 0.5 0.5 µA
Input Current, VIN High IIH Full - 0.5 0.5 - 0.5 0.5
Dynamic Characteristics
Tu r n - On T im e t ON RL = 300 Ω, CL = 35 pF
VS = ± 10 V, See Switching
Time Test Circuit
DG417B
DG418B
Room
Full 62 89
106
89
99
ns
Turn-Off Time tOFF
DG417B
DG418B
Room
Full 53 80
88
80
86
Transition Time tTRANS
RL = 300 Ω, CL = 35 pF
VS1 = ± 10 V, VS2 = ± 10 V DG419B Room
Full 60 87
96
87
93
Break-Before-Make
Time Delay tD
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = ± 10 V DG419B Room 16 3 3
Charge Injection Q CL = 10 nF
Vgen = 0 V, Rgen = 0 ΩRoom 38 pC
Off IsolationeOIRR RL = 50 Ω, CL = 5 pF,
f = 1 MHz Room - 82
dB
Channel-to-Channel
CrosstalkeXTALK DG419B Room - 88
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Document Number: 72107
S09-1261-Rev. D, 13-Jul-09
Vishay Siliconix
DG417B, DG418B, DG419B
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
Stresses beyond those listed under “Absolut e Maximum Ratings” may cause permanent damage to t he device. These are stress rating s only, and functiona l operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 15 V
VL = 5 V, VIN = 2.4 V, 0.8 VfTemp.b Typ.c
A Suffix
- 55 °C to 125 °C
D Suffix
- 40 °C to 85 °C
Unit Min.d Max.dMin.d Maxd.
Dynamic Characteristics
Source Off CapacitanceeCS(off)
f = 1 MHz, VS = 0 V
Room 12
pF
Drain Off CapacitanceeCD(off)
DG417B
DG418B Room 12
Channel On Capacitancee
CD(on)
f = 1 MHz, VS = 0 V
DG417B
DG418B Room 50
DG419B Room 57
Power Supplies
Positive Supply Current I+
V+ = 16.5 V, V- = - 16.5 V
VIN = 0 or 5 V
Room
Full
0.001 1
5
1
5
µA
Negative Supply Current I- Room
Full
- 0.001 - 1
- 5
- 1
- 5
Logic Supply Current IL
Room
Full
0.001 1
5
1
5
Ground Current IGND
Room
Full
- 0.001 - 1
- 5
- 1
- 5
SPECIFICATIONSa
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 12 V, V- = 0 V
VL = 5 V, VIN = 2.4 V, 0.8 VfTemp.b Typ.c
A Suffix
- 55 °C to 125 °C
D Suffix
- 40 °C to 85 °C
Unit Min.d Max.dMin.d Max.d
Analog Switch
Analog Signal RangeeVANALOG Full 0 12 0 12 V
Drain-Source
On-Resistance RDS(on)
IS = - 10 mA, VD = 3.8 V
V+ = 10.8 V
Room
Full 26 35
52
35
45 Ω
Dynamic Characteristics
Tur n -On T i m e tON RL = 300 Ω, CL = 35 pF
VS = 8 V, See Switching
Time Test Circuit
Room
Full 100 125
155
125
143
ns
Turn-Off Time tOFF
Room
Full 38 66
73
66
69
Break-Before-Make
Time Delay tDRL = 300 Ω, CL = 35 pF DG419B Room 62 25 25
Transition Time tTRANS
RL = 300 Ω, CL = 35 pF
VS1 = 0 V, 8 V, VS2 = 8 V, 0 V
Room
Full 95 119
153
119
141
Charge Injection Q CL = 10 nF, Vgen = 0 V, Rgen = 0 Ω Room 18 pC
Power Supplies
Positive Supply Current I+
V+ = 13.2 V, VL = 5.25 V
VIN = 0 or 5 V
Room
Full 0.001 1
5
1
5
µA
Negative Supply Current I- Room - 0.001 - 1
- 5
- 1
- 5
Logic Supply Current ILRoom 0.001 1
5
1
5
Ground Current IGND Room - 0.001 - 1
- 5
-1
- 5
SPECIFICATIONSa
Document Number: 72107
S09-1261-Rev. D, 13-Jul-09
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5
Vishay Siliconix
DG417B, DG418B, DG419B
TYPICAL CHARACTERISTICS TA = 25 °C, unless otherwise noted
On-Resistance vs. V
D
and Unipolar Power Supply Voltage
On-Resistance vs. VD and Temperature
Leakage vs. Analog Voltage
0
50
100
150
200
250
300
04812 16 20
V+ = 3 V
V
L
= 3 V
V+ = 5 V
TA = 25 °C
VL = 5 V
RDS(on) - (Ω) e c n a t s i s e R - n O e c r u o S - n i a r D
V
D
- Drain Voltage (V)
V+ = 8 V
V+ = 12 V
V+ = 15 V
V+ = 20 V
5
10
15
20
25
30
- 15 - 10 - 5 0 5 10 15
- 55 °C
V ± = ± 15 V
V
L
= 5 V
25 °C
85 °C
RDS(on) - (Ω) e c n a t s i s e R - n O
e
c r u o S
-
n
i
a
r D
V
D
- Drain Voltage (V)
125 °C
- 100
- 80
- 60
- 40
- 20
0
20
40
60
80
100
-15 - 10 - 5 0 5 10 15
V
D
or V
S
- Drain or Source Voltage (V)
V ± = ± 15 V
V
L
= 5 V
T
A
= 25 °C
I
D I
, S
)
A
p
(
IS(off)
ID(off) ID(on)
On-Resistance vs. VD and Dual Supply Voltage
On-Resistance vs. VD and Temperature
Supply Current vs. Input Switching Frequency
5
10
15
20
25
30
35
40
- 20 - 15 - 10 - 5 0 5 10 15 20
e (Ω)c n a t s i s e R - n O e c r u o S - n i a r RDS(on) - D
V
D
- Drain Voltage (V)
T
A
= 25 °C
± 5 V
± 8 V
± 10 V
± 15 V
± 20 V
± 12 V
5
10
15
20
25
30
35
40
45
5
0
0246810 12
- 55 °C
25 °C
85 °C
RDS(on) - (Ω) e c n a t s i s e R - n O
e
c r u o S - n i
a
r D
V
D
- Drain Voltage (V)
125 °C
V+ = 12 V
V- = 0 V
V
L
= 5 V
Input Switchin
g
Frequency (Hz)
10 100 1 K 10 K 100 K 1 M 10 M
100 p
10 n
100 n
1 m
100 m
1 µ
10 µ
100 µ
) A n (
t n e
r r u C
y l
p p u S
+ -
I
10 m
1 n
V ± = ± 15 V
V
L
= 5 V
I
L
I+, I-
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Document Number: 72107
S09-1261-Rev. D, 13-Jul-09
Vishay Siliconix
DG417B, DG418B, DG419B
TYPICAL CHARACTERISTICS TA = 25 °C, unless otherwise noted
Switching Time vs. Temperature
Transition Time vs. Temperature
Switching Threshold vs. Supply Voltage
)
s n
(
20
40
60
80
100
120
140
- 55 - 35 - 15 5 25 45 65 85 105 125
t N O t , F F O
Temperature ( C)
tOFF V = 12 V
tON V = ± 15 V
tON V = 12 V
VL = 5 V
tOFF V = ± 15 V
20
40
60
80
100
120
- 55 - 35 - 15 5 25 45 65 85 105 125
Tem
erature
C
s
n
t N O t
, F
F
O
V+ = 12 V
V- = 0 V
V
L
= 5 V
t
TRANS+
tTRANS-
0.0
0.5
1.0
1.5
2.0
2.5
3
.
0
46810 12 14 16 1820
) V ( d l o h s e r h T g n i h c t
i
w S
V+ - Supply Voltage (V)
V
T -
V
L
= 5 V
Transition Time vs. Temperature
Insertion Loss, Off -Isolation Crosstalk vs. Frequency
Insertion Loss, Off -Isolation Crosstalk vs. Frequency
20
30
40
50
60
70
80
90
100
- 55 - 35 - 15 5 25 45 65 85 105 125
Tem
p
erature
(
C
)
t
TRANS-
V ± = ± 15 V
V
L
= 5 V
tTRANS+
)
s n
(
t
N O
t ,
F F O
K L A
T
Frequency (Hz)
) B d ( X
, R
R
I
O
,
s s o
L
- 100
- 90
- 80
- 70
- 60
- 50
- 40
- 30
- 20
- 10
0
10
100K 1M 10M 100M 1G
OIRR
Loss
DG417B
V+ = + 15 V
V- = - 15 V
RL = 50 Ω
K
L A T
Frequency (Hz)
) B d ( X , R R I
O
,
s s
o
L
- 100
- 90
- 80
- 70
- 60
- 50
- 40
- 30
- 20
- 10
0
10
100K 1M 10M 100M 1G
Loss
XTALK
DG419B
V+ = + 15 V
V- = - 15 V
RL = 50 Ω
OIRR
Document Number: 72107
S09-1261-Rev. D, 13-Jul-09
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7
Vishay Siliconix
DG417B, DG418B, DG419B
TYPICAL CHARACTERISTICS TA = 25 °C, unless otherwise noted
TEST CIRCUITS
Charge Injection vs. Analog Voltage
(Measured at drain pin)
Charge Injection vs. Analog Voltage
(Measured at drain pin)
Analog Voltage (V)
Qinj - Charge Injection (pC)
- 100
- 80
- 60
- 40
- 20
0
20
40
60
80
100
120
140
160
180
200
- 15 - 12 - 9 - 6 - 3 0 3 6 9 12 15
V+ = + 12 V
V- = 0 V
V+ = + 12 V
V- = - 12 V
V+ = + 15 V
V- = - 15 V
DG417B
CL=10nF
Analog Voltage (V)
Qinj - Charge Injection (pC)
- 200
- 180
- 160
- 140
- 120
- 100
- 80
- 60
- 40
- 20
0
20
40
60
80
100
- 15 - 12 - 9 - 6 - 3 0 3 6 9 12 15
V+=+12V
V-=-0V
DG419B
CL=10nF
V+=+15V
V-=-15V
V+=+12V
V-=-12V
Charge Injection vs. Analog Voltage
(Measured at source pin)
Charge Injection vs. Analog Voltage
(Measured at source pin)
Qinj - Charge Injection (pC)
V+ = + 15 V
V- = - 15 V
V+ = + 12 V
V- = 0 V
V+ = + 12 V
V- = - 12 V
DG417B
CL=10nF
- 100
- 80
- 60
- 40
- 20
0
20
40
60
80
100
120
140
160
180
200
- 15 - 12 - 9 - 6 - 3 0 3 6 9 12 15
Analog Voltage (V)
Analog Voltage (V)
Qinj - Charge Injection (pC)
- 100
- 80
- 60
- 40
- 20
0
20
40
60
80
100
120
140
160
180
200
- 15 - 12 - 9 - 6 - 3 0 3 6 9 12 15
V+=+12V
V-=-0V
DG419B
CL=10nF
V+=+15V
V-=-15V
V+=+12V
V-=-12V
Figure 2. Switching Time (DG417B/418B)
CL (includes fixture and stray capacitance)
RL
RL + RDS(on)
VO = VS
V-
IN
S D
C
L
35 pF
- 15 V
V
L
GND
V
O
10 V
V+
R
L
300
+ 15 V + 5 V
VO is the steady state output with the switch on.
0 V
Logic
Input
Switch
Input
Switch
Output
3 V
50 %
0 V
V
O
V
S
t
r
< 5 ns
t
f
< 5 ns
t
OFF
t
ON
90 %
Note: Logic input waveform is inverted for switches that have the
opposite logic sense.
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8
Document Number: 72107
S09-1261-Rev. D, 13-Jul-09
Vishay Siliconix
DG417B, DG418B, DG419B
TEST CIRCUITS
Figure 3. Break-Before-Make (DG419B)
IN
V
L
V
S1
D
V -
V
S2
S
2
V+
S
1
- 15 V
GND
+ 1 V+ 5 V
C
L
35 pF
V
O
R
L
300
C
L
(includes fixture and stray capacitance)
0 V
3 V
0 V
Logic
Input
Switch
Output
V
O
V
S1
= V
S2
t
r
< 5 ns
t
f
< 5 ns
90 %
t
D
t
D
Figure 4. Transition Time (DG419B)
CL (includes fixture and stray capacitance)
VL
RL
RL + rDS(on)
VO = VS
V -
V+
IN
CL
35 pF
RL
300
D
VO
S2
S1
VS2
VS1
- 15 V
GND
+ 15 V+ 5 V
0 V
3 V
50 %
Logic
Input
Switch
Output
VS1
tr < 5 ns
tf < 5 ns
10 %
tTRANS
90 %
V01
VS2
V02
tTRANS
Figure 5. Charge Injection
CL
10 nF
D
Rg
VO
V+
S
V -
3 V
IN
VL
- 15 V
GND
+ 15 V+ 5 V
OFFONOFF
VO
VO
INX
Q = VO x CL
Document Number: 72107
S09-1261-Rev. D, 13-Jul-09
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9
Vishay Siliconix
DG417B, DG418B, DG419B
TEST CIRCUITS
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72107.
Figure 6. Crosstalk
Rg = 50
IN
0.8 V
VLV+
V -
XTALK Isolation = 20 log
VO
VS
GND
S2
VS
VO
S1
RL
D
C = RF bypass
50
+ 15 V
- 15 V
C
C
+ 5 V
C
Figure 7. Off isolation
V+
S
VL
Rg = 50
D
- 15 V
VS
GNDV - C
RL
IN
VO
0 V, 2.4 V
Off Isolation = 20 log
VO
VS
+ 5 V
C
+ 15 V
C
Figure 8. Insertion Loss
S
VSVO
0 V, 2.4 VINRL
VL
D
Rg = 50
+ 5 V
- 15 V
GNDV-C
C
+ 15 V
V+
C
Figure 9. Source/Drain Capacitances
VL
IN
S
V+
D
f = 1 MHz
C
0 V, 2.4 V
Meter
HP4192A
Impedance
Analyzer
or Equivalent
+ 5
V
C
+ 15
V
C
D2D1
S1
f = 1 MHz
+ 15 V
IN
S2
NC
- 15 V
GND
V+
C
C
0 V, 2.4 V
Meter
HP4192A
Impedance
Analyzer
or Equivalent
DG417B/418B
DG419B
f = 1 MHz
- 15 V
GNDV- V-
Vishay Siliconix
Package Information
Document Number: 71192
11-Sep-06
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1
DIM
MILLIMETERS INCHES
Min Max Min Max
A 1.35 1.75 0.053 0.069
A10.10 0.20 0.004 0.008
B 0.35 0.51 0.014 0.020
C 0.19 0.25 0.0075 0.010
D 4.80 5.00 0.189 0.196
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.50 0.93 0.020 0.037
q0°8°0°8°
S 0.44 0.64 0.018 0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
4
3
12
5
6
87
HE
h x 45
C
All Leads
q0.101 mm
0.004"
L
BA
1
A
e
D
0.25 mm (Gage Plane)
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
S
NOTES:
1. Die thickness allowable is 0.203"0.0127.
2. Dimensioning and tolerances per ANSI.Y14.5M-1994.
3. Dimensions “D” and “E1” do not include mold flash or protrusions, and are
measured at Datum plane -H- , mold flash or protrusions shall not exceed
0.15 mm per side.
4. Dimension is the length of terminal for soldering to a substrate.
5. Terminal positions are shown for reference only .
6. Formed leads shall be planar with respect to one another within 0.10 mm at
seating plane.
7. The lead width dimension does not include Dambar protrusion. Allowable
Dambar protrusion shall be 0.08 mm total in excess of the lead width
dimension at maximum material condition. Dambar cannot be located on the
lower radius or the lead foot. Minimum space between protrusions and an
adjacent lead to be 0.14 mm. See detail “B” and Section “C-C”.
8. Section “C-C” to be determined at 0.10 mm to 0.25 mm from the lead tip.
9. Controlling dimension: millimeters.
10. This part is compliant with JEDEC registration MO-187, variation AA and BA.
11. Datums -A- and -B- to be determined Datum plane -H- .
12. Exposed pad area in bottom side is the same as teh leadframe pad size.
5
N N-1 A B C 0.20
(N/2) Tips)
2X
N/221
0.60
0.50
0.60
E
Top View
e
See Detail “B”
-H-
3
D-A-
Seating Plane
A1
A
6
C0.10
Side View
0.25
BSC
T4
L-C-
Seating Plane
0.07 R. Min
2 Places
Parting Line
Detail “A”
(Scale: 30/1)
0.48 Max
Detail “B”
(Scale: 30/1)
Dambar Protrusion
7
C0.08 MBSAS
b
b1
With Plating
Base Metal
c1c
Section “C-C”
Scale: 100/1
(See Note 8)
See Detail “A”
A20.05 S
C
C
ς
3
E1-B-
End View
e1
0.95
Package Information
Vishay Siliconix
Document Number: 71244
12-Jul-02 www.vishay.com
1
MSOP: 8−LEADS
JEDEC Part Number: MO-187, (Variation AA and BA)
N = 8L
MILLIMETERS
Dim Min Nom Max Note
A- - 1.10
A10.05 0.10 0.15
A20.75 0.85 0.95
b0.25 - 0.38 8
b10.25 0.30 0.33 8
c0.13 - 0.23
c10.13 0.15 0.18
D3.00 BS C 3
E4.90 BSC
E12.90 3.00 3.10 3
e0.65 BSC
e11.95 BSC
L0.40 0.55 0.70 4
N8 5
T0_4_6_
ECN: T-02080—Rev. C, 15-Jul-02
DWG: 5867
Q1
A
L
A1
B
E1E
e1
B1
S
CeA
D
15°
MAX
1234
8765
NOTE: End leads may be half leads.
Package Information
Vishay Siliconix
Document Number: 71259
05-Jul-01 www.vishay.com
1
PDIP: 8ĆLEAD
MILLIMETERS INCHES
Dim Min Max Min Max
A3.81 5.08 0.150 0.200
A10.38 1.27 0.015 0.050
B0.38 0.51 0.015 0.020
B10.89 1.65 0.035 0.065
C0.20 0.30 0.008 0.012
D9.02 10.92 0.355 0.430
E7.62 8.26 0.300 0.325
E15.59 7.11 0.220 0.280
e12.29 2.79 0.090 0.110
eA7.37 7.87 0.290 0.310
L2.79 3.81 0.110 0.150
Q11.27 2.03 0.050 0.080
S0.76 1.65 0.030 0.065
ECN: S-03946—Rev. E, 09-Jul-01
DWG: 5478
E1E
Q1
A
L
A1
e1
BB1
L1
S
C
eA∝
D
1234
8765
Package Information
Vishay Siliconix
Document Number: 71280
03-Jul-01 www.vishay.com
1
CERDIP: 8ĆLEAD
MILLIMETERS INCHES
Dim Min Max Min Max
A4.06 5.08 0.160 0.200
A10.51 1.14 0.020 0.045
B0.38 0.51 0.015 0.020
B11.14 1.65 0.045 0.065
C0.20 0.30 0.008 0.012
D9.40 10.16 0.370 0.400
E7.62 8.26 0.300 0.325
E16.60 7.62 0.260 0.300
e12.54 BS C 0.100 BSC
eA7.62 BSC 0.300 BSC
L3.18 3.81 0.125 0.150
L13.18 5.08 0.150 0.200
Q11.27 2.16 0.050 0.085
S0.64 1.52 0.025 0.060
∝0°15°0°15°
ECN: S-03946—Rev. C, 09-Jul-01
DWG: 5348
VISHAY SILICONIX
TrenchFET® Power MOSFETs Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
APPLICATION NOTE
Document Number: 70740 www.vishay.com
Revision: 18-Jun-07 1
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a s ingle MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providin g the thermal connect ion
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
Figure 1. Single M O SFET SO-8 Pad
Pattern With Copper Spreading
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Cop per S preading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footpri nt with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
0.027
0.69
0.078
1.98
0.2
5.07
0.196
5.0
0.288
7.3
0.050
1.27
0.027
0.69
0.078
1.98
0.2
5.07
0.088
2.25
0.288
7.3
0.050
1.27
0.088
2.25
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72606
22 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SO-8
0.246
(6.248)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.172
(4.369)
0.152
(3.861)
0.047
(1.194)
0.028
(0.711)
0.050
(1.270)
0.022
(0.559)
Return to Index
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Revision: 12-Mar-12 1Document Number: 91000
Disclaimer
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