LM5067MMX-1 - Texas Instruments High-Performance Analog

LM5067

LM5067 Negative Hot Swap / Inrush Current Controller with Power Limiting

Literature Number: SNVS532B

LM5067

September 9, 2009

Negative Hot Swap / Inrush Current Controller with Power

Limiting

General Description

The LM5067 negative hot swap controller provides intelligent

control of the power supply connections during insertion and

removal of circuit cards from a live system backplane or other

“hot” power sources. The LM5067 provides in-rush current

control to limit system voltage droop and transients. The cur-

rent limit and power dissipation in the external series pass N-

Channel MOSFET are programmable, ensuring operation

within the Safe Operating Area (SOA). In addition, the

LM5067 provides circuit protection by monitoring for over-

current and over-voltage conditions. The POWER GOOD

output indicates when the output voltage is close to the input

voltage. The input under-voltage and over-voltage lockout

levels and hysteresis are programmable, as well as the fault

detection time. The LM5067-1 latches off after a fault detec-

tion, while the LM5067-2 automatically attempts restarts at a

fixed duty cycle. The LM5067 is available in a 10 pin MSOP

package and a 14 pin SOIC package.

Features

■Wide operating range: -9V to -80V

■In-rush current limit for safe board insertion into live power

sources

■Programmable maximum power dissipation in the external

pass device

■Adjustable current limit

■Circuit breaker function for severe over-current events

■Adjustable under-voltage lockout (UVLO) and hysteresis

■Adjustable over-voltage lockout (OVLO) and hysteresis

■Initial insertion timer allows ringing and transients to

subside after system connection

■Programmable fault timer avoids nuisance trips

■Active high open drain POWER GOOD output

■Available in latched fault and automatic restart versions

Applications

■Server Backplane Systems

■In-Rush Current Limiting

■Solid State Circuit Breaker

■Transient Voltage Protector

■Solid State Relay

■Under-voltage Lock-out

■Power Good Detector/Indicator

Package

■MSOP-10

■SO-14 (Latched Fault Version)

Typical Application

30030901

Negative Power Bus In-Rush and Fault Protection

LM5067 Negative Hot Swap / Inrush Current Controller with Power Limiting

Connection Diagrams (Note 7)

30030902

Top View

10-Lead MSOP

30030964

Top View

14-Lead SOIC

Ordering Information

Order Number Fault Response Package Type NSC Package Drawing Supplied As

LM5067MM-1 Latch Off

MSOP-10 MUB10A

1000 Units on Tape and Reel

LM5067MMX-1 Latch Off 3500 Units on Tape and Reel

LM5067MM-2 Auto Restart 1000 Units on Tape and Reel

LM5067MMX-2 Auto Restart 3500 Units on Tape and Reel

LM5067MW-1 Latch Off SO-14 M14B 50 Units per Rail

LM5067MWX-1 Latch Off 1000 Units on Tape and Reel

Pin Descriptions

Pin # Name Description Applications Information

MSOP-10 SO-14

1 1 VCC Positive supply

input

Connect to system ground through a resistor. Connect a bypass capacitor

to VEE. The voltage from VCC to VEE is nominally 13V set by an internal

zener diode.

2 3 UVLO/EN Under-voltage

lockout

An external resistor divider from the system input voltage sets the under-

voltage turn-on threshold. The enable threshold at the pin is 2.5V above

VEE. An internal 22 µA current source provides hysteresis. This pin can be

used for remote enable and disable.

3 4 OVLO Over-voltage

lockout

An external resistor divider from the system input voltage sets the over-

voltage turn-off threshold. The disable threshold at the pin is 2.5V above

VEE. An internal 22 µA current source provides hysteresis.

4 5 PWR Power limit set An external resistor at this pin, in conjunction with the current sense resistor

(RS), sets the maximum power dissipation in the external series pass

MOSFET.

5 6 VEE Negative supply

input

Connect to the system negative supply voltage (typically -48V).

6 8 TIMER Timing capacitor An external capacitor at this pin sets the insertion time delay and the fault

timeout period. The capacitor also sets the restart timing of the LM5067-2.

7 9 SENSE Current sense

input

The voltage across the current sense resistor (RS) is measured from VEE

to this pin. If the voltage across RS reaches 50 mV the load current is limited

and the fault timer activates.

8 10 GATE Gate drive output Connect to the external N-channel MOSFET’s gate.

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LM5067

Pin # Name Description Applications Information

MSOP-10 SO-14

9 12 OUT Output feedback Connect to the external MOSFET’s drain. Internally used to determine the

MOSFET VDS voltage for power limiting, and to control the PGD output pin.

10 14 PGD Power Good

indicator

An open drain output capable of sustaining 80V when off. When the external

MOSFET VDS decreases below 1.23V the PGD pin switches high. When

the external MOSFET VDS increases above ≊2.5V the PGD pin switches

low.

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LM5067

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Current into VCC (100 µs pulse) 100 mA

OUT, PGD to VEE -0.3V to 100V

UVLO, OVLO to VEE -0.3V to 17V

SENSE to VEE -0.3V to +0.3V

ESD Rating (Note 2)

Human Body Model

2kV

Storage Temperature -65°C to +150°C

Junction Temperature +150°C

Operating Ratings

Current into VCC (Note 5) 2 mA (min)

OUT Voltage above VEE 0V to 80V

PGD Off Voltage above VEE 0V to 80V

Junction Temperature −40°C to +125°C

Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the

junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical

correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.

Unless otherwise stated the following conditions apply: ICC = 2 mA, OUT Pin = 48V above VEE, all voltages are with respect to

VEE. See (Note 3).

Symbol Parameter Conditions Min Typ Max Units

Input

VZOperating voltage, VCC – VEE ICC = 2 mA, UVLO = 5V 12.35 13 13.65 V

ICC-EN Internal operating current, enabled VCC-VEE = 11V,

UVLO = 5V

0.8 1mA

ICC-DIS Internal operating current, disabled VCC-VEE = 11V,

UVLO = 2V

480 660 µA

PORIT Threshold voltage to start insertion timer VCC-VEE increasing 7.7 8.2 V

POREN Threshold voltage to enable all functions VCC-VEE increasing 8.4 8.7 V

POREN-HYS POREN hysteresis VCC-VEE decreasing 125 mV

OUT Pin

IOUT-EN OUT bias current, enabled OUT = VEE, Normal operation 0.1 µA

IOUT-DIS OUT bias current, disabled Disabled, OUT = VEE + 48V 50

SENSE Pin

ISNS-EN SENSE bias current, enabled OUT = VEE, Normal operation -6 µA

ISNS-DIS SENSE bias current, disabled Disabled, OUT = VEE + 48V -50

UVLO, OVLO Pins

UVLOTH UVLO threshold 2.45 2.5 2.55 V

UVLOHYS UVLO hysteresis current UVLO = VEE + 2V 10 22 34 µA

UVLODEL UVLO delay Delay to GATE high 26 µs

Delay to GATE low 12 µs

UVLOBIAS UVLO bias current UVLO = VEE + 5V 1µA

OVLOTH OVLO threshold 2.43 2.5 2.57 V

OVLOHYS OVLO hysteresis current OVLO = VEE+2.8V -34 -22 -10 µA

OVLODEL OVLO delay Delay to GATE high 26 µs

Delay to GATE low 12 µs

OVLOBIAS OVLO bias current OVLO = VEE + 2.4V 1µA

Gate Control (GATE Pin)

IGATE Source current Normal Operation -72 -52 -32 µA

Sink current UVLO < 2.5V 1.9 2.2 2.68 mA

SENSE - VEE =150 mV or

VCC - VEE < PORIT, VGATE = 5V

45 110 200

VGATE Gate output voltage in normal operation GATE-VEE voltage VZ V

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LM5067

Symbol Parameter Conditions Min Typ Max Units

Current Limit

VCL Threshold voltage SENSE - VEE voltage 44 50 56 mV

tCL Response time SENSE - VEE stepped from 0 mV

to 80 mV

25 µs

Circuit Breaker

VCB Threshold voltage SENSE - VEE voltage 70 100 130 mV

tCB Response time SENSE - VEE stepped from 0 mV

to 150 mV, time to GATE low, no

load

0.65 1.0 µs

Power Limit (PWR Pin)

PWRLIM Power limit sense voltage (SENSE - VEE) OUT - SENSE = 24V, RPWR = 75

kΩ

16.5 22 27.5 mV

IPWR PWR pin current VPWR = 2.5V -23 µA

Timer (TIMER Pin)

VTMRH Upper threshold 3.76 44.16 V

VTMRL Lower threshold Restart cycles (LM5067-2) 1.18 1.25 1.32 V

End of 8th cycle (LM5067-2) 0.3 V

Re-enable threshold (LM5067-1) 0.3 V

ITIMER Insertion time current TIMER pin = 2V -9.5 -6 -2.5 µA

Sink current, end of insertion time TIMER pin = 2V 1.2 1.55 1.9 mA

Fault detection current TIMER pin = 2V -140 -85 -44 µA

Sink current, end of fault time 0.9 2.5 4.25 µA

DCFAULT Fault Restart Duty Cycle LM5067-2 0.5 %

tFAULT Fault to GATE low delay TIMER pin reaches 4.0V 15 µs

Power Good (PGD Pin)

PGDTH Threshold measured at OUT - SENSE Decreasing 1.162 1.23 1.285 V

Increasing, relative to decreasing

threshold

1.143 1.25 1.325

PGDVOL Output low voltage ISINK = 2 mA 60 150 mV

PGDIOH Off leakage current VPGD = 80V 5µA

Thermal Resistance (Note 6)

θJA Junction to Ambient MSOP package 94 °C/W

θJC Junction to Case MSOP package 44 °C/W

θJA Junction to Ambient SO-14 Package 90 °C/W

θJC Junction to Case SO-14 Package 27 °C/W

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and conditions see the Electrical Characteristics.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.

Note 3: Current out of a pin is indicated as a negative value.

Note 4: For detailed information on soldering plastic MSOP package refer to the Packaging Databook available from National Semiconductor Corporation.

Note 5: Maximum continuous current into VCC is limited by power dissipation and die temperature. See the Thermal Considerations section.

Note 6: Tested on a 4 layer JEDEC board with 2 vias under the package. See JEDEC standards JESD51-7 and JESD51-3. See the Thermal Considerations

section.

Note 7: N/C Pins are internally not connected to anything.

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LM5067

Typical Performance Characteristics Unless otherwise specified the following conditions

apply: TJ = 25°C.

ICC vs. Operating Voltage - Disabled

30030904

ICC vs. Operating Voltage - Enabled

30030905

Operating Voltage vs. ICC

30030906

SENSE Pin Current vs. System Voltage

30030907

OUT Pin Current vs. System Voltage

30030908

GATE Source Current vs. Operating Voltage

30030909

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LM5067

GATE Pull-Down Current, Circuit Breaker vs. GATE Voltage

30030910

PGD Low Voltage vs. Sink Current

30030911

MOSFET Power Dissipation Limit vs. RPWR and RS

30030912

UVLO & OVLO Hysteresis Current vs. Temperature

30030913

UVLO, OVLO Threshold Voltage vs. Temperature

30030915

VZ Operating Voltage vs. Temperature

30030916

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LM5067

Current Limit Threshold vs. Temperature

30030917

Circuit Breaker Threshold vs. Temperature

30030918

Power Limit Threshold vs. Temperature

30030919

Gate Source Current vs. Temperature

30030920

GATE Pull-Down Current, Circuit Breaker vs. Temperature

30030921

PGD Pin Low Voltage vs. Temperature

30030922

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LM5067

POREN Threshold vs. Temperature

30030923

TIMER Pin Thresholds vs. Temperature

30030925

TIMER Pin Fault Detection Current vs. Temperature

30030926

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LM5067

Block Diagram

30030927

30030928

FIGURE 1. Basic Application Circuit

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LM5067

Functional Description

The LM5067 is designed to control the in-rush current to the

load upon insertion of a circuit card into a live backplane or

other “hot” power source, thereby limiting the voltage sag on

the backplane’s supply voltage, and the dV/dt of the voltage

applied to the load. Effects on other circuits in the system are

minimized, preventing possible unintended resets. During the

system power up, the maximum power dissipation in the se-

ries pass device is limited to a safe value within the device’s

Safe Operating Area (SOA). After the system power up is

complete, the LM5067 monitors the load for excessive cur-

rents due to a fault or short circuit at the load. Limiting the load

current and/or the power in the external MOSFET for an ex-

tended period of time results in the shutdown of the series

pass MOSFET. After a fault event, the LM5067-1 latches off

until the circuit is re-enabled by external control, while the

LM5067-2 automatically restarts with defined timing. The cir-

cuit breaker function quickly switches off the series pass

device upon detection of a severe over-current condition

caused by, e.g. a short circuit at the load. The Power Good

(PGD) output pin indicates when the output voltage is close

to the normal operating value. Programmable under-voltage

lock-out (UVLO) and over-voltage lock-out (OVLO) circuits

shut down the LM5067 when the system input voltage is out-

side the desired operating range. The typical configuration of

a circuit card with LM5067 hot swap protection is shown in

Figure 2.

30030929

FIGURE 2. LM5067 Application

The LM5067 can be used in a variety of applications, other

than plug-in boards, to monitor for excessive load current,

provide transient protection, and ensuring the voltage to the

load is within preferred limits. The circuit breaker function

protects the system from a sudden short circuit at the load.

Use of the UVLO/EN pin allows the LM5067 to be used as a

solid state relay. The PGD output provides a status indication

of the voltage at the load relative to the input system voltage.

Power Up Sequence

The system voltage range of the LM5067 is -9V to -80V, with

a transient capability to -100V. Referring to the Block Diagram

and Figures 1 and 3, as the system voltage (VSYS) initially

increases from zero, the external N-channel MOSFET (Q1) is

held off by an internal 110 mA pull-down current at the GATE

pin. The strong pull-down current at the GATE pin prevents

an inadvertent turn-on as the MOSFET’s gate-to-drain (Miller)

capacitance is charged. When the operating voltage of the

LM5067 (VCC – VEE) reaches the PORIT threshold (7.7V) the

insertion timer starts. During the insertion time, the capacitor

at the TIMER pin (CT) is charged by a 6 µA current source,

and Q1 is held off by a 2.2 mA pull-down current at the GATE

pin regardless of the system voltage. The insertion time delay

allows ringing and transients at VSYS to settle before Q1 can

be enabled. The insertion time ends when the TIMER pin

voltage reaches 4.0V above VEE, and CT is then quickly dis-

charged by an internal 1.5 mA pull-down current. After the

insertion time, the LM5067 control circuitry is enabled when

the operating voltage reaches the POREN threshold (8.4V).

As VSYS continues to increase, the LM5067 operating voltage

is limited at ≊13V by an internal zener diode. The remainder

of the system voltage is dropped across the input resistor

RIN.

The GATE pin switches on Q1 when VSYS exceeds the UVLO

threshold (UVLO pin >2.5V above VEE). If VSYS exceeds the

UVLO threshold at the end of the insertion time, Q1 is

switched on at that time. The GATE pin sources 52 µA to

charge Q1’s gate capacitance. The maximum gate-to-source

voltage of Q1 is limited by the LM5067’s operating voltage

(VZ) to approximately 13V. During power up, as the voltage

at the OUT pin increases in magnitude with respect to

Ground, the LM5067 monitors Q1’s drain current and power

dissipation. In-rush current limiting and/or power limiting cir-

cuits actively control the current delivered to the load. During

the in-rush limiting interval (t2 in Figure 3) an internal current

source charges CT at the TIMER pin. When the load current

reduces from the limiting value to a value determined by the

load the in-rush limiting interval is complete and CT is dis-

charged. The PGD pin switches high when the voltage at the

OUT pin reaches to within 1.25V of the voltage at the SENSE

pin.

If the TIMER pin voltage reaches 4.0V before in-rush current

limiting or power limiting ceases (during t2), a fault is declared

and Q1 is turned off. See the Fault Timer & Restart section

for a complete description of the fault mode.

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LM5067

30030930

FIGURE 3. Power Up Sequence (Current Limit only)

Operating Voltage

The LM5067 operating voltage is the voltage from VCC to

VEE. The maximum operating voltage is set by an internal

13V zener diode. With the IC connected as shown in Figure

1, the LM5067 controller operates in the voltage range be-

tween VEE and VEE+13V. The remainder of the system

voltage is dropped across the input resistor RIN, which must

be selected to pass at least 2 mA into the LM5067 at the min-

imum system voltage.

Gate Control

The external N-channel MOSFET is turned on when the

GATE pin sources 52 µA to enhance the gate. During normal

operation (t3 in Figure 3) Q1’s gate is held charged to ap-

proximately 13V above VEE, typically within 20 mV of the

voltage at VCC. If the maximum VGS rating of Q1 is less than

13V, a lower voltage external zener diode must be added be-

tween the GATE and SENSE pins. The external zener diode

must have a forward current rating of at least 110 mA.

When the system voltage is initially applied (before the oper-

ating voltage reaches the PORIT threshold), the GATE pin is

held low by a 110 mA pull-down current. The pull-down cur-

rent helps prevent an inadvertent turn-on of the MOSFET

through its drain-gate capacitance as the applied system volt-

age increases.

During the insertion time (t1 in Figure 3) the GATE pin is held

low by a 2.2 mA pull-down current. This maintains Q1 in the

off-state until the end of t1, regardless of the voltage at VCC

and UVLO.

Following the insertion time, during t2 in Figure 3, the gate

voltage of Q1 is modulated to keep the current or Q1’s power

dissipation level from exceeding the programmed levels. Cur-

rent limiting and power limiting are considered fault condi-

tions, during which the voltage on the TIMER pin capacitor

increases. If the current and power limiting cease before the

TIMER pin reaches 4V the TIMER pin capacitor is discharged,

and the circuit enters normal operation. See the Fault Timer

& Restart paragraph for details on the fault timer.

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LM5067

If the system input voltage falls below the UVLO threshold, or

rises above the OVLO threshold, the GATE pin is pulled low

by the 2.2 mA pull-down current to switch off Q1.

30030931

FIGURE 4. Gate Control

Current Limit

The current limit threshold is reached when the voltage across

the sense resistor RS (SENSE to VEE) reaches 50 mV. In the

current limiting condition, the GATE voltage is controlled to

limit the current in MOSFET Q1. While the current limit circuit

is active, the fault timer is active as described in the Fault

Timer & Restart section. If the load current reduces below the

current limit threshold before the end of the Fault Timeout

Period, the LM5067 resumes normal operation. For proper

operation, the RS resistor value should be no larger than 100

mΩ.

Circuit Breaker

If the load current increases rapidly (e.g., the load is short-

circuited) the current in the sense resistor (RS) may exceed

the current limit threshold before the current limit control loop

is able to respond. If the current exceeds approximately twice

the current limit threshold (100 mV/RS), Q1’s gate is quickly

pulled down by the 110 mA pull-down current at the GATE

pin, and a Fault Timeout Period begins. When the voltage

across RS falls below 100 mV the 110 mA pull-down current

at the GATE pin is switched off, and the gate voltage of Q1 is

then determined by the current limit or the power limit func-

tions. If the TIMER pin reaches 4.0V before the current limiting

or power limiting condition ceases, Q1 is switched off by the

2.2 mA pull-down current at the GATE pin as described in the

Fault Timer & Restart section.

Power Limit

An important feature of the LM5067 is the MOSFET power

limiting. The Power Limit function can be used to maintain the

maximum power dissipation of MOSFET Q1 within the device

SOA rating. The LM5067 determines the power dissipation in

Q1 by monitoring its drain-source voltage (OUT to SENSE),

and the drain current through the sense resistor (SENSE to

VEE). The product of the current and voltage is compared to

the power limit threshold programmed by the resistor at the

PWR pin. If the power dissipation reaches the limiting thresh-

old, the GATE voltage is modulated to reduce the current in

Q1, and the fault timer is active as described in the Fault Timer

& Restart section.

Fault Timer & Restart

When the current limit or power limit threshold is reached

during turn-on or as a result of a fault condition, the gate-to-

source voltage of Q1 is modulated to regulate the load current

and power dissipation in Q1. When either limiting function is

active, an 85 µA fault timer current source charges the exter-

nal capacitor (CT) at the TIMER pin as shown in Figure 6

(Fault Timeout Period). If the fault condition subsides before

the TIMER pin reaches 4.0V, the LM5067 returns to the nor-

mal operating mode and CT is discharged by the 2.5 µA

current sink. If the TIMER pin reaches 4.0V during the Fault

Timeout Period, Q1 is switched off by a 2.2 mA pull-down

current at the GATE pin. The subsequent restart procedure

depends on which version of the LM5067 is in use.

The LM5067-1 latches the GATE pin low at the end of the

Fault Timeout Period, and CT is discharged by the 2.5 µA fault

current sink. The GATE pin is held low until a power up se-

quence is externally initiated by cycling the input voltage

(VSYS), or momentarily pulling the UVLO/EN pin within 2.5V

of VEE with an open-collector or open-drain device as shown

in Figure 5. The voltage across CT must be <0.3V for the

restart procedure to be effective.

30030932

FIGURE 5. Latched Fault Restart Control

The LM5067-2 provides an automatic restart sequence which

consists of the TIMER pin cycling between 4.0V and 1.25V

seven times after the Fault Timeout Period, as shown in Fig-

ure 6. The period of each cycle is determined by the 85 µA

charging current, and the 2.5 µA discharge current, and the

value of the capacitor CT. When the TIMER pin reaches 0.3V

during the eighth high-to-low ramp, the 52 µA current source

at the GATE pin turns on Q1. If the fault condition is still

present, the Fault Timeout Period and the restart cycle repeat.

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LM5067

30030933

FIGURE 6. Restart Sequence (LM5067-2)

Under-Voltage Lock-Out (UVLO)

The series pass MOSFET (Q1) is enabled when the input

supply voltage (VSYS) is within the operating range defined by

the programmable under-voltage lockout (UVLO) and over-

voltage lock-out (OVLO) levels. Typically the UVLO level at

VSYS is set with a resistor divider (R1-R3) as shown in Figure

1. When VSYS is less than the UVLO level, the internal 22 µA

current sink at UVLO/EN is enabled, the current source at

OVLO is off, and Q1 is held off by the 2.2 mA pull-down cur-

rent at the GATE pin. VSYS reaches its UVLO level when the

voltage at the UVLO/EN pin reaches 2.5V above VEE. Upon

reaching the UVLO level, the 22 µA current sink at the UVLO/

EN pin is switched off, increasing the voltage at the pin, pro-

viding hysteresis for this threshold. With the UVLO/EN pin

above 2.5V, Q1 is switched on by the 52 µA current source at

the GATE pin.

See the Applications Section for a procedure to calculate the

values of the threshold setting resistors (R1-R3). The mini-

mum possible UVLO level can be set by connecting the

UVLO/EN pin to VCC. In this case Q1 is enabled when the

operating voltage (VCC – VEE) reaches the POREN threshold

(8.4V).

Over-Voltage Lock-Out (OVLO)

The series pass MOSFET (Q1) is enabled when the input

supply voltage (VSYS) is within the operating range defined by

the programmable under-voltage lockout (UVLO) and over-

voltage lock-out (OVLO) levels. Typically the OVLO level at

VSYS is set with a resistor divider (R1-R3) as shown in Figure

1. If VSYS raises the OVLO pin voltage more than 2.5V above

VEE Q1 is switched off by the 2.2 mA pull-down current at the

GATE pin, denying power to the load. When the OVLO pin is

above 2.5V, the internal 22 µA current source at OVLO is

switched on, raising the voltage at OVLO and providing

threshold hysteresis. When the voltage at the OVLO pin is

reduced below 2.5V the 22 µA current source is switched off,

and Q1 is enabled. See the Applications Section for a proce-

dure to calculate the threshold setting resistor values.

Shutdown/Enable Control

See the Applications Information section for a description of

how to use the UVLO/EN pin and/or the OVLO pin for remote

shutdown and enable control of the LM5067.

Power Good Pin

The Power Good output indicator pin (PGD) is connected to

the drain of an internal N-channel MOSFET. An external pull-

up resistor is required at PGD to an appropriate voltage to

indicate the status to downstream circuitry. The off-state volt-

age at the PGD pin must be more positive than VEE, and can

be up to 80V above VEE with transient capability to 100V.

PGD is switched high at the end of the turn-on sequence when

the voltage from OUT to SENSE (the external MOSFET’s

VDS) decreases below 1.23V. PGD switches low if the

MOSFET’s VDS increases past 2.5V, if the system input volt-

age goes below the UVLO threshold or above the OVLO

threshold, or if a fault is detected. The PGD output is high

when the operating voltage (VCC-VEE) is less than 2V.

Application Information

(Refer to Figure 1)

RIN, CIN

The LM5067 operating voltage is determined by an internal

13V shunt regulator which receives its current from the sys-

tem voltage via RIN. When the system voltage exceeds 13V,

the LM5067 operating voltage (VCC – VEE) is between VEE

and VEE+13V. The remainder of the system voltage is

dropped across the input resistor RIN, which must be selected

to pass at least 2 mA into the LM5067 at the minimum system

voltage. The resistor’s power rating must be selected based

on the power dissipation at maximum system voltage, calcu-

lated from:

PRIN = (VSYS(max) – 13V)2/RIN

CURRENT LIMIT, RS

The LM5067 monitors the current in the external MOSFET

(Q1) by measuring the voltage across the sense resistor

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LM5067

(RS), connected from SENSE to VEE. The required resistor

value is calculated from:

(1)

where ILIM is the desired current limit threshold. When the

voltage across RS reaches 50 mV, the current limit circuit

modulates the gate of Q1 to regulate the current at ILIM. While

the current limiting circuit is active, the fault timer is active as

described in the Fault Timer & Restart section. For proper

operation, RS must be no larger than 100 mΩ.

While the maximum load current in normal operation can be

used to determine the required power rating for resistor RS,

basing it on the current limit value provides a more reliable

design since the circuit can operate near the current limit

threshold continuously. The resistor’s surge capability must

also be considered since the circuit breaker threshold is ap-

proximately twice the current limit threshold. Connections

from RS to the LM5067 should be made using Kelvin tech-

niques. In the suggested layout of Figure 7 the small pads at

the upper corners of the sense resistor connect only to the

sense resistor terminals, and not to the traces carrying the

high current. With this technique, only the voltage across the

sense resistor is applied to VEE and SENSE, eliminating the

voltage drop across the high current solder connections.

30030935

FIGURE 7. Sense Resistor Connections

POWER LIMIT THRESHOLD

The LM5067 determines the power dissipation in the external

MOSFET (Q1) by monitoring the drain current (the current in

RS), and the VDS of Q1 (OUT to SENSE pins). The resistor at

the PWR pin (RPWR) sets the maximum power dissipation for

Q1, and is calculated from the following equation:

RPWR = 1.42 x 105 x RS x PFET(LIM) (2)

where PFET(LIM) is the desired power limit threshold for Q1,

and RS is the current sense resistor described in the Current

Limit section. For example, if RS is 10 mΩ, and the desired

power limit threshold is 60W, RPWR calculates to 85.2 kΩ. If

Q1’s power dissipation reaches the power limit threshold,

Q1’s gate is modulated to control the load current, keeping

Q1’s power from exceeding the threshold. For proper opera-

tion of the power limiting feature, RPWR must be ≤150 kΩ.

While the power limiting circuit is active, the fault timer is ac-

tive as described in the Fault Timer & Restart section. Typi-

cally, power limit is reached during startup, or when the VDS

of Q1 increases due to a severe overload or short circuit.

The programmed maximum power dissipation should have a

reasonable margin relative to the maximum power defined by

the SOA chart if the LM5067-2 is used since the FET will be

repeatedly stressed during fault restart cycles. The FET man-

ufacturer should be consulted for guidelines. The PWR pin

can be left open if the application does not require use of the

power limit function.

TURN-ON TIME

The output turn-on time depends on whether the LM5067 op-

erates in current limit only, or in both power limit and current

limit, during turn-on.

A) Turn-on with current limit only: If the current limit thresh-

old is less than the current defined by the power limit threshold

at maximum VDS the circuit operates only at the current limit

threshold during turn-on. Referring to Figure 10a, as the drain

current reaches ILIM, the gate-to-source voltage is controlled

at VGSL to maintain the current at ILIM. As the output voltage

reaches its final value (VDS ≊ 0V) the drain current reduces

to the value defined by the load, and the gate is charged to

approximately 13V (VGATE). The time for the OUT pin voltage

to transition from zero volts to VSYS is equal to:

where CL is the load capacitance. For example, if VSYS = -48V,

CL = 1000 µF, and ILIM = 1A, tON calculates to 48 ms. The

maximum instantaneous power dissipated in the MOSFET is

48W. This calculation assumes the time from t1 to t2 in Figure

10a is small compared to tON, and the load does not draw any

current until after the output voltage has reached its final val-

ue, and PGD switches high (Figure 8).

30030937

FIGURE 8. No Load Current During Turn-on

If the load draws current during the turn-on sequence (Figure

9), the turn-on time is longer than the above calculation, and

is approximately equal to:

where RL is the load resistance and VSYS is the absolute value

of the system input voltage. The Fault Timeout Period must

be set longer than tON to prevent a fault shutdown before

the turn-on sequence is complete.

15 www.national.com

LM5067

30030939

FIGURE 9. Load Draws Current During Turn-On

B) Turn-on with power limit and current limit: The power

dissipation limit in Q1 (PFET(LIM)) is defined by the resistor at

the PWR pin, and the current sense resistor RS. See the

Power Limit Threshold section. If the current limit threshold

(ILIM) is higher than the current defined by the power limit

threshold at maximum VDS (PFET(LIM)/VSYS) the circuit oper-

ates initially in power limit mode when the VDS of Q1 is high,

and then transitions to current limit mode as the current in-

creases to ILIM as VDS decreases. See Figure 10b. Assuming

the load (RL) is not connected during turn-on, the time for the

output voltage to reach its final value is approximately equal

to:

For example, if VSYS = -48V, CL = 1000 µF, ILIM = 1A, and

PFET(LIM) = 20W, tON calculates to ≊68 ms, and the initial cur-

rent level (IP) is approximately 0.42A. The Fault Timeout

Period must be set longer than tON.

30030941

FIGURE 10. MOSFET Power Up Waveforms

www.national.com 16

LM5067

MOSFET SELECTION

It is recommended that the external MOSFET (Q1) selection

be based on the following criteria:

- The BVDSS rating should be greater than the maximum

system voltage (VSYS), plus ringing and transients which can

occur at VSYS when the circuit card, or adjacent cards, are

inserted or removed.

- The maximum continuous current rating should be based

on the current limit threshold (50 mV/RS), not the maximum

load current, since the circuit can operate near the current

limit threshold continuously.

- The Pulsed Drain Current spec (IDM) must be greater than

the current threshold for the circuit breaker function (100 mV/

RS).

- The SOA (Safe Operating Area) chart of the device, and

the thermal properties, should be used to determine the max-

imum power dissipation threshold set by the RPWR resistor.

The programmed maximum power dissipation should have a

reasonable margin from the maximum power defined by the

FET's SOA chart if the LM5067-2 is used since the FET will

be repeatedly stressed during fault restart cycles. The FET

manufacturer should be consulted for guidelines.

- RDS(on) should be sufficiently low that the power dissipa-

tion at maximum load current (IL(max)2 x RDS(on)) does not raise

its junction temperature above the manufacturer’s recom-

mendation.

If the device chosen for Q1 has a maximum VGS rating less

than 13V, an external zener diode must be added from its gate

to source, with the zener voltage less than the maximum

VGS rating. The zener diode’s forward current rating must be

at least 110 mA to conduct the GATE pull-down current during

startup and in the circuit breaker mode.

TIMER CAPACITOR, CT

The TIMER pin capacitor (CT) sets the timing for the insertion

time delay, fault timeout period, and restart timing of the

LM5067-2.

A) Insertion Delay - Upon applying the system voltage

(VSYS) to the circuit, the external MOSFET (Q1) is held off

during the insertion time (t1 in Figure 3) to allow ringing and

transients at VSYS to settle. Since each backplane’s response

to a circuit card plug-in is unique, the worst case settling time

must be determined for each application. The insertion time

starts when the operating voltage (VCC-VEE) reaches the

PORIT threshold, at which time the internal 6 µA current

source charges CT from 0V to 4.0V. The required capacitor

value is calculated from:

where t1 is the desired insertion delay. For example, if the

desired insertion delay is 250 ms, CT calculates to 0.38 µF.

At the end of the insertion delay, CT is quickly discharged by

a 1.5 mA current sink.

B) Fault Timeout Period - During turn-on of the output volt-

age, or upon detection of a fault condition where the current

limit and/or power limit circuits regulate the current through

Q1, CT is charged by the fault timer current source (85 µA).

The Fault Timeout Period is the time required for the TIMER

pin voltage to reach 4.0V above VEE, at which time Q1 is

switched off. The required capacitor value for the desired

Fault Timeout Period tFAULT is calculated from:

(3)

For example, if the desired Fault Timeout Period is 16 ms,

CT calculates to 0.34 µF. After a fault timeout, if the LM5067-1

is in use, CT must be allowed to discharge to <0.3V by the 2.5

µA current sink, after which a power up sequence can be ini-

tiated by external circuitry. See the Fault Timer and Restart

section and Figure 5. If the LM5067-2 is in use, after the Fault

Timeout Period expires a restart sequence begins as de-

scribed below (Restart Timing).

Since the LM5067 normally operates in power limit and/or

current limit during a power up sequence, the Fault Timeout

Period MUST be longer than the time required for the output

voltage to reach its final value. See the Turn-on Time section.

C) Restart Timing If the LM5067-2 is in use, after the Fault

Timeout Period described above, CT is discharged by the 2.5

µA current sink to 1.25V. The TIMER pin then cycles through

seven additional charge/discharge cycles between 1.25V and

4.0V as shown in Figure 6. The restart time ends when the

TIMER pin voltage reaches 0.3V during the final high-to-low

ramp. The restart time, after the Fault Timeout Period, is equal

to:

= CT x 9.4 x 106

For example, if CT = 0.33 µF, tRESTART = 3.1 seconds. At the

end of the restart time, Q1 is switched on. If the fault is still

present, the fault timeout and restart sequence repeats. The

on-time duty cycle of Q1 is approximately 0.5% in this mode.

UVLO, OVLO

By programming the UVLO and OVLO thresholds the

LM5067 enables the series pass device (Q1) when the input

supply voltage (VSYS) is within the desired operational range.

If VSYS is below the UVLO threshold, or above the OVLO

threshold, Q1 is switched off, denying power to the load. Hys-

teresis is provided for each threshold.

Note: All voltages are with respect to Vee in the discus-

sions below. Use absolute values in the equations.

Option A: The configuration shown in Figure 11 requires

three resistors (R1-R3) to set the thresholds.

30030946

FIGURE 11. UVLO and OVLO Thresholds Set By R1-R3

17 www.national.com

LM5067

The procedure to calculate the resistor values is as follows:

- Determine the upper UVLO threshold (VUVH) to enable

Q1, and the lower UVLO threshold (VUVL) to disable Q1.

- Determine the upper OVLO threshold (VOVH) to disable

Q1.

- The lower OVLO threshold (VOVL), to enable Q1, cannot

be chosen in advance in this case, but is determined after the

values for R1-R3 are determined. If VOVL must be accurately

defined in addition to the other three thresholds, see Option

B below.

The resistors are calculated as follows:

The lower OVLO threshold is calculated from:

As an example, assume the application requires the following

thresholds: VUVH = -36V, VUVL = -32V, VOVH = -60V.

The lower OVLO threshold calculates to -55.8V, and the OV-

LO hysteresis is 4.2V. Note that the OVLO hysteresis is

always slightly greater than the UVLO hysteresis in this con-

figuration.

When the R1-R3 resistor values are known, the threshold

voltages and hysteresis are calculated from the following:

Note: Ensure the voltages at the UVLO and OVLO pins do

not exceed the Absolute Maximum ratings for those pins

when the system voltage is at maximum.

Option B: If all four thresholds must be accurately defined,

the configuration in Figure 12 can be used.

30030951

FIGURE 12. Programming the Four Thresholds

The four resistor values are calculated as follows:

- Determine the upper UVLO threshold (VUVH) to enable Q1,

and the lower UVLO threshold (VUVL) to disable Q1.

- Determine the upper OVLO threshold (VOVH) to disable

Q1, and the lower OVLO threshold (VOVL) to enable Q1.

www.national.com 18

LM5067

As an example, assume the application requires the following

thresholds: VUVH = -22V, VUVL = -17V, VOVH = -60V, and

VOVL = -58V. Therefore VUV(HYS) = 5V, and VOV(HYS) = 2V. The

resistor values are:

R1 = 227 kΩ, R2 = 39.1 kΩ

R3 = 90.9 kΩ, R4 = 3.95 kΩ

Where the R1-R4 resistor values are known, the threshold

voltages and hysteresis are calculated from the following:

Note: Ensure the voltages at the UVLO and OVLO pins do

not exceed the Absolute Maximum ratings for those pins

when the system voltage is at maximum.

Option C: The minimum UVLO level is obtained by connect-

ing the UVLO pin to VCC as shown in Figure 13. Q1 is

switched on when the operating voltage reaches the POREN

threshold (≊8.4V). The OVLO thresholds are set by R3 and

R4 using the procedure in Option B.

Note: Ensure the voltage at the OVLO pin does not ex-

ceed the Absolute Maximum ratings for that pin when the

system voltage is at maximum.

30030955

FIGURE 13. UVLO = POREN

Option D: The OVLO function can be disabled by connecting

the OVLO pin to VEE. The UVLO thresholds are set as de-

scribed in Option B or Option C.

SHUTDOWN / ENABLE CONTROL

Figure 14a shows how to use the UVLO/EN pin for remote

shutdown and enable control. Taking the UVLO/EN pin below

its 2.5V threshold (with respect to VEE) shuts off the load

current. Upon releasing the UVLO/EN pin the LM5067 switch-

es on the load current with in-rush current and power limiting.

In Figure 14b the OVLO pin is used for remote shutdown and

enable control. When the external transistor is off, the OVLO

pin is above its 2.5V threshold (with respect to VEE) and the

load current is shut off. Turning on the external transistor al-

lows the LM5067 to switch on the load current with in-rush

current and power limiting.

30030956

a) Shutdown/Enable Using the UVLO/EN Pin

30030957

b) Shutdown/Enable Using the OVLO Pin

FIGURE 14. Shutdown/Enable

19 www.national.com

LM5067

POWER GOOD PIN

During initial power up, the Power Good pin (PGD) is high until

the operating voltage (VCC – VEE) increases above ≊2V.

PGD then switches low, remaining low as the system voltage

and the operating voltage increase. After Q1 is switched on,

when the voltage at the OUT pin is within 1.23V of the SENSE

pin (Q1’s VDS <1.23V), PGD switches high indicating the out-

put voltage is at, or nearly at, its final value. Any of the

following situations will cause PGD to switch low within ≊10

µs:

- The VDS of Q1 increases above 2.5V.

- The system input voltage decreases below the UVLO level.

- The system input voltage increase above the OVLO level.

- The TIMER pin increases to 4V due to a fault condition.

A pull-up resistor is required at PGD as shown in Figure 15.

The pull-up voltage (VPGD) can be as high as 80V above VEE,

with transient capability to 100V, and can be higher or lower

than the system ground.

30030958

FIGURE 15. Power Good Output

If a delay is required at PGD, suggested circuits are shown in

Figure 16. In Figure 16a, capacitor CPG adds delay to the ris-

ing edge, but not to the falling edge. In Figure 16b, the rising

edge is delayed by RPG1 + RPG2 and CPG, while the falling

edge is delayed a lesser amount by RPG2 and CPG. Adding a

diode across RPG2 (Figure 16c) allows for equal delays at the

two edges, or a short delay at the rising edge and a long delay

at the falling edge.

30030959

FIGURE 16. Adding Delay to the Power Good Output Pin

Design-in Procedure

The recommended design-in procedure for the LM5067 is as

follows:

•Determine the minimum and maximum system voltages

(VEE). Select the input resistor (RIN) to provide at least 2

mA into the VCC pin at the minimum system voltage.The

resistor’s power rating must be suitable for its power

dissipation at maximum system voltage ((VSYS – 13V)2/

RIN).

•Determine the current limit threshold (ILIM). This threshold

must be higher than the normal maximum load current,

allowing for tolerances in the current sense resistor value

and the LM5067 Current Limit threshold voltage. Use

equation 1 to determine the value for RS.

•Determine the maximum allowable power dissipation for

the series pass FET (Q1), using the device’s SOA

information. Use equation 2 to determine the value for

RPWR.

•Determine the value for the timing capacitor at the TIMER

pin (CT) using equation 3. The fault timeout period

(tFAULT) must be longer than the circuit’s turn-on-

time. The turn-on time can be estimated using the

equations in the Turn-on Time section of this data sheet,

but should be verified experimentally. Allow for tolerances

in the values of the external capacitors, sense resistor, and

the LM5067 Electrical Characteristics for the TIMER pin,

current limit and power limt. Review the resulting insertion

time, and the restart timing if the LM5067-2 is used.

•Choose option A, B, C, or D from the UVLO, OVLO section

of the Application Information for setting the UVLO and

OVLO thresholds and hysteresis. Use the procedure in the

appropriate option to determine the resistor values at the

UVLO and OVLO pins.

•Choose the appropriate voltage, and pull-up resistor, for

the Power Good output.

www.national.com 20

LM5067

PC Board Guidelines

The following guidelines should be followed when designing

the PC board for the LM5067:

•Place the LM5067 close to the board’s input connector to

minimize trace inductance from the connector to the FET.

•Place RIN and CIN close to the VCC and VEE pins to keep

transients below the Absolute Maximum rating of the

LM5067. Transients of several volts can easily occur when

the load current is shut off.

•The sense resistor (RS) should be close to the LM5067,

and connected to it using the Kelvin techniques shown in

Figure 7.

•The high current path from the board’s input to the load,

and the return path (via Q1), should be parallel and close

to each other wherever possible to minimize loop

inductance.

•The VEE connection for the various components around

the LM5067 should be connected directly to each other,

and to the LM5067’s VEE pin, and then connected to the

system VEE at one point. Do not connect the various

components to each other through the high current VEE

track.

•Provide adequate heat sinking for the series pass device

(Q1) to help reduce thermal stresses during turn-on and

turn-off.

•The board’s edge connector can be designed to shut off

the LM5067 as the board is removed, before the supply

voltage is disconnected from the LM5067. In Figure 17 the

voltage at the UVLO/EN pin goes to VEE before VSYS is

removed from the LM5067 due to the shorter edge

connector pin. When the board is inserted into the edge

connector, the system voltage is applied to the LM5067’s

VEE and VCC pins before voltage is applied to the UVLO/

EN pin.

•If power dissipation within the LM5067 is high, an exposed

copper pad should be provided beneath the package, and

that pad should be connected to exposed copper on the

board’s other side with as many vias as possible. See the

Thermal Considerations section.

30030962

FIGURE 17. Suggested Board Connector Design

21 www.national.com

LM5067

Thermal Considerations

The LM5067 should be operated so that its junction temper-

ature does not exceed 125°C. The junction temperature is

equal to:

TJ = TA + (RθJA x PD)

where TA is the ambient temperature, and RθJA is the thermal

resistance of the LM5067. PD is the power dissipated within

the LM5067, calculated from:

PD = 13V x ICC

where ICC is the current into the VCC pin (the current through

the RIN resistor). Values for RθJA and RθJC are in the table of

Electrical Chracteristics.

System Considerations

A) Continued proper operation of the LM5067 hot swap circuit

requires capacitance be present on the supply side of the

connector into which the hot swap circuit is plugged in, as

depicted in Figure 2. The capacitor in the “Live Backplane”

section is necessary to absorb the transient generated when-

ever the hot swap circuit shuts off the load current. If the

capacitance is not present, inductance in the supply lines will

generate a voltage transient at shut-off which can exceed the

absolute maximum rating of the LM5067, resulting in its de-

struction.

B) If the load powered via the LM5067 hot swap circuit has

inductive characteristics, a diode is required across the

LM5067’s output to provide a recirculating path for the load’s

current. Adding the diode prevents possible damage to the

LM5067 as the OUT pin will be taken above ground by the

inductive load at shutoff. See Figure 18.

30030963

FIGURE 18. Output Diode Required for Inductive Loads

www.national.com 22

LM5067

Physical Dimensions inches (millimeters) unless otherwise noted

NS Package Number MUB10A

NS Package Number M14B

23 www.national.com

LM5067

Notes

LM5067 Negative Hot Swap / Inrush Current Controller with Power Limiting

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