© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 8
1Publication Order Number:
SN74LS221/D
SN74LS221
Dual Monostable
Multivibrators with
Schmitt−Trigger Inputs
Each multivibrator of the LS221 features a negative-transition-
triggered input and a positive-transition-triggered input either of
which can be used as an inhibit input.
Pulse triggering occurs at a voltage level and is not related to the
transition time of the input pulse. Schmitt-trigger input circuitry for B
input allows jitter-free triggering for inputs as slow as 1 volt/second,
providing the circuit with excellent noise immunity. A high immunity
to VCC noise is also provided by internal latching circuitry.
Once triggered, the outputs are independent of further transitions of
the inputs and are a function of the timing components. The output
pulses can be terminated by the overriding clear. Input pulse width
may be of any duration relative to the output pulse width. Output pulse
width may be varied from 35 nanoseconds to a maximum of 70 s by
choosing appropriate timing components. With Rext = 2.0 kΩ and Cext
= 0, a typical output pulse of 30 nanoseconds is achieved. Output rise
and fall times are independent of pulse length.
Pulse width stability is achieved through internal compensation and
is virtually independent of VCC and temperature. In most applications,
pulse stability will only be limited by the accuracy of external timing
components.
Jitter-free operation is maintained over the full temperature and VCC
ranges for greater than six decades of timing capacitance (10 pF to 10
μF), and greater than one decade of timing resistance (2.0 to 100 kΩ
for the SN74LS221). Pulse width is defined by the relationship:
tw(out) = CextRext ln 2.0 ≈0.7 Cext Rext; where tW is in ns if Cext is in
pF and Rext is in kΩ. If pulse cutoff is not critical, capacitance up to
1000 μF and resistance as low as 1.4 kΩ may be used. The range of
jitter-free pulse widths is extended if VCC is 5.0 V and 25°C
temperature.
•SN74LS221 is a Dual Highly Stable One-Shot
•Overriding Clear Terminates Output Pulse
•Pin Out is Identical to SN74LS123
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient
Temperature Range
0 25 70 °C
IOH Output Current − High −0.4 mA
IOL Output Current − Low 8.0 mA
LOW
POWER
SCHOTTKY
SOIC
D SUFFIX
CASE 751B
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
Device Package Shipping
ORDERING INFORMATION
SN74LS221N 16 Pin DIP 2000 Units/Box
SN74LS221D SOIC−16 38 Units/Rail
SN74LS221DR2 SOIC−16 2500/Tape & Reel
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SN74LS221
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2
(TOP VIEW)
Positive logic: Low input to clear resets Q low and
Positive logic: Q high regardless of dc levels at A
Positive logic: or B inputs.
14 13 12 11 10 9
123456 7
16 15
8
VCC
1A
1 Rext/
Cext
1
Cext 1Q 2Q 2B
2
CLR 2A
1B 1
CLR 1Q 2Q 2
Cext
2 Rext/
Cext GND
Q
Q
CLR
Q
Q
CLR
+
VCC
Rext
R/CCext
FUNCTION TABLE
(EACH MONOSTABLE)
INPUTS OUTPUTS
CLEAR A B Q Q
L X X L H
X H XL H
X X LL H
H L °
H±H
*°L H
*See operational notes — Pulse Trigger Modes
TYPE
TYPICAL
POWER
MAXIMUM
OUTPUT PULSE
DISSIPATION LENGTH
SN74LS221 23 mW 70 s
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3
OPERATIONAL NOTES
Once in the pulse trigger mode, the output pulse width is
determined by tW = RextCextIn2, as long as Rext and Cext are
within their minimum and maximum valves and the duty
cycle is less than 50%. This pulse width is essentially
independent of VCC and temperature variations. Output
pulse widths varies typically no more than ±0.5% from
device to device.
If the duty cycle, defined as being 100 @tW
T where T is the
period of the input pulse, rises above 50%, the output pulse
width will become shorter. If the duty cycle varies between
low and high valves, this causes the output pulse width to
vary in length, or jitter. To reduce jitter to a minimum, Rext
should be as large as possible. (Jitter is independent of Cext).
With Rext = 100K, jitter is not appreciable until the duty
cycle approaches 90%.
Although the LS221 is pin-for-pin compatible with the
LS123, it should be remembered that they are not
functionally identical. The LS123 is retriggerable so that the
output is dependent upon the input transitions once it is high.
This is not the case for the LS221. Also note that it is
recommended to externally ground the LS123 Cext pin.
However, this cannot be done on the LS221.
The SN74LS221 is a dual, monolithic, non-retriggerable,
high-stability one shot. The output pulse width, tW can be
varied over 9 decades of timing by proper selection of the
external timing components, Rext and Cext.
Pulse triggering occurs at a voltage level and is, therefore,
independent of the input slew rate. Although all three inputs
have this Schmitt-trigger effect, only the B input should be
used for very long transition triggers (≥1.0 μV/s). High
immunity to VCC noise (typically 1.5 V) is achieved by
internal latching circuitry. However, standard VCC
bypassing is strongly recommended.
The LS221 has four basic modes of operation.
Clear Mode: If the clear input is held low, irregardless of
the previous output state and other input
states, the Q output is low.
Inhib-
it Mode:
If either the A input is high or the B input is
low, once the Q output goes low, it cannot
be retriggered by other inputs.
Pulse Trigger
Mode: A transition of the A or B inputs as indicated
in the functional truth table will trigger the Q
output to go high for a duration determined
by the tW equation described above; Q will
go low for a corresponding length of time.
The Clear input may also be used to trigger
an output pulse, but special logic precondi-
tioning on the A or B inputs must be done
as follows:
Following any output triggering action
using the A or B inputs, the A input must
be set high OR the B input must be set
low to allow Clear to be used as a trigger.
Inputs should then be set up per the truth
table (without triggering the output) to
allow Clear to be used a trigger for the
output pulse.
If the Clear pin is routinely being used to
trigger the output pulse, the A or B inputs
must be toggled as described above be-
fore and between each Clear trigger
event.
Once triggered, as long as the output re-
mains high, all input transitions (except
overriding Clear) are ignored.
Overriding
Clear Mode: If the Q output is high, it may be forced low
by bringing the clear input low.
SN74LS221
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4
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
Limits
Unit Test Conditions
Min Typ Max
VT+
Positive-Going Threshold
Voltage at C Input 1.0 2.0 V VCC = MIN
VT−Negative-Going Threshold
Voltage at C Input
0.7 0.8 V VCC = MIN
VT+
Positive-Going Threshold
Voltage at B Input 1.0 2.0 V VCC = MIN
VT−Negative-Going Threshold
Voltage at B Input
0.8 0.9 V VCC = MIN
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
A Input
VIL Input LOW Voltage 0.8 VGuaranteed Input LOW Voltage for
A Input
VIK Input Clamp Voltage −1.5 V VCC = MIN, IIN = −18 mA
VOH Output HIGH Voltage 2.7 3.4 V VCC = MIN, IOH = MAX
VOL Output LOW Voltage 0.35 0.5 V IOL = 8.0 mA VCC = MIN
IIH Input HIGH Current
20 μA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
Input A
Input B
Clear
−0.4
−0.8
−0.8
mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) −20 −100 mA VCC = MAX
ICC
Power Supply Current
Quiescent 4.7 11 mA VCC = MAX
Triggered 19 27
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
SN74LS221
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5
AC CHARACTERISTICS (VCC = 5.0 V, TA = 25°C)
Symbol
From
(Input)
To
(Output)
Limits
Unit Test Conditions
Min Typ Max
tPLH
A Q 45 70
ns
CL = 15 pF,
See Figure 1
Cext = 80 pF, Rext = 2.0 Ω
B Q 35 55
tPHL
A Q 50 80
ns
B Q 40 65
tPHL Clear Q 35 55 ns
tPLH Clear Q 44 65 ns
tW(out) A or B Q or Q
70 120 150
ns
Cext = 80 pF, Rext = 2.0 Ω
20 47 70 Cext = 0, Rext = 2.0 kΩ
600 670 750 Cext = 100 pF, Rext = 10 kΩ
6.0 6.9 7.5 ms Cext = 1.0 μF, R ext = 10 kΩ
AC SETUP REQUIREMENTS (VCC = 5.0 V, TA = 25°C)
Symbol Parameter
Limits
Unit
Min Typ Max
dv/dt
Rate of Rise or Fall of Input Pulse
Schmitt, B 1.0 V/s
Logic Input, A 1.0 V/μs
tW
Input Pulse Width
A or B, tW(in) 40 ns
Clear, tW (clear) 40
tsClear-Inactive-State Setup Time 15 ns
Rext External Timing Resistance 1.4 100 kΩ
Cext External Timing Capacitance 0 1000 μF
Output Duty Cycle
RT = 2.0 kΩ50 %
RT = MAX Rext 90
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6
AC WAVEFORMS
B INPUT
CLEAR
Q OUTPUT
Q OUTPUT
A INPUT IS LOW.
B INPUT
CLEAR
Q OUTPUT
A INPUT IS LOW.
B INPUT
CLEAR
Q OUTPUT
A INPUT IS LOW.
tW(in)
≥60 ns
tPLH
tPHL tPLH
tPHL
1.3 V
3 V
0 V
3 V
0 V
VOH
VOL
VOH
VOL
≥60 ns
1.3 V
1.3 V
3 V
0 V
3 V
0 V
VOH
VOL
≥50 ns ≥0ts
3 V
0 V
3 V
0 V
VOH
VOL
3 V
0 V
3 V
0 V
VOH
VOL
TRIGGERED
NOT TRIGGERED
≥50 ns≥50 ns
B INPUT
CLEAR
Q OUTPUT
A INPUT IS LOW.
tW(out)
TRIGGER FROM B, THEN CLEAR — CONDITION 1
TRIGGER FROM B, THEN CLEAR — CONDITION 2
CLEAR OVERRIDING B, THEN TRIGGER FROM B
TRIGGERING FROM POSITIVE TRANSITION OF CLEAR
Figure 1.
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7
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648−08
ISSUE R NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
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