C8051F52x/F52xA/F53x/F53xA
Rev. 1.4 98
10. Interrupt Handler
The C8051F52x/F52xA/F53x/F53xA family includes an extended interrupt syst em with two selectable pri-
ority levels. The allo cation of interrupt so urces between o n-chip peripher als and external inpu t pins varies
according to the specific version of the de vice. Each in terrupt sou rce has one or mor e associated interrup t-
pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition,
the associat ed interr up t- pe n din g fla g is set to logic 1.
If interrupt s are ena bled for the sour ce, an interrupt req uest is generated when the inter rupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede-
termined address to begin executio n of an interrupt service routine ( ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt requ est had not occurred. If inter rupt s are not enabled, the inter rupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-
less of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in the Interrupt Enable and Extended Interrupt Enable SFRs. However, interrupts must first be
globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recog-
nized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-
enable settings. Note that interrupts which occur when the EA bit is set to logic 0 will be held in a pending
state, and will not be serviced until the EA bit is set back to logic 1.
Some interrupt-pending flags ar e auto matically cleare d by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by sof tware be fore returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
10.1. MCU Interrupt Sources and Vectors
The C8051F52x/F52xA/F53x/F53xA MCUs support 15 interrupt sources. Software can simulate an inter-
rupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt
request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending
flag. MCU interrupt sources, associated vector addresses, priority order, and control bits are summarized
in Table 10.1 on page 99. Refer to the data sheet sect ion associa ted with a pa rticular on -chip peripher al for
information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending
flag(s).
10.2. Interrupt Priorities
Each interrupt source can be in dividua lly prog ra mmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be pree mpted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure
its priority level. Low priority is the defa ult. If two interrupt s are recognize d simultane ously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 10.1.
10.3. Interrupt Latency
Interrupt response time depen ds on the state of the CPU when the interr upt occur s. Pending inter ru pts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to serv ice the pendin g inte rrup t. Th eref ore, the maxim um r espo nse tim e for an int errupt (when no
other interrupt is currently being serviced or the ne w interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, t he response time is