LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 5V, 10A Synchronous Step-Down SilentSwitcher2 in 3mmx3mm LQFN FEATURES DESCRIPTION Silent Switcher(R)2 Architecture: Ultralow EMI Emissions (LTC3310S and LTC3310S-1) n High Efficiency: 4.5m NMOS and 16m PMOS n Wide Bandwidth, Fast Transient Response n Safely Tolerates Inductor Saturation in Overload n V Range: 2.25V to 5.5V IN n V OUT Range: 0.5V to VIN n V OUT Accuracy: 1% with Remote Sense n Peak Current Mode Control n 35ns Minimum On-Time n Programmable Frequency to 5MHz n Shutdown Current: 1A n Precision 400mV Enable Threshold n Output Soft-Start with Voltage Tracking n Power Good Output n Die Temperature Monitor n Configurable for Paralleling Power Stages n Thermally-Enhanced 3mm x 3mm LQFN Package n AEC-Q100 Qualified for Automotive Applications The LTC(R)3310S is a very small, low noise, monolithic step-down DC/DC converter capable of providing up to 10A of output current from a 2.25V to 5.5V input supply. The device employs Silent Switcher 2 architecture with internal hot loop bypass capacitors to achieve both low EMI and high efficiency at switching frequencies as high as 5MHz. For systems with higher power requirements, multi-phasing parallel converters is readily implemented. PART NUMBER Silent Switcher VOUT APPLICATIONS LTC3310S SS2 Adjustable LTC3310S-1 SS2 Fixed 1V LTC3310 SS1 Adjustable LTC3310-1 SS1 Fixed 1V n The LTC3310S uses a constant-frequency, peak current mode control architecture for fast transient response. A 500mV reference allows for low voltage outputs. 100% duty cycle operation delivers low drop out. Other features include a power good signal when the output is in regulation, precision enable threshold, output overvoltage protection, thermal shutdown, a temperature monitor, clock synchronization, mode selection and output short circuit protection. Automotive/Industrial/Communications n Servers, Telecom Power Supplies n Distributed DC Power Systems (POL) n FPGA, ASIC, P Core Supplies n All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION Efficiency vs Load Current 1.2V 10A Step-Down Converter VIN 2.25V TO 5V 100 3.0 90 MODE/SYNC PGOOD LTC3310S 80 100nH 70 2.1 60 1.8 50 1.5 40 1.2 SW 15pF FB 100k SSTT 0.1F ITH PGND 10k 140k VOUT 1.2V 10A 22F x3 AGND 30 RT 20 3310S1 TA01a 274k 220pF L = XEL4030-101ME, COILCRAFT 0.9 POWER LOSS 10 0 2.4 0 1 2 0.6 VIN = 3.3V VOUT = 1.2V fOSC = 2MHz 3 4 5 6 7 LOAD CURRENT (A) 8 9 0.3 10 3310S1 TA01b Document Feedback For more information www.analog.com POWER LOSS (W) EN VIN 2.7 EFFICIENCY 22F EFFICIENCY (%) 22F 0 Rev. E 1 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) FB or VOUT ITH SSTT RT TOP VIEW 18 17 16 15 14 PGOOD EN 1 13 MODE/SYNC AGND 2 19 PGND VIN 3 12 VIN 11 VIN VIN 4 10 PGND 6 7 8 9 SW SW SW PGND 5 SW VIN .............................................................. -0.3V to 6V EN, SSTT.............. -0.3V to Lesser of (VIN + 0.3V) or 6V MODE/SYNC......... -0.3V to Lesser of (VIN + 0.3V) or 6V RT......................... -0.3V to Lesser of (VIN + 0.3V) or 6V FB or VOUT............ -0.3V to Lesser of (VIN + 0.3V) or 6V PGOOD.......................................................... -0.3V to 6V IPGOOD.......................................................................5mA Operating Junction Temperature Range (Notes 2, 3) LTC3310SE/LTC3310SE-1................... -40C to 125C LTC3310SI/LTC3310SI-1..................... -40C to 125C LTC3310J/LTC3310J-1........................ -40C to 150C LTC3310H/LTC3310H-1...................... -40C to 150C Storage Temperature............................. -65C to +150C Maximum Reflow (Package Body) Temperature.... 260C LQFN PACKAGE 18-LEAD (3mm x 3mm) JA = 42C/W, JCbottom = 9C/W, JCtop = 62C/W, JB = 14C/W JT = 1.25C/W, VALUES DETERMINED PER JESD51-12 EXPOSED PAD (PIN 19) IS PGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH AUTOMOTIVE PRODUCTS** PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3310S LTC3310SEV#PBF LTC3310SEV#WPBF LTC3310SIV#PBF LTC3310SIV#WPBF LTC3310SEV#TRPBF LTC3310SEV#WTRPBF LTC3310SIV#TRPBF LTC3310SIV#WTRPBF LTC3310SEV#TRMPBF LTC3310SEV#WTRMPBF LTC3310SIV#TRMPBF LTC3310SIV#WTRMPBF LHCN 18-Lead (3mm x 3mm) LQFN (Laminate Package with QFN Footprint) -40C to 125C LHKG 18-Lead (3mm x 3mm) LQFN (Laminate Package with QFN Footprint) -40C to 125C LTC3310S-1 LTC3310SEV-1#PBF Contact Marketing LTC3310SIV-1#PBF Contact Marketing LTC3310SEV-1#TRPBF Contact Marketing LTC3310SIV-1#TRPBF Contact Marketing LTC3310SEV-1#TRMPBF Contact Marketing LTC3310SIV-1#TRMPBF Contact Marketing Rev. E 2 For more information www.analog.com LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 ORDER INFORMATION LEAD FREE FINISH AUTOMOTIVE PRODUCTS** PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3310 LTC3310JV#PBF LTC3310JV#WPBF LTC3310HV#PBF LTC3310HV#WPBF LTC3310JV#TRPBF LTC3310JV#WTRPBF LTC3310HV#TRPBF LTC3310HV#WTRPBF LTC3310JV#TRMPBF LTC3310JV#WTRMPBF LTC3310HV#TRMPBF LTC3310HV#WTRMPBF LHGW 18-Lead (3mm x 3mm) LQFN (Laminate Package with QFN Footprint) -40C to 150C LHMP 18-Lead (3mm x 3mm) LQFN (Laminate Package with QFN Footprint) -40C to 150C LTC3310-1 LTC3310JV-1#PBF LTC3310JV-1#WPBF LTC3310HV-1#PBF LTC3310HV-1#WPBF LTC3310JV-1#TRPBF LTC3310JV-1#WTRPBF LTC3310HV-1#TRPBF LTC3310HV-1#WTRPBF LTC3310JV-1#TRMPBF LTC3310JV-1#WTRMPBF LTC3310HV-1#TRMPBF LTC3310HV-1#WTRMPBF Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for thesemodels. ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operatingtemperature range, otherwise specifications are at TA = 25C. (Notes 2, 3) VIN = 3.3V, VEN = VIN, MODE/SYNC = 0V, unlessotherwisenoted. PARAMETER CONDITIONS MIN TYP MAX UNITS Input Supply Operating Supply Voltage (VIN) VIN Undervoltage Lockout VIN Undervoltage Lockout Hysteresis VIN Rising VIN Quiescent Current VIN Quiescent Current in Shutdown (Note 4) VEN = 0.1V EN Threshold EN Hysteresis VEN Rising EN Pin Leakage Current VEN = 0.4V l 2.25 l 2.0 l 0.375 5.5 V 2.1 150 2.2 V mV 1.3 1 2.0 2 mA A 0.4 60 0.425 V mV 20 nA mV Voltage Regulation Regulated Feedback Voltage (VFB) Regulated Output Voltage LTC3310S-1, LTC3310-1, IOUT = 4A Output Line Regulation 2.5V VIN 5.0V VOUT Active Voltage Positioning LTC3310S-1, LTC3310-1, l 495 500 505 l 0.990 1.000 1.010 0.002 0.025 %/V l 1.7 2.4 3.1 mV/A 20 nA V Feedback Pin Input Current VFB = 0.5V Error Amp Transconductance LTC3310S, LTC3310 400 S Error Amp Transconductance LTC3310S-1, LTC3310-1 800 S Rev. E For more information www.analog.com 3 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operatingtemperature range, otherwise specifications are at TA = 25C. (Notes 2, 3) VIN = 3.3V, VEN = VIN, MODE/SYNC = 0V, unlessotherwisenoted. PARAMETER CONDITIONS MIN Error Amp Sink/Source Current TYP MAX 25 UNITS A Top Switch Current Limit VOUT/VIN 0.2, Current Out of SW l 14.5 16 18.5 A Bottom Switch Current Limit (IVALLEYMAX) Current Out of SW l 10 12 14 A Top Switch ON-Resistance Bottom Switch ON-Resistance SW Leakage Current VEN = 0.1V VITH to IPeak Current Gain 16 m 4.5 m 100 nA 18 35 Minimum On-Time l Maximum Duty cycle l 100 A/V 60 ns % Power Good/Soft-Start/Temp Monitor PGOOD Rising Threshold PGOOD Hysteresis As a Percentage of the Regulated VOUT l l 97 0.5 98 1 99 1.5 % % Overvoltage Rising Threshold Overvoltage Hysteresis As a Percentage of the Regulated VOUT l l 106 1 110 2.5 112.5 3.5 % % PGOOD Leakage Current VPGOOD = 5.5V 20 nA PGOOD Pull-Down Resistance VPGOOD = 0.1V 20 13 A 12 PGOOD Delay Soft-Start Charge Current 100 VSSTT = 0.5V l 7 Temp Monitor Slope 10 s 4 mV/C Oscillator Switching Frequency Range RT Programmable l Switching Frequency RT = 274k l 1.8 Synchronization Frequency Range RT = VIN l 0.5 Default Frequency RT = VIN l 1.8 l l 1.2 SYNC Level High on MODE/SYNC SYNC Level Low on MODE/SYNC Minimum MODE/SYNC Pulse Width 0.5 5 2 2 40 MHz 2.2 MHz 2.25 MHz 2.2 MHz 0.4 V V ns MODE/SYNC Input Resistance 200 k MODE/SYNC No Clock Detect Time 20 s MODE/SYNC Clock Out Rise/Fall Time CMODE/SYNC = 50pF 10 ns MODE/SYNC Clock Low Output Voltage IMODE/SYNC = 100A 0.2 V MODE/SYNC Clock High Output Voltage IMODE/SYNC = 100A VIN - 0.2 V 50 % MODE/SYNC Clock Out Duty Cycle Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3310SE/LTC3310SE-1 is guaranteed to meet performance specifications from 0C to 125C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. The LTC3310SI/LTC3310SI-1 is guaranteed over the -40C to 125C operating junction temperature range. The LTC3310J/LTC3310J-1 and LTC3310H/LTC310H-1 are guaranteed over the -40C to 150C operating junction temperature range. Note 3: The LTC3310S includes overtemperature protection which protects the device during momentary overload conditions. Junction temperatures will exceed 150C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 4: Supply current specification does not include switching currents. Actual supply currents will be higher. Rev. E 4 For more information www.analog.com LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 TYPICAL PERFORMANCE CHARACTERISTICS 1.210 1.208 1.208 1.206 1.206 1.204 1.204 1.202 1.202 1.200 1.198 1.194 1.194 1.190 1.188 0 2 4 6 ILOAD (A) 1.08 1.06 1.04 1.198 1.196 VIN = 2.25V VIN = 3.3V VIN = 5V 1.10 1.200 1.196 1.192 1.190 10 1.188 2 2.5 3 3.5 4 4.5 INPUT VOLTAGE (V) 5 3310S1 G01 0.92 0.90 5.5 100 20.0 0 1 2 3 4 5 6 ILOAD (A) 7 8 9 10 3310S1 G03 Efficiency, Forced Continuous Mode, ForcedVContinuous IN = 3.3V Mode Operation 90 1.06 80 PMOS CURRENT (A) 1.02 1.00 0.98 0.96 0.94 2 2.5 3 3.5 4 4.5 INPUT VOLTAGE (V) 5 16.0 14.0 12.0 1A 5A 9A 0.92 EFFICIENCY (%) 18.0 1.04 VOUT (V) 25C -45C 125C 0.94 1.08 5.5 10.0 0 VOUT = 0.5V VOUT = 1.2V VOUT = 1.8V fSW = 2MHz COILCRAFT XEL4030-101MEC 1 ILOAD (A) 40 30 10 0 0.01 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 10 3310S1 G07 VOUT = 0.5V VOUT = 1.2V VOUT = 1.8V fSW = 2MHz COILCRAFT XEL4030-101MEC 0.1 100 100 90 95 80 90 70 85 60 50 40 30 20 10 0 0.001 FSW = 2MHz FSW = 4MHz 4MHz XFMRS XF303020-50NM 2MHz COILCRAFT XEL4030-101MEC 0.01 0.1 ILOAD (A) 1 3310S1 G06 80 75 70 VIN = 2.5V VIN = 3.3V VIN = 5.0V fSW = 2MHz COILCRAFT XEL4030-101MEC 65 55 3310S1 G08 10 Efficiency, PulseSkipping Mode, VPulse Skip Mode Operation IN = 1.2V 60 10 1 ILOAD (A) EFFICIENCY (%) 70 EFFICIENCY (%) 80 0.1 50 Efficiency, PulseSkipping Mode VPulse VOUT = 1.2V Skip Mode IN = 3.3V, 90 50 0.01 60 3310S1 G05 Efficiency, PulseSkipping Mode, VIN = 3.3V 60 70 20 VIN = 2.5V VIN = 3.3V VIN = 5V 3310S4 G04 EFFICIENCY (%) 0.98 PMOS Current Limit 1.10 100 1.00 3310S1 G02 VOUT Line Regulation (LTC3310S-1, LTC3310-1) Vout Line Regulation 0.90 1.02 0.96 LOAD = 1A LOAD = 3A LOAD = 6A LOAD = 9A 1.192 8 VOUT Load Regulation (LTC3310S-1, LTC3310-1) Vout Load Regulation VOUT Line Regulation, VOUTOUT =1.2V VOUT (V) 1.212 1.210 VOUT (V) VOUT (V) 1.212 VOUT Load Regulation, VOUTOUT =1.2V TA = 25C, VIN = 3.3V, unless otherwise noted. 50 0.01 0.1 1 ILOAD (A) 10 3310S1 G09 Rev. E For more information www.analog.com 5 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 TYPICAL PERFORMANCE CHARACTERISTICS Switch On-Resistance VOUT Voltage vs Temperature 24 505 1.05 504 1.04 22 503 1.03 20 502 1.02 501 1.01 500 499 1.00 0.99 498 0.98 497 0.97 496 0.96 495 -50 0.95 -50 -25 0 50 25 75 TEMPERATURE (C) 100 125 Switch On-Resistance -25 10 5 0 25 50 75 TEMPERATURE (C) 0 25 50 75 TEMPERATURE (C) 100 100 1 0 25 50 75 100 TEMPERATURE (C) 2.1 2.0 1.9 1.8 1.6 -50 125 0 25 50 75 TEMPERATURE (C) 100 125 3310S1 G16 0 25 50 75 TEMPERATURE (C) 125 EN Pin Thresholds RT = 274k EN RISING 400 2.05 2.00 1.95 390 380 370 360 EN FALLING 350 1.85 1.80 -50 100 410 1.90 RISING FALLING -25 3310S1 G15 EN THRESHOLD (mV) FREQUENCY (MHz) VIN UVLO (V) 2.2 1.7 2.10 1.7 5.5 2.3 3310S1 G14 2.3 50 3310S1 G12 Switching Frequency 1.9 3.0 3.5 4.0 4.5 INPUT VOLTAGE (V) Default Switching Frequency 2 2.20 2.1 2.5 2.4 3 2.15 -25 2 2.0 125 4 -1 125 VIN UVLO 1.5 -50 4 PMOS NMOS 5 3310S1 G13 2.5 10 6 DEFAULT FREQUENCY (MHz) SWITCH LEAKAGE CURRENT (A) RDS(ON) (m) 15 -25 12 Switch Leakage 6 0 -50 14 3310S1 G11 25 20 16 8 0A 5A 10A 3310S1 G10 VIN = 3.3V PMOS NMOS PMOS NMOS 18 RDS(ON) (m) VOUT (V) REFERENCE VOLTAGE (mV) Feedback Reference Voltage TA = 25C, VIN = 3.3V, unless otherwise noted. -25 0 25 50 75 TEMPERATURE (C) 100 125 3310S1 G17 340 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 3310S1 G18 Rev. E 6 For more information www.analog.com LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 TYPICAL PERFORMANCE CHARACTERISTICS Soft-Start Current VIN Quiescent Current Soft-Start Tracking 10.8 600 10.7 2.5 500 2.0 10.5 10.4 10.3 VIN CURRENT (mA) 10.6 FB VOLTAGE (mV) 400 300 200 10.2 10.0 -50 -25 0 25 50 75 TEMPERATURE (C) 100 0 125 0 100 3310S1 G19 VIN Shutdown Current 200 300 400 SSTT VOLTAGE (mV) 500 CURRENT (A) 12 10 8 6 4 0.5 NMOS I LIMIT PMOS I LIMIT 2 100 0 -50 125 -25 0 25 50 75 TEMPERATURE (C) 100 3310S1 G22 80 9.5 70 MINIMUM ON-TIME (ns) 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.0 -50 FB RISING FB FALLING -25 100 125 125 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 -50 FB RISING FB FALLING -25 0 25 50 75 TEMPERATURE (C) 100 125 3310S1 G24 Minimum On-Time 10.0 5.5 0 25 50 75 TEMPERATURE (C) 3310S1 G23 OV PGOOD Threshold PGOOD THRESHOLD OFFSET FROM VREF (%) VIN CURRENT (A) 14 1.0 -25 UV PGOOD Threshold 16 1.5 VIN = 2.25V VIN = 3.3V VIN = 5.5V 3310S1 G21 Switch Current Limit 2.0 0 25 50 75 TEMPERATURE (C) 0 -50 600 18 -25 1.0 3310S1 G20 2.5 0 -50 1.5 0.5 100 10.1 PGOOD THRESHOLD OFFSET FROM VREF (%) SOFT-START CURRENT (A) TA = 25C, VIN = 3.3V, unless otherwise noted. 0 25 50 75 TEMPERATURE (C) 100 125 60 50 40 30 20 VIN = 2.25V VIN = 3.3V VIN = 5.5V 10 0 -50 3310S1 G25 -25 0 25 50 75 TEMPERATURE (C) 100 125 3310S1 G26 Rev. E For more information www.analog.com 7 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 TYPICAL PERFORMANCE CHARACTERISTICS Start-Up Waveforms PulseSkipping Mode TA = 25C, VIN = 3.3V, unless otherwise noted. Start-Up Waveforms Forced Continuous Mode EN 2V/DIV VOUT 1V/DIV PGOOD 5V/DIV EN 2V/DIV VOUT 1V/DIV PGOOD 5V/DIV IL 1A/DIV IL 1A/DIV 3310S1 G27 400s/DIV 400s/DIV Switching Waveforms, PulseSkipping Mode 3310S1 G28 Switching Waveforms, Forced Continuous Mode SW 2V/DIV SW 2V/DIV IL 500mA/DIV IL 1A/DIV VOUT 10mV/DIV VOUT 10mV/DIV 3310S1 G29 200ns/DIV 200ns/DIV Load Transient Response Forced Continuous Mode Load Transient Response PulseSkipping Mode ILOAD 5A/DIV ILOAD 5A/DIV IL 5A/DIV IL 5A/DIV VOUT 20mV/DIV VOUT 20mV/DIV 40s/DIV 3.3VIN TO 1.2VOUT, 2MHz COUT = 110F, L = 100nH LOAD STEP: 0.1A TO 9A 1A/s SLEW RATE 3310S1 G30 3310S1 G31 40s/DIV 3310S1 G32 3.3VIN TO 1.2VOUT, 2MHz COUT = 110F, L = 100nH LOAD STEP: 1A TO 9A 1A/s SLEW RATE Rev. E 8 For more information www.analog.com LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VIN = 3.3V, unless otherwise noted. CISPR25 Conducted EMI Emissions with Class 5 Peak Limits (Voltage Method) 60 AMPLITUDE (dBV/m) 50 40 30 20 10 0 -10 -20 PEAK LIMIT PEAK 0 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 50 Radiated EMI Performance (CISPR25 Radiated Emissions Test with Class 5 Peak Limits) 50 HORIZONTAL POLARIZATION PEAK DETECTOR 45 40 35 AMPLITUDE (dBV/m) AMPLITUDE (dBV/m) VERTICAL POLARIZATION PEAK DETECTOR 45 40 30 25 20 15 10 35 30 25 20 15 10 PEAK LIMIT PEAK 5 0 110 3310S1 G33 LTC3310S DC2629A DEMO BOARD (WITH EMI FILTER INSTALLED) 3.3V INPUT TO 1.2V OUTPUT AT 7.5A, fSW = 2MHz Radiated EMI Performance (CISPR25 Radiated Emissions Test with Class 5 Peak Limits) 100 0 100 200 300 400 500 600 FREQUENCY (MHz) LTC3310S DC2629A DEMO BOARD (WITH EMI FILTER INSTALLED) 3.3V INPUT TO 1.2V OUTPUT AT 7.5A, fSW = 2MHz 700 800 900 1000 3310S1 G34 PEAK LIMIT PEAK 5 0 0 100 200 300 400 500 600 FREQUENCY (MHz) LTC3310S DC2629A DEMO BOARD (WITH EMI FILTER INSTALLED) 3.3V INPUT TO 1.2V OUTPUT AT 7.5A, fSW = 2MHz 700 800 900 1000 3310S1 G35 Rev. E For more information www.analog.com 9 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 PIN FUNCTIONS EN (Pin 1): The EN pin has a precision enable threshold with hysteresis. An external resistor divider, from VIN or from another supply, programs the threshold below which the LTC3310S will shut down. If the precision threshold is not used, directly connect the pin to VIN. When the EN pin is low, the LTC3310S enters a low current shutdown mode where all internal circuitry is disabled. Operation in Applications Information). The MODE/SYNC pin also programs the mode of operation: pulse skip or forced continuous. AGND (Pin 2): The AGND pin is the output voltage remote ground sense. Connect the AGND pin directly to the negative terminal of the output capacitor at the load and to the feedback divider resistor. RT (Pin 15): The RT pin sets the oscillator frequency with an external resistor to AGND or sets the phasing for multiphase operation. (see Multiphase Operation in Applications Information). VIN (Pins 3, 4, 11, 12): The VIN pins supply current to the internal circuitry and topside power switch. All of the VIN pins must be connected together with short, wide traces and bypassed to PGND with low ESR capacitors located as close as possible to the pins. The Silent Switcher 2 LTC3310S/LTC3310S-1 include internal bypass capacitors between VIN and PGND and VIN and AGND. The Silent Switcher 1 LTC3310/LTC3310-1 do not include these capacitors. It is recommended to include them externally. See the Applications Information section for more details. PGND (Pins 5, 10, 19): The PGND pins are the return path of the internal bottom side power switch. Connect the PGND pins together and to the exposed pad. Connect the negative terminal of the input capacitors as close to the PGND pins as possible. The PGND node is the main thermal highway and should be connected to a large PCB ground plane with many large vias. SW (Pins 6-9): The SW pins are the switching outputs of the internal power switches. Connect these pins together to the inductor with short, wide traces. MODE/SYNC (Pin 13): The MODE/SYNC pin facilitates multiphase operation and synchronization to an external clock. Depending on the mode of operation, the MODE/ SYNC pin either accepts an input clock pulse or outputs a clock pulse at its operating frequency. (see Multiphase PGOOD (Pin 14): The PGOOD pin is a power good pin and is the open drain output of an internal comparator. The PGOOD output is pulled low when VIN is above 2.25V and the part is in shutdown. SSTT (Pin 16): Soft-Start, Track, Temperature Monitor. An internal 10A current into an external capacitor on the soft-start pin programs the output voltage ramp rate during start-up. During the soft-start cycle, the FB pin voltage will track the SSTT pin voltage. When the soft-start cycle is complete, the tracking function is disabled, the internal reference resumes control of the error amplifier and the SSTT pin servos to a voltage representative of junction temperature. For a clean recovery from an output short circuit condition, the SSTT pin is pulled down to approximately 140mV above the VFB voltage and a new soft-start cycle is initiated. During shutdown and fault conditions, the SSTT pin is pulled to ground. ITH (Pin 17): The ITH pin is the compensation node for the output voltage regulation control loop. Compensation components connected to this pin are referenced to AGND. FB (Pin 18): The LTC3310S output voltage feedback pin is externally connected to the output voltage via a resistive divider and is internally connected to the inverting input of the error amplifier. The LTC3310S regulates the FB pin to 500mV. A phase lead capacitor connected between VFB and VOUT is used to optimize the transient response. VOUT (Pin 18): The output voltage pin is externally connected to the output voltage and is internally connected to a resistive divider. The LTC3310S-1 regulates the VOUT pin to 1.0V. Rev. E 10 For more information www.analog.com LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 BLOCK DIAGRAM VIN R1 EN R2 + - 0.4V RT RT INTERNAL REFERENCE S OSCILLATOR Q R 0.55V 0.5V 0.49V VIN SWITCH LOGIC AND ANTI-SHOOT THROUGH SW VIN CIN L VOUT COUT SENSE+ + - MODE/SYNC VIN 0.1F x2 PGND SENSE- SLOPE COMP RC + FB 0.5V RA CFF RB AGND CC 0.49V - + 0.55V + - 10A SSTT CSS + - ERROR AMP ITH FAULT + - VTEMP PGOOD FAULT 3310S1 BD Note 1: On the LTC3310S-1 the RA and RB resistors are internal. Note 2: The LTC3310/LTC3310-1 do not include internal bypass capacitors. Rev. E For more information www.analog.com 11 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 OPERATION Voltage Regulation The LTC3310S is a monolithic, constant frequency, current mode step-down DC/DC converter. An oscillator turns on the internal top power switch at the beginning of each clock cycle. Current in the inductor increases until the top switch current comparator trips and turns off the top power switch. The peak inductor current at which the top switch turns off is controlled by the voltage on the ITH node. The error amplifier servos the ITH node by comparing the voltage on the FB pin with an internal 500mV reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference leading the error amplifier to raise the ITH voltage until the average inductor current matches the new load current. When the top power switch turns off, the synchronous power switch turns on until the next clock cycle begins or, in pulse-skipping mode, inductor current falls to zero. If overload conditions result in excessive current flowing through the bottom switch, the next clock cycle will be delayed until switch current returns to a safe level. The output voltage is resistively divided externally to create a feedback voltage for the regulator. In high current operation, a ground offset may be present between the LTC3310S local ground and ground at the load. To overcome this offset, AGND should have a Kelvin connection to the load ground, and the lowest potential node of the resistor divider should be connected to AGND. The internal error amplifier senses the difference between this feedback voltage and a 0.5V AGND referenced voltage. This scheme overcomes any ground offsets between local ground and remote output ground, resulting in a more accurate output voltage. The LTC3310S allows for remote output ground deviations as much as 100mV with respect to local ground. If the EN pin is low, the LTC3310S is shut down and in a low quiescent current state. When the EN pin is above its threshold, the switching regulator will be enabled. Silent Switcher The "S" in LTC3310S/LTC3310S-1 refers to the second generation Silent Switcher 2 technology, allowing fast switching edges for high efficiency at high switching frequencies, while simultaneously achieving good EMI performance. Ceramic capacitors on VIN keep all the fast AC current loops small, improving EMI performance. The LTC3310S/LTC3310S-1 also include an internal bypass capacitor connected between VIN and AGND. The Silent Switcher 1 LTC3310/LTC3310-1 do not include any ceramiccapacitors. Synchronizing the Oscillator to an External Clock The LTC3310S's internal oscillator is synchronized through an internal PLL circuit to an external frequency by applying a square wave clock signal to the MODE/ SYNC pin. During synchronization, the top power switch turn-on is locked to the rising edge of the external frequency source. While synchronizing, the switcher operates in pulse skip mode. The slope compensation is automatically adapted to the external clock frequency. After detecting an external clock on the first rising edge of the MODE/SYNC pin, the internal PLL gradually adjusts its operating frequency to match the frequency and phase of the signal on the MODE/SYNC pin. When the external clock is removed, the LTC3310S detects the absence of the external clock within approximately 20s. During this time, the PLL will continue to provide clock cycles. Oncethe external clock removal has been detected, the oscillator gradually adjusts its operating frequency back to the default frequency. Mode Selection The MODE/SYNC pin either synchronizes the switching frequency to an external clock, is a clock output, or sets the PWM mode. The PWM modes of operation are either pulse skip or forced continuous. See Table6 or Table7 in the Applications Information section. In pulse skip mode, switching cycles are skipped at light loads to regulate the output voltage. During forced continuous mode, the top switch turns on every cycle and light load regulation is achieved by allowing negative inductor current. Rev. E 12 For more information www.analog.com LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 OPERATION Output Power Good Low Supply Operation Comparators monitoring the FB pin voltage pull the PGOOD pin low if the output voltage varies from the nominal set point or if a fault condition is present. The comparator includes voltage hysteresis. A time delay to report PGOOD is used to filter short duration output voltage transients. The LTC3310S is designed to operate down to an input supply voltage of 2.25V. An important thermal design consideration is that the RDS(ON) of the power switches increase at low VIN. Calculate the worst case LTC3310S power dissipation and die junction temperature at the lowest input voltages. Soft-Start/Tracking/Temperature Monitor Output Short-Circuit Protection and Recovery The soft-start tracking function facilitates supply sequencing, limits VIN inrush current and reduces start-up output overshoot. When soft-starting is completed, the SSTT pin parks itself at a voltage representative of the LTC3310S die junction temperature. The SSTT capacitor is reset during shutdown, VIN UVLO and thermal shutdown. See Application section. The peak inductor current level, at which the current comparator shuts off the top power switch, is controlled by the voltage on the ITH pin. If the output current increases, the error amplifier raises the ITH pin voltage until the average inductor current matches the load current. The LTC3310S clamps the maximum ITH pin voltage, thereby limiting the peak inductor current. Dropout Operation When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle because the voltage across the inductor is low. To keep the inductor current in control, a secondary limit is imposed on the valley of the inductor current. If the inductor current measured through the bottom power switch is greater than the IVALLEY(MAX) the top power switch will be held off. Subsequent switching cycles will be skipped until the inductor current is reduced below IVALLEY(MAX). As the input supply voltage approaches the output voltage, the duty cycle increases. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle, eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the DC voltage drop across the internal main P-channel MOSFET and the inductor. In many designs when the input voltage approaches the output voltage, the amplitude of the output ripple voltage increases from its normally low value. To avoid any increase in output ripple voltage under these conditions, it is recommended to utilize a resistor divider on the EN input and limit the VIN turn-on and turn-off thresholds to where the output ripple voltage is acceptable for the given application (typically 500mV above VOUT). Recovery from an output short circuit goes through a soft-start cycle. When VOUT goes below regulation, as defined by the PGOOD threshold, the SSTT voltage is pulled to a voltage just above the FB voltage. Because the SSTT pin is pulled low, a soft-start cycle is initiated once the output short is removed. Active Voltage Positioning The LTC3310S-1/LTC3310-1 includes Active Voltage Positioning (AVP) where the output voltage is dependent on load current. At light loads the output voltage is regulated above the nominal value. At full load the output voltage is regulated below the nominal value. The DC load regulation is adjusted to improve transient performance and reduce output capacitor requirements. Rev. E For more information www.analog.com 13 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 APPLICATIONS INFORMATION Refer to the Block Diagram for reference. switching frequency (fSW(MAX)) for a given application can be calculated as follows: FB Resistor Network The output voltage is programmed with a resistor divider between the output and the FB pin. Choose the resistor values according to: V RA = RB OUT - 1 (1) 500mV as shown in Figure1: VOUT BUCK SWITCHING FB REGULATOR RA RB CFF + COUT (OPTIONAL) 3310S1 F01 fSW (MAX ) = ( VOUT + VSW (BOT ) tON(MIN) VIN(MAX ) - VSW ( TOP ) + VSW (BOT ) ) (3) where VIN(MAX) is the maximum input voltage, VOUT is the output voltage, VSW(TOP) and VSW(BOT) are the internal switch drops and tON(MIN) is the minimum top switch on-time. This equation shows that a slower switching frequency is necessary to accommodate a high VIN/VOUT ratio. The LTC3310S is capable of a maximum duty cycle of 100%, therefore, the VIN-to-VOUT dropout is limited by the RDS(ON) of the top switch, the inductor DCR and the load current. Setting the Switching Frequency Figure1. Feedback Resistor Network Reference designators refer to the Block Diagram. 1% resistors are recommended to maintain output voltage accuracy. When optimizing the control loop for high bandwidth and optimal transient response add a phase-lead capacitor connected from VOUT to FB. Operating Frequency Selection and Trade-Offs Selection of the operating frequency is a trade-off between efficiency, component size, transient response and input voltage range. The advantage of high frequency operation is that smaller inductor and capacitor values may be used. Higher switching frequencies allow for higher control loop bandwidth and, therefore, faster transient response. The disadvantages of higher switching frequencies are lower efficiency, because of increased switching losses, and a smaller input voltage range, because of minimum switch on-time limitations. Although the maximum programmable switching frequency is 5MHz, the minimum on-time of the LTC3310S imposes a minimum operating duty cycle. The highest The LTC3310S uses a constant frequency PWM architecture. There are three methods to set the switching frequency. The first method is with a resistor (RT) tied from the RT pin to ground. The frequency can be programmed to switch from 500kHz to 5MHz. Table1 shows the necessary RT value for a desired switching frequency. The RT resistor required for a desired switching frequency is calculated using the following formula: RT = 568 * fSW(-1.08)(2) where RT is in k and fSW is the desired switching frequency in MHz. Table1. SW Frequency vs RT Value fSW (MHz) RT (k) 0.5 1210 1 549 2 274 2.2 243 3 178 4 130 5 100 Rev. E 14 For more information www.analog.com LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 APPLICATIONS INFORMATION The second method to set the LTC3310S switching frequency is by synchronizing the internal PLL circuit to an external frequency applied to the MODE/SYNC pin. The synchronization frequency range is 0.5MHz to 2.25MHz. The internal PLL starts up at the 2MHz default frequency. After detecting an external clock on the first rising edge of the MODE/SYNC pin, the internal PLL gradually adjusts its operating frequency to match the frequency and phase of the MODE/SYNC signal. The LTC3310S detects when the external clock is removed and will gradually adjust its operating frequency to the 2MHz default frequency. The third method of setting the LTC3310S switching frequency is to use the internal nominal 2MHz default clock. See Table4 for pin configuration. Inductor Selection and Maximum Output Current Considerations in choosing an inductor are inductance, RMS current rating, saturation current rating, DCR and core loss. A good first choice for the inductor value is: L VOUT VOUT VOUT * 1 for 3A * fSW VIN(MAX ) VIN(MAX ) L 0.25 * VIN(MAX ) VOUT for > 0.5 (5) 3A * fSW VIN(MAX ) 0.5(4) where ILOAD(MAX) is the maximum output load current for a given application and IL is the inductor ripple current calculated as: IL = VOUT V * 1- OUT (7) L * fSW VIN(MAX) where VIN(MAX) is the maximum application input voltage. To keep the efficiency high, choose an inductor with the lowest series resistance (DCR). The core material should be intended for high frequency applications. The LTC3310S limits the peak switch current in order to protect the switches and the system from overload faults. The inductor value must then be sufficiently large to supply the desired maximum output current, IOUT(MAX), which is a function of the switch current limit, ILIM, and the ripple current. IOUT (MAX ) = ILIM - IL (8) Therefore, the maximum output current that the LTC3310S will deliver depends on the switch current limit, the inductor value, and the input and output voltages. The inductor value may have to be increased if the inductor ripple current does not allow sufficient maximum output current (IOUT(MAX)) given the switching frequency, and maximum input voltage used in the desired application. Table2. Inductor Manufacturers VENDOR URL where fSW is the switching frequency in MHz, VIN is the input voltage and L is the inductor value in H. Coilcraft www.coilcraft.com Sumida www.sumida.com To avoid overheating of the inductor, choose an inductor with an RMS current rating that is greater than the maximum expected output load of the application. Overload and short circuit conditions may need to be taken into consideration. Toko www.toko.com Wurth Elektronik www.we-online.com Vishay www.vishay.com XFMRS www.xfmrs.com In addition, the saturation current (ISAT) rating of the inductor must be higher than the load current plus 1/2 of the inductor ripple current: 1 I SAT ILOAD(MAX ) + IL 2 (6) Input Capacitors Bypass the input of the LTC3310S with at least two ceramic capacitors close to the part, one on each side from VIN to PGND. These capacitors should be 0603 or 0805 in size. See layout section for more detail. X7R or Rev. E For more information www.analog.com 15 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 APPLICATIONS INFORMATION X5R capacitors are recommended for best performance across temperature and input voltage variations. Note that larger input capacitance is required when a lower switching frequency is used. If the input power source has high impedance, or there is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. This can be provided with a low performance electrolytic capacitor. A ceramic input capacitor combined with trace or cable inductance forms a high quality (under damped) tank circuit. If the LTC3310S circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LTC3310S's voltage rating. This situation is easily avoided (see Analog Devices Application Note 88). have very low equivalent series resistance (ESR) and provide the best ripple performance. For good starting values, see the Typical Application section. X5R or X7R type capacitors will provide low output ripple and good transient response. Transient performance is improved with a higher value output capacitor and the addition of a feedforward capacitor placed between VOUT and FB. Increasing the output capacitance will also decrease the output voltage ripple. A lower value of output capacitor saves space and cost but transient performance will suffer and may cause loop instability. See the Typical Application in this data sheet for suggested capacitor values. Multiphase Operation The LTC3310S is easily configurable for multiphase operation. See Table4. Table3. Ceramic Capacitor Manufacturers VENDOR URL AVX www.avxcorp.com Murata www.murata.com TDK www.tdk.com Taiyo Yuden www.t-yuden.com Samsung www.samsungsem.com Connecting the RT pin, of the master phase, to a resistor to AGND programs the frequency and configures the MODE/SYNC pin to become clock output used to drive the MODE/SYNC pin of the slave phase(s). Output Capacitor and Output Ripple The output capacitor has two essential functions. Along with the inductor, it filters the square wave, generated by the LTC3310S, to produce the DC output. In this role it determines the output ripple, thus, low impedance at the switching frequency is important. The second function is to store energy in order to satisfy transient loads and stabilize the LTC3310S's control loop. Ceramic capacitors Connecting the RT pin of the master phase to VIN configures the MODE/SYNC pin to become an input capable of accepting an external clock. The switching frequency defaults to the nominal 2MHz internal frequency when the external clock is unavailable, such as during start-up. Connecting the FB pin to VIN configures a phase as a slave. The MODE/SYNC becomes an input and the voltage control loop is disabled. The slave phase current control loop is still active and the peak current is controlled via the shared ITH node. Table4. LTC3310S Multiphase Configuration Master/Slave RT Pin FB Pin MODE/SYNC Pin Switching Frequency (fSW) Master VIN VOUT Divider Clock Input External Clock/2MHz Default Master Resistor to AGND VOUT Divider Clock Output RT programmed Slave VIN Divider VIN Clock Input External Clock Rev. E 16 For more information www.analog.com LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 APPLICATIONS INFORMATION The phasing of a slave phase relative to the master phase is programmed with a resistor divider on the RT pin. Use of 1% resistors is recommended. See Table5 for more information. Table5. LTC3310S Programming Slave Phase Angle Table6. LTC3310S Single Phase Configuration RT Pin Connection MODE/SYNC Pin Connection MODE of Operation Switching Frequency VIN Clock Input Pulse Skip External Clock VIN AGND Pulse Skip 2MHz Default VIN VIN Forced Continuous 2MHz Default Resistor to AGND Clock Output Pulse Skip RT Programmed SYNC Phase Angle R3 Ratio R4 Ratio R3 Example R4 Example 0 0 NA 0 NA 90 3*R R 301k 100k LTC3310S-1 Mode of Operation 120 7*R 5*R 243k 174k 180 NA 0 NA 0 240 5*R 7*R 174k 243k 270 R 3*R 100k 300k For most configurations, the LTC3310S-1 operates in forced continuous mode. While in forced continuous mode, regulation at low currents is achieved by allowing negative inductor current. Switching cycles are not skipped. When configured for master/slave operation, the slave regulator(s) operates in pulse skip mode where negative inductor currents are disallowed and regulation at low currents is achieved by skipping switching cycles. VIN Table7. LTC3310S-1 Single Phase Configuration FB LTC3310S The LTC3310S-1 operates in pulse skip mode when both RT and MODE/SYNC pins are connected to VIN. In this mode, the switching frequency is set with the nominal 2MHz internal clock. While in pulse skip mode negative current is disallowed and regulation at low currents is achieved by skipping switching cycles. R3 RT R4 3310S1 F02 AGND Figure2. Phase Programming LTC3310S Mode of Operation RT Pin Connection MODE/SYNC Pin Connection MODE of Operation Switching Frequency VIN Clock Input Forced Continuous External Clock VIN AGND Forced Continuous 2MHz Default VIN VIN Pulse Skip 2MHz Default Resistor to AGND Clock Output Forced Continuous RT Programmed For most configurations, the LTC3310S operates in pulse skip mode where negative inductor current is disallowed and regulation at low currents is achieved by skipping switching cycles. The LTC3310S operates in forced continuous mode when both the RT and MODE/SYNC pins are connected to VIN. In this mode, the switching frequency is set with the nominal 2MHz internal clock. While in forced continuous mode, regulation at low currents is achieved by allowing negative inductor current. Switching cycles are not skipped. Rev. E For more information www.analog.com 17 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 APPLICATIONS INFORMATION Synchronization To synchronize the LTC3310S oscillator to an external frequency, configure the MODE/SYNC pin as an input by connecting the RT pin to VIN. Drive the MODE/SYNC pin with a square wave in the frequency range of 500 kHz to 2.25MHz range, an amplitude greater than 1.2V and less than 0.4V with a pulse width greater than 40ns. The LTC3310S phase locked loop (PLL) will synchronize the internal oscillator to the clock applied to the MODE/ SYNC pin. At start up, before the LTC3310S recognizes the external clock applied to MODE/SYNC, the LTC3310S will switch at its default frequency of 2MHz. Once the externally applied clock is recognized, the switching frequency will gradually transition from the default frequency to the applied frequency. If the external clock is removed, the LTC3310S will slowly transition back to the default frequency. The LTC3310S operates in pulse skip mode during synchronization. An internal 200k resistor on MODE/SYNC pin to AGND allows the MODE/SYNC pin to be left floating. Transient Response and Loop Compensation When determining the compensation components, CFF, RC, and CC, control loop stability and transient response are the two main considerations. The LTC3310S has been designed to operate at a high bandwidth for fast transient response capability. Operating at a high loop bandwidth reduces the output capacitance required to meet transient response requirements. Applying a load transient and monitoring the response of the system or using a network analyzer to measure the actual loop response are two ways to verify and optimize the control loop stability. LTpowerCAD(R) is a useful tool to help optimize the compensation components. When using the load transient response method to stabilize the control loop, apply an output current pulse of 20% to 100% of full load current having a rise time of 1s. This will produce a transient on the output voltage and ITH pin waveforms. Switching regulators take multiple cycles to respond to a step in load current. When a load step occurs, VOUT is immediately perturbed, generating a feedback error signal used by the regulator to return VOUT to its steady-statevalue. During this recovery time, monitor VOUT for overshoot or ringing that would indicate a stability problem. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The gain of the loop increases with the RC and the bandwidth of the loop increases with decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. In addition, adding a feed forward capacitor, CFF, improves the high frequency response. Capacitor CFF provides phase lead by creating a high frequency zero with RA to improve the phase margin. The compensation components of the typical application circuits are a good starting point for component values. On the LTC3310S-1 an internal voltage regulation adjustment circuit modifies the regulated output voltage based on load current. This circuit effectively increases the output impedance of the supply, reducing the output voltage during a heavy load, and raising the voltage during light loads. The output is centered at 1V at an average load current of 4.5A; the regulated output voltage varies typically, 2.4mV per Amp of average load current. This variation in output voltage helps compensate for the short-duration voltage spikes created during a fast load step, reducing the overall voltage perturbation in response to these loadsteps. The output voltage settling behavior is related to the stability of the closed-loop system. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Analog Devices Application Note 76. Rev. E 18 For more information www.analog.com LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 APPLICATIONS INFORMATION Output Overvoltage Protection During an output overvoltage event, when the FB pin voltage is greater than 110% of nominal, the LTC3310S top power switch will be turned off. If the output remains out of regulation for more than 100s, the PGOOD pin will be pulled low. An output overvoltage event should not happen under normal operating conditions. Output Voltage Sensing The LTC3310S AGND pin is the ground reference for the internal analog circuitry, including the bandgap voltage reference. To achieve good load regulation, connect the AGND pin to the negative terminal of the output capacitor (COUT) at the load. A drop in the high current power ground return path will be compensated. All of the signal components, such as the FB resistor dividers and softstart capacitor, should be referenced to the AGND node. The AGND node carries very little current and, therefore, can be a minimal size trace. See the example PCB Layout for more information. Enable Threshold Programming The LTC3310S has a precision threshold enable pin to enable or disable switching. When forced low, the LTC3310S enters a low current shutdown mode. The rising threshold of the EN comparator is 400mV, with 60mV of hysteresis. Connect the EN pin to VIN if the shutdown feature is not used. Adding a resistor divider from VIN to EN programs the LTC3310S to regulate the output only when VIN is above a desired voltage (see the Block Diagram). Typically, this threshold, VIN(EN), is used in situations where the input supply is current limited or has a relatively high source resistance. A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. The VIN(EN) threshold prevents the regulator from operating at source voltages where problems may occur. This threshold can be adjusted by setting the values R1 and R2 such that they satisfy the followingequation: R1 VIN(EN) = + 1 * 400mV (9) R2 where the LTC3310S will remain off until VIN is above VIN(EN). Due to the comparator's hysteresis, switching will not stop until the input falls slightly below VIN(EN). Alternatively, a resistor divider from an output of another regulator to the enable pin of the LTC3310S provides event-based power-up sequencing, enabling the LTC3310S when the output of the other regulator reaches a predetermined level. Output Voltage Tracking and Soft-Start The LTC3310S allows the user to program its output voltage ramp rate by means of the SSTT pin. An internal 10A pulls up the SSTT pin. Putting an external capacitor on SSTT enables soft-starting the output to prevent current surge on the input supply and output voltage overshoot. During the soft-start ramp, the output voltage will proportionally track the SSTT pin voltage. When the soft-start is complete, the pin will servo to a voltage proportional to the LTC3310S junction temperature. See Figure3 showing the SSTT pin operating range. The soft-start time is calculated as follows: t SS = CSS * 500mV 10A (10) For output tracking applications, SSTT can be externally driven by another voltage source. From 0V to 0.5V, the SSTT voltage will override the internal 0.5V reference input to the error amplifier, thus regulating the FB pin voltage to that of SSTT pin. When SSTT is above 0.5V, tracking is disabled and the feedback voltage will regulate to the internal reference voltage An active pull-down circuit is connected to the SSTT pin to discharge the external soft-start capacitor in the case of fault conditions. The ramp will restart when the fault is cleared. Fault conditions that clear the soft-start capacitor are the EN/UV pin transitioning low, VIN voltage falling too low or thermal shutdown. Rev. E For more information www.analog.com 19 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 APPLICATIONS INFORMATION Temperature Monitor Output Power Good Once the soft-start cycle has completed and the output power good flag thrown, the SSTT pin reports the die junction temperature. The LTC3310S regulates the SSTT pin to a voltage proportional to the junction temperature. While reporting the temperature, the SSTT voltage is not valid below 1V. The junction temperature is calculated with the following formula: When the LTC3310S's output voltage is within the -2/+10% window of the nominal regulation voltage the output is considered good and the open-drain PGOOD pin goes high impedance and is typically pulled high with an external resistor. Otherwise, the internal pull-down device will pull the PGOOD pin low. To prevent glitching both the upper and lower thresholds, include 1% of hysteresis as well as a built in time delay, typically 100s. The PGOOD pin is also actively pulled low during fault conditions: EN pin is low, VIN is too low or in thermal shutdown. TJ (C) = VSSTT - 273 4mV The following procedure is used for a more accurate measurement of the junction temperature: 1.Measure the ambient temperature TA. 2.Measure the SSTT voltage while in pulse skip mode with the VOUT pulled up slightly higher than the regulatedVOUT. 3.Calculate the slope of the temperature sensing circuit as follows: Slope (mV / C) = VSSTT TA + 273 4. Calculate the junction temperature with the new calibrated slope. When the output voltage goes out of regulation and the power good pin is pulled low, the soft-start pin no longer reports the temperature. 125 SSTT PIN VOLTAGE OPERATING RANGE TEMP MONITOR ~4mV/C 50 25 0.6 0.5 0.4 FB 0.3 (V) 0.2 0.1 0 The peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the ITH pin. If the output current increases, the error amplifier raises the ITH pin voltage until the average inductor current matches the new load current. In normal operation, the LTC3310S clamps the maximum ITH pin voltage. When the output is shorted to ground, the inductor current decays very slowly during the switch off time because of the low voltage across the inductor. To keep the current in control, a secondary limit is also imposed on the valley inductor current. If the inductor current measured through the bottom power switch increases beyond IVALLEY(MAX), the top power switch will be held off and switching cycles will be skipped until the inductor current is reduced. Recovery from a short circuit can be abrupt and because the output is shorted and below regulation the regulator is requesting the maximum current to charge the output. When the short circuit condition is removed, the inductor current could cause an extreme voltage overshoot in the output. The LTC3310S addresses this potential issue by regulating the SSTT voltage just above the FB voltage anytime the output is out of regulation. Therefore, a recovery from an output short circuit goes through a soft-start cycle. The output ramp is controlled and the overshoot is minimized. 150 DIE TEMP 100 (C) 75 Output Short Circuit Protection and Recovery SOFT-START AND TRACKING 0 0.1 0.2 0.3 0.4 0.5 0.6 1.2 1.3 1.4 1.5 1.6 1.7 SSTT (V) 3310S1 F03 Figure3. Soft-Start and Temperature Monitor Operation 20 For more information www.analog.com Rev. E LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 APPLICATIONS INFORMATION Low EMI PCB Layout The LTC3310S is specifically designed to minimize EMI/ EMC emissions and also to maximize efficiency when switching at high frequencies. For optimal performance, the LTC3310S/LTC3310 requires the use of multiple VIN bypass capacitors. Many designs will benefit from additional 0402 ceramic capacitors (CIN3 and CIN4) placed between the larger bulk input ceramic capacitors as shown in Figure4. These capacitors range from 0.1F to 0.47F and are often needed for high frequency designs. If the additional 0402 capacitors are not added to the layout then the bulk input ceramic capacitors should be moved as close as possible to the VIN pins. The LTC3310/LTC3310-1 does not have any internal bypass capacitors and hence requires three additional 0201 external capacitors (CIN5, CIN6, and CIN7), as shown in Figure 5. Place these capacitors as close as possible to the ICs. To avoid noise coupling into FB, the resistor divider should be placed near the FB and AGND pins and physically close to the LTC3310S. The remote output and ground traces should be routed together as a differential pair to the remote output. These traces should be terminated as close as physically possible to the remote output point that is to be accurately regulated through remote differential sensing. See Figure4 and Figure5 for a recommended PCB layouts. Large, switched currents flow in the LTC3310S VIN, SW and PGND pins and the input capacitors. The loops formed by the input capacitors should be as small as possible by placing the capacitors adjacent to the VIN and PGND pins. Place the input capacitors, inductor and output capacitors on the same layer of the circuit board. Place a local, unbroken ground plane under the application circuit on the layer closest to the surface layer. The SW node should be as short as possible. Finally, keep the FB and RT nodes small and away from the noisy SWnode. GROUND PLANE ON LAYER 2 VIN CC1 CC1 CSS CFF RT CSS CFF CC2 RB RC 14 18 CC2 RB 1 CIN7 15 CIN3 14 18 6 9 (OPT) 15 CIN6 CIN4 5 CIN1 RC 1 19 19 10 CIN5 5 CIN1 CIN2 6 9 10 CIN2 (OPT) GND GND GND TO VOUT & GND REMOTE SENSE RT RA RA COUT1 GROUND PLANE ON LAYER 2 VIN L VOUT GND COUT1 COUT2 3310S1 F04 Figure4. Recommended PCB Layout for the LTC3310S TO VOUT & GND REMOTE SENSE L VOUT COUT2 3310S1 F05 Figure5. Recommended PCB Layout for the LTC3310 Rev. E For more information www.analog.com 21 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 APPLICATIONS INFORMATION High Temperature Considerations heat dissipated by the LTC3310S. Placing additional vias can reduce thermal resistance further. The maximum load current should be derated as the ambient temperature approaches the maximum junction rating. Power dissipation within the LTC3310S can be estimated by calculating the total power loss from an efficiency measurement and subtracting the inductor loss. The die temperature is monitored with the SSTT pin. For higher ambient temperatures, care should be taken in the layout of the PCB to ensure good heat sinking of the LTC3310S. The PGND pins and the exposed pad on the bottom of the package should be soldered to a ground plane. This ground should be tied to large copper layers below with many thermal vias; these layers will spread TYPICAL APPLICATIONS Dual Phase 5V to 3.3V, 20A VIN 4.5V TO 5.5V 1F 47F 0.22F 1M 0.22F VIN EN PGOOD 100k SW 100k ITH SSTT 4.7pF 15k 274k FB RT AGND PGND PGOOD VOUT 3.3V 20A 200nH LTC3310S MODE/SYNC 1.0pF 47F 22F x2 48.7k 274k 0.1F 390pF VIN 1F 47F 0.22F 47F 0.22F EN VIN PGOOD MODE/SYNC LTC3310S ITH SW FB 200nH 22F x2 VIN 1.0pF AGND PGND RT 180 3310S1 TA03 L = COILCRAFT, XEL4030-201ME Rev. E 22 For more information www.analog.com LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 TYPICAL APPLICATIONS Three Phase, 0.6V, 30A VIN 2.25V TO 4.5V 1F 47F 0.22F VIN EN 100k PGOOD MODE/SYNC SW 0.22F 100nH 12pF LTC3310S ITH 10k 86.6k FB SSTT 390pF 47F RT AGND PGND 432k 47F x2 10F x2 VOUT 0.6V 30A 274K 0.1F VIN 1F 47F 0.22F EN VIN 0.22F PGOOD MODE/SYNC SW LTC3310S ITH 47F 100nH 47F x2 10F x2 VIN FB 243k 120 AGND PGND RT 174k VIN 1F 47F 0.22F EN VIN 0.22F PGOOD MODE/SYNC LTC3310S ITH SW 47F x2 10F x2 VIN FB 174k 240 AGND PGND RT 3310S1 TA04 47F 100nH 243k L = WURTH ELEKTRONIK, 744373240010 Rev. E For more information www.analog.com 23 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 TYPICAL APPLICATIONS Four Phase, 2MHz, 1.2V, 40A VIN 2.25V TO 5.5V 1F 47F 0.22F VIN EN 0.22F PGOOD MODE/SYNC SW 100nH 6.8pF LTC3310S ITH 10k SSTT 390pF FB RT AGND PGND 47F 140k 22F x2 10F x2 100k 274k VOUT 1.2V 40A 0.1F VIN 1F 47F 0.22F EN VIN 0.22F PGOOD MODE/SYNC SW LTC3310S ITH 47F 100nH 22F x2 10F x2 VIN FB 301k 90 AGND PGND RT 100k VIN 1F 47F 0.22F EN VIN 0.22F PGOOD MODE/SYNC 100nH SW LTC3310S ITH FB 47F 22F x2 10F x2 VIN 180 AGND PGND RT VIN 1F 47F 0.22F EN VIN PGOOD MODE/SYNC LTC3310S ITH SW 0.22F 100nH 22F x2 10F x2 VIN FB 100k 270 AGND PGND RT 3310S1 TA05 47F 301k L = COILCRAFT, XEL4030-101ME Rev. E 24 For more information www.analog.com LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 TYPICAL APPLICATIONS Four Phase, 2MHz, 1.2V, 40A Driven with External Clock VIN 2.25V TO 5.5V 1F 47F 0.22F VIN EN 0.22F PGOOD MODE/SYNC EXTERNAL CLOCK SW 100nH 6.8pF LTC3310S ITH 10k SSTT 390pF 47F FB RT AGND PGND VIN 140k 22F x2 10F x2 100k VOUT 1.2V 40A 0.1F VIN 1F 47F 0.22F EN VIN 0.22F PGOOD MODE/SYNC SW LTC3310S ITH 47F 100nH 22F x2 10F x2 VIN FB 301k 90 AGND PGND RT 100k VIN 1F 47F 0.22F EN VIN 0.22F PGOOD MODE/SYNC 100nH SW LTC3310S ITH 47F 22F x2 10F x2 VIN FB 180 AGND PGND RT VIN 1F 47F 0.22F EN VIN PGOOD MODE/SYNC LTC3310S ITH SW 0.22F 47F 100nH 22F x2 10F x2 VIN FB 100k 270 AGND PGND RT 3310S1 TA06 301k L = COILCRAFT, XEL4030-101ME Rev. E For more information www.analog.com 25 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 TYPICAL APPLICATIONS LTC3310S, 5MHz, 1V, 10A VIN 3.0V TO 3.6V 22F 0.22F 649k 0.22F VIN EN 22F PGOOD 100k 50nH MODE/SYNC 0.1F 10pF 100k 22F x3 FB LTC3310S SSTT VOUT 1V 10A SW 100k AGND ITH 10pF 15k RT PGND 220pF 100k 3310S1 TA07 L = XF303020LT-50NM, XFMR INC. LTC3310S, 2MHz, 3.3V, 10A, Forced Continuous VIN 4.5V TO 5.5V 22F 22F 1M VIN EN PGOOD 100k VOUT PGOOD 100k VIN 200nH MODE/SYNC 15pF LTC3310S SSTT 0.1F SW 562k FB 100k ITH VOUT 3.3V 10A 22F x2 AGND 10k RT PGND 220pF VIN 3310S1 TA08 L = COILCRAFT, XEL4030-201ME LTC3310, 1.2V 10A, Step-Down Converter VIN 2.25V TO 5.5V 22F 0.1F 0.1F EN VIN MODE/SYNC PGOOD LTC3310 100nH SW 15pF FB SSTT 0.1F VIN 0.1F 140k 100k VOUT 1.2V 10A 22F x3 AGND ITH PGND 10k 22F RT 3310S1 TA09 274k 220pF L = XEL4030-101ME, COILCRAFT Rev. E 26 For more information www.analog.com LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 TYPICAL APPLICATIONS LTC3310S, High Efficiency, 2MHz, 0.5V, 10A, Pulse Skip, Low Part Count VIN 2.25V TO 4.3V 22F 22F VIN EN PGOOD 100nH MODE/SYNC 0.1F VOUT 0.5V 10A SW SSTT 47F x4 FB LTC3310S ITH 1M AGND 15k 270pF RT PGND VIN 3310S1 TA10 L = COILCRAFT, XEL4030-101ME LTC3310S-1, 2MHz, 1.0V, Forced Continuous 1.5A DC to 7.5A Step Load 6A/s Transient, <3% Total Variation VIN 3.3V 10% 22F 0.1F 1M VIN EN 249k PGOOD 100k 100nH SW SSTT LTC3310S-1 330pF VOUT VOUT 1V 10A 47F x5 VOUT ITH 13.3k 22F PGOOD MODE/SYNC 0.1F 0.1F AGND RT PGND VIN 3310S1 TA11 L = COILCRAFT, XEL4030-101ME Rev. E For more information www.analog.com 27 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 TYPICAL APPLICATIONS LTC3310-1, 2MHz, 1.0V, Forced Continuous 1.5A DC to 7.5A Step Load 6A/s Transient, <3% Total Variation VIN 3.3V 10% 22F 0.1F 1M VIN EN 249k PGOOD 100k VOUT PGOOD MODE/SYNC 100nH VOUT 1V 10A SW 0.1F SSTT LTC3310-1 3.3pF 330pF VIN VOUT 0.1F ITH 15k 22F 0.1F 47F x5 AGND RT PGND VIN 3310S1 TA12a L = COILCRAFT, XEL4030-101ME Forced Continuous Mode IOUT 2A/DIV 1.0V VOUT 10mV/DIV 10s/DIV 3310S1 TA12b LTC3310-1 3.3VIN TO 1.0VOUT LOADSTEP 1.5A TO 7.5A 6A/s Rev. E 28 For more information www.analog.com LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 TYPICAL APPLICATIONS LTC3310S-1, 3MHz, 1.0V, 10A VIN 2.25V TO 5.5V 22F 0.1F 0.1F VIN EN PGOOD 72nH MODE/SYNC 0.1F 22F VOUT 1.0V 10A SW SSTT LTC3310S-1 ITH 22F x3 VOUT AGND 2.80k 680pF PGND RT 3310S1 TA13 178k L = COILCRAFT, XEL3515-720MEB LTC3310S-1, 5MHz, 1.0V, 10A VIN 2.25V TO 5V 22F 0.1F 0.1F EN VIN MODE/SYNC PGOOD LTC3310S-1 50nH SW VOUT 22F VOUT 1.0V 10A 22F x3 SSTT 0.1F AGND ITH PGND 3.74k RT 3310S1 TA14 100k 1.5pF L = XF303020LT-50NM, XFMR INC. Rev. E For more information www.analog.com 29 3.50 0.05 4 For more information www.analog.com 0.70 0.25 PACKAGE TOP VIEW 0.20 1.51 3.50 0.05 0.20 1.70 0.39 SUGGESTED PCB LAYOUT TOP VIEW 0.7500 aaa Z 2x E 0.2500 0.0000 0.2500 PIN 1 CORNER 0.7500 Y aaa Z 1.0000 0.5000 0.0000 0.5000 1.0000 PACKAGE OUTLINE X D 2x SYMBOL A A1 L b D E D1 E1 e H1 H2 aaa bbb ccc ddd eee fff DETAIL B H2 MOLD CAP MIN 0.85 0.01 0.30 0.22 H1 NOM 0.94 0.02 0.40 0.25 3.00 3.00 1.51 1.70 0.50 0.24 REF 0.70 REF DIMENSIONS 18b eee M Z X Y fff M Z DETAIL C SUBSTRATE DETAIL C A1 18x Z 0.10 0.10 0.08 0.10 0.15 0.08 MAX 1.03 0.03 0.50 0.28 e/2 e L SUBSTRATE THK MOLD CAP HT NOTES DETAIL A DETAIL B A (Reference LTC DWG # 05-08-1548 Rev C) ddd Z Z 30 b 10 14 b E1 e 0.250 6 6 DETAIL A 18 PACKAGE BOTTOM VIEW 9 0.250 0.440 15 5 1 3 SEE NOTES e PIN 1 NOTCH 0.25 x 45 DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 4 TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION LTXXXXXX LQFN 18 1218 REV C THE EXPOSED HEAT FEATURE MAY HAVE OPTIONAL CORNER RADII COMPONENT PIN 1 6 5. PRIMARY DATUM -Z- IS SEATING PLANE METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN SO AS NOT TO OBSCURE THESE TERMINIALS AND HEAT FEATURES 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 D1 ccc M Z X Y ccc M Z X Y LQFN Package 18-Lead (3mm x 3mm x 0.94mm) LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 PACKAGE DESCRIPTION Rev. E // bbb Z LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 REVISION HISTORY REV DATE DESCRIPTION A 12/18 Added Thermal Package Information 2 Modified Order Information 2 B C 06/19 03/20 Changed Pin Configuration Package Description 2 Changed Inductor 23 Added Typical Performance Curves 5-9 Modified Package Drawing 28 Added LTC3310S-1 Option to Order Information 2 Modify Pin Configuration, Abs Max Ratings 2 Added LTC3310S-1 Option Specifications 4-8 Added LTC3310S-1 Option VOUT Pin Function 10 Modified Block Diagram for LTC3310S-1 Option 11 Modified Applications Section for LTC3310S-1 Option E 06/20 09/20 3 Added LTC3310S-1 Option Typ Performance Curves Modified Operation Section for LTC3310S-1 Option D PAGE NUMBER 13 14-21 Added LTC3310S-1 Option Application Circuits 28 Added LTC3310 and LTC3310-1 Part Numbers All Added Condition IOUT = 4A to Regulated Output Voltage LTC3310S-1 3 Modified VIN Pin Functions Section 10 Added Note 2 on Block Diagram 11 Modified Voltage Regulation Section 12 Modified Low EMI PCB Layout Section 21 Added LTC3310-1 #W in Order Info 3 Figs 4 & 5, added line drawings with label "To VOUT & GND Remote Sense" on PCB layout 21 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 31 LTC3310S/LTC3310S-1 LTC3310/LTC3310-1 TYPICAL APPLICATION LTC3310S, 3MHz, 1.0V, 10A VIN 2.25V TO 5.5V 22F 22F VIN EN 0.1F PGOOD 72nH MODE/SYNC SW SSTT 10pF 100k FB LTC3310S 100k ITH VOUT 1.0V 10A 22F x3 AGND 15k 220pF RT PGND 3310S1 TA02 178k L = COILCRAFT, XEL3515-720MEB RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3636/LTC3636-1 Dual Channel 6A, 20V Monolithic Synchronous 95% Efficiency, VIN: 3.1V to 20V, VOUT(MIN) = 0.6V (LTC3636), 1.8V(LTC3636-1), IQ = 1.3mA, ISD < 13A, 4mmx5mm QFN-28 Step-Down Regulator LTC3615/LTC3615-1 Dual Channel 5.5V, 3A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 94% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 130A, ISD < 1A, 4mmx4mm QFN-24 Package LTC7150S 20V, 20A Synchronous Step-Down SilentSwitcher2 Regulator 92% Efficiency, VIN: 3.1V to 20V, VOUT(MIN) = 0.6V, IQ = 2mA, ISD 40A, Differential Remote Sense, 6mmx5mm BGA LT8642S 18V, 10A Synchronous Step-Down SilentSwitcher 2 Regulator 96% Efficiency, VIN: 2.8V to 18V, VOUT(MIN) = 0.6V, IQ = 240A, ISD < 1A, 4mmx4mm LQFN-24 LT8640S 42V, 6A Synchronous Step-Down 96% Efficiency, VIN: 3.4V to 42V, VOUT(MIN) = 1.0V, IQ = 230A, ISD < 1A, SilentSwitcher 2 with 2.5A Quiescent Current 4mmx4mm LQFN-24 LT8650S Dual Channel 4A, 42V, Synchronous Step-Down Silent Switcher 2 with 6.2A Quiescent Current 94.5% Efficiency, VIN: 3V to 42V, VOUT(MIN) = 0.8V, IQ = 5mA, ISD < 2A, 4mmx6mm LQFN-32 LTC7151S 20V, 15A Synchronous Step-Down SilentSwitcher 2 Regulator 92.5% Efficiency, VIN: 3.1V to 20V, VOUT(MIN) = 0.5V, IQ = 2mA, ISD < 20A, 4mmx5mm LQFN-28 LTC3307A 5V, 3A Synchronous Step-Down SilentSwitcher in 2mmx2mm LQFN Monolithic Synchronous Step-Down DC/DC Capable of Supplying 3A at Switching Frequencies up to 3MHz. SilentSwitcher Architecture for Ultralow EMI Emissions. 2.25V to 5.5V Input Operating Range. 0.5V to VIN Output Voltage Range with 1% Accuracy. PGOOD Indication, RTProgramming, SYNC Input. 2mm x 2mmLQFN. LTC3308A 5V, 4A Synchronous Step-Down SilentSwitcher in 2mmx2mm LQFN Monolithic Synchronous Step-Down DC/DC Capable of Supplying 4A at Switching Frequencies up to 3MHz. SilentSwitcher Architecture for Ultralow EMI Emissions. 2.25V to 5.5V Input Operating Range. 0.5V to VIN Output Voltage Range with 1% Accuracy. PGOOD Indication, RTProgramming, SYNC Input. 2mm x 2mmLQFN. LTC3309A 5A, 6A, Synchronous Step-Down DC/DC in 2mm x 2mm LQFN Monolithic Synchronous Step-Down DC/DC Capable of Supplying 6A at Switching Frequencies Up to 3MHz. Silent Switcher Architecture for Ultralow EMI Emissions. 2.25V to 5.5V Input Operating Range. 0.5V to VIN Output Voltage Range with 1% Accuracy. PGOOD Indication, RT Programming, SYNC Input. 2mm x 2mm LQFN LTC3315A Dual 5V, 2A Synchronous Step-Down DC/DC in 2mm x 2mm LQFN Dual Monolithic Synchronous Step-Down Voltage Regulators Each Capable of Supplying 2A at Switching Frequencies Up to 3MHz. 2.25V to 5.5V Input Operating Range. 0.5V to VIN Output Voltage Range with 1% Accuracy. PGOOD Indication, SYNC Input. 2mm x 2mm LQFN Rev. E 32 09/20 www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2018-2020