LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
1
Rev. E
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TYPICAL APPLICATION
FEATURES DESCRIPTION
The LTC
®
3310S is a very small, low noise, monolithic
step-down DC/DC converter capable of providing up to
10A of output current from a 2.25V to 5.5V input supply.
The device employs Silent Switcher 2 architecture with
internal hot loop bypass capacitors to achieve both low
EMI and high efficiency at switching frequencies as high
as 5MHz. For systems with higher power requirements,
multi-phasing parallel converters is readily implemented.
The LTC3310S uses a constant-frequency, peak current
mode control architecture for fast transient response. A
500mV reference allows for low voltage outputs. 100%
duty cycle operation delivers low drop out.
Other features include a power good signal when the out-
put is in regulation, precision enable threshold, output
overvoltage protection, thermal shutdown, a temperature
monitor, clock synchronization, mode selection and out-
put short circuit protection.
1.2V 10A Step-Down Converter Efficiency vs Load Current
APPLICATIONS
n Silent Switcher
®
2 Architecture: Ultralow EMI
Emissions (LTC3310S and LTC3310S-1)
n High Efficiency: 4.5mΩ NMOS and 16mΩ PMOS
n Wide Bandwidth, Fast Transient Response
n Safely Tolerates Inductor Saturation in Overload
n VIN Range: 2.25V to 5.5V
n VOUT Range: 0.5V to VIN
n VOUT Accuracy: ±1% with Remote Sense
n Peak Current Mode Control
n 35ns Minimum On-Time
n Programmable Frequency to 5MHz
n Shutdown Current: 1µA
n Precision 400mV Enable Threshold
n Output Soft-Start with Voltage Tracking
n Power Good Output
n Die Temperature Monitor
n Configurable for Paralleling Power Stages
n Thermally-Enhanced 3mm × 3mm LQFN Package
n AEC-Q100 Qualified for Automotive Applications
n Automotive/Industrial/Communications
n Servers, Telecom Power Supplies
n Distributed DC Power Systems (POL)
n FPGA, ASIC, µP Core Supplies All registered trademarks and trademarks are the property of their respective owners.
3310S1 TA01a
140k
22µF
×3
100k
V
OUT
1.2V
10A
15pF
274k
L = XEL4030-101ME, COILCRAFT
22µF 22µF
0.1µF
SW
FB
AGND
RT
EN
MODE/SYNC
PGOOD
SSTT
ITH
10k
220pF
VIN
V
IN
2.25V TO 5V
PGND
LTC3310S
100nH
LOAD CURRENT (A)
0
EFFICIENCY (%)
100
10
90
70
50
30
80
60
40
POWER LOSS (W)
20
05 93 7
3310S1 TA01b
104 82 61
VIN = 3.3V
VOUT = 1.2V
fOSC = 2MHz
3.0
0.3
2.7
2.1
1.5
0.9
2.4
1.8
1.2
0.6
0
POWER LOSS
EFFICIENCY
5V, 10A Synchronous Step-Down
Silent Switcher 2 in 3mm × 3mm LQFN
PART NUMBER Silent Switcher VOUT
LTC3310S SS2 Adjustable
LTC3310S-1 SS2 Fixed 1V
LTC3310 SS1 Adjustable
LTC3310-1 SS1 Fixed 1V
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
2
Rev. E
For more information www.analog.com
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VIN ............................................................. –0.3V to 6V
EN, SSTT ............. –0.3V to Lesser of (VIN + 0.3V) or 6V
MODE/SYNC ........ –0.3V to Lesser of (VIN + 0.3V) or 6V
RT ........................ –0.3V to Lesser of (VIN + 0.3V) or 6V
FB or VOUT ........... –0.3V to Lesser of (VIN + 0.3V) or 6V
PGOOD ......................................................... –0.3V to 6V
IPGOOD ......................................................................5mA
Operating Junction Temperature Range (Notes 2, 3)
LTC3310SE/LTC3310SE-1 .................. –40°C to 125°C
LTC3310SI/LTC3310SI-1 .................... –40°C to 125°C
LTC3310J/LTC3310J-1 ....................... –40°C to 150°C
LTC3310H/LTC3310H-1 ..................... –40°C to 150°C
Storage Temperature............................. –65˚C to +150°C
Maximum Reflow (Package Body) Temperature ... 260°C
(Note 1)
TOP VIEW
19
PGND
EN
AGND
VIN
VIN
PGND
PGOOD
MODE/SYNC
VIN
VIN
PGND
FB or VOUT
ITH
SSTT
RT
SW
SW
SW
SW
LQFN PACKAGE
18-LEAD (3mm × 3mm)
θ
JA = 42°C/W, θJCbottom = 9°C/W, θJCtop = 62°C/W, θJB
= 14°C/W
ΨJT = 1.25°C/W, θ VALUES DETERMINED PER JESD51-12
EXPOSED PAD (PIN 19) IS PGND, MUST BE SOLDERED TO PCB
18 17 16 15
6 7 8 9
1
2
3
4
5
14
13
12
11
10
ORDER INFORMATION
LEAD FREE FINISH AUTOMOTIVE PRODUCTS** PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3310S
LTC3310SEV#PBF LTC3310SEV#WPBF
LHCN 18-Lead (3mm × 3mm) LQFN (Laminate
Package with QFN Footprint) –40°C to 125°C
LTC3310SIV#PBF LTC3310SIV#WPBF
LTC3310SEV#TRPBF LTC3310SEV#WTRPBF
LTC3310SIV#TRPBF LTC3310SIV#WTRPBF
LTC3310SEV#TRMPBF LTC3310SEV#WTRMPBF
LTC3310SIV#TRMPBF LTC3310SIV#WTRMPBF
LTC3310S-1
LTC3310SEV-1#PBF Contact Marketing
LHKG 18-Lead (3mm × 3mm) LQFN (Laminate
Package with QFN Footprint) –40°C to 125°C
LTC3310SIV-1#PBF Contact Marketing
LTC3310SEV-1#TRPBF Contact Marketing
LTC3310SIV-1#TRPBF Contact Marketing
LTC3310SEV-1#TRMPBF Contact Marketing
LTC3310SIV-1#TRMPBF Contact Marketing
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
3
Rev. E
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified
operatingtemperature range, otherwise specifications are at TA = 25°C. (Notes 2, 3) VIN = 3.3V, VEN = VIN, MODE/SYNC = 0V,
unlessotherwisenoted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Supply
Operating Supply Voltage (VIN)l2.25 5.5 V
VIN Undervoltage Lockout
VIN Undervoltage Lockout Hysteresis
VIN Rising l2.0 2.1
150
2.2 V
mV
VIN Quiescent Current
VIN Quiescent Current in Shutdown
(Note 4)
VEN = 0.1V
1.3
1
2.0
2
mA
μA
EN Threshold
EN Hysteresis
VEN Rising l0.375 0.4
60
0.425 V
mV
EN Pin Leakage Current VEN = 0.4V ±20 nA
Voltage Regulation
Regulated Feedback Voltage (VFB)l495 500 505 mV
Regulated Output Voltage LTC3310S-1, LTC3310-1, IOUT = 4A l0.990 1.000 1.010 V
Output Line Regulation 2.5V ≤ VIN ≤ 5.0V 0.002 0.025 %/V
VOUT Active Voltage Positioning LTC3310S-1, LTC3310-1, l1.7 2.4 3.1 mV/A
Feedback Pin Input Current VFB = 0.5V ±20 nA
Error Amp Transconductance LTC3310S, LTC3310 400 µS
Error Amp Transconductance LTC3310S-1, LTC3310-1 800 µS
LEAD FREE FINISH AUTOMOTIVE PRODUCTS** PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3310
LTC3310JV#PBF LTC3310JV#WPBF
LHGW 18-Lead (3mm × 3mm) LQFN (Laminate
Package with QFN Footprint) –40°C to 150°C
LTC3310HV#PBF LTC3310HV#WPBF
LTC3310JV#TRPBF LTC3310JV#WTRPBF
LTC3310HV#TRPBF LTC3310HV#WTRPBF
LTC3310JV#TRMPBF LTC3310JV#WTRMPBF
LTC3310HV#TRMPBF LTC3310HV#WTRMPBF
LTC3310-1
LTC3310JV-1#PBF LTC3310JV-1#WPBF
LHMP 18-Lead (3mm × 3mm) LQFN (Laminate
Package with QFN Footprint) –40°C to 150°C
LTC3310HV-1#PBF LTC3310HV-1#WPBF
LTC3310JV-1#TRPBF LTC3310JV-1#WTRPBF
LTC3310HV-1#TRPBF LTC3310HV-1#WTRPBF
LTC3310JV-1#TRMPBF LTC3310JV-1#WTRMPBF
LTC3310HV-1#TRMPBF LTC3310HV-1#WTRMPBF
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
thesemodels.
ORDER INFORMATION
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
4
Rev. E
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3310SE/LTC3310SE-1 is guaranteed to meet performance
specifications from 0°C to 125°C junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization, and correlation with statistical process controls.
The LTC3310SI/LTC3310SI-1 is guaranteed over the –40°C to 125°C
operating junction temperature range. The LTC3310J/LTC3310J-1 and
PARAMETER CONDITIONS MIN TYP MAX UNITS
Error Amp Sink/Source Current ±25 µA
Top Switch Current Limit VOUT/VIN ≤ 0.2, Current Out of SW l14.5 16 18.5 A
Bottom Switch Current Limit (IVALLEYMAX) Current Out of SW l10 12 14 A
Top Switch ON-Resistance 16 mΩ
Bottom Switch ON-Resistance 4.5 mΩ
SW Leakage Current VEN = 0.1V ±100 nA
VITH to IPeak Current Gain 18 A/V
Minimum On-Time l35 60 ns
Maximum Duty cycle l100 %
Power Good/Soft-Start/Temp Monitor
PGOOD Rising Threshold
PGOOD Hysteresis
As a Percentage of the Regulated VOUT l
l
97
0.5
98
1
99
1.5
%
%
Overvoltage Rising Threshold
Overvoltage Hysteresis
As a Percentage of the Regulated VOUT l
l
106
1
110
2.5
112.5
3.5
%
%
PGOOD Leakage Current VPGOOD = 5.5V 20 nA
PGOOD Pull-Down Resistance VPGOOD = 0.1V 12 20 Ω
PGOOD Delay 100 µs
Soft-Start Charge Current VSSTT = 0.5V l7 10 13 µA
Temp Monitor Slope 4 mV/°C
Oscillator
Switching Frequency Range RT Programmable l0.5 5 MHz
Switching Frequency RT = 274k l1.8 2 2.2 MHz
Synchronization Frequency Range RT = VIN l0.5 2.25 MHz
Default Frequency RT = VIN l1.8 2 2.2 MHz
SYNC Level High on MODE/SYNC
SYNC Level Low on MODE/SYNC
l
l
1.2
0.4
V
V
Minimum MODE/SYNC Pulse Width 40 ns
MODE/SYNC Input Resistance 200 kΩ
MODE/SYNC No Clock Detect Time 20 µs
MODE/SYNC Clock Out Rise/Fall Time CMODE/SYNC = 50pF 10 ns
MODE/SYNC Clock Low Output Voltage IMODE/SYNC = 100µA 0.2 V
MODE/SYNC Clock High Output Voltage IMODE/SYNC = 100µA VIN – 0.2 V
MODE/SYNC Clock Out Duty Cycle 50 %
The l denotes the specifications which apply over the specified
operatingtemperature range, otherwise specifications are at TA = 25°C. (Notes 2, 3) VIN = 3.3V, VEN = VIN, MODE/SYNC = 0V,
unlessotherwisenoted.
LTC3310H/LTC310H-1 are guaranteed over the -40°C to 150°C operating
junction temperature range.
Note 3: The LTC3310S includes overtemperature protection which
protects the device during momentary overload conditions. Junction
temperatures will exceed 150°C when overtemperature protection is
active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 4: Supply current specification does not include switching currents.
Actual supply currents will be higher.
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
5
Rev. E
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.3V, unless otherwise noted.
VOUT Load Regulation,
VOUT=1.2V
VOUT Line Regulation,
VOUT=1.2V
PMOS Current Limit
Efficiency, Forced Continuous
Mode, VIN = 3.3V
Efficiency, Pulse-Skipping Mode,
VIN = 3.3V
Efficiency, Pulse-Skipping Mode
VIN = 3.3V, VOUT = 1.2V Efficiency, Pulse-Skipping Mode,
VIN = 1.2V
VIN = 2.25V
VIN = 3.3V
VIN = 5V
I
LOAD
0
2
4
6
8
10
1.188
1.190
1.192
1.194
1.196
1.198
1.200
1.202
1.204
1.206
1.208
1.210
1.212
V
OUT
(V)
OUT
3310S1 G01
LOAD = 1A
LOAD = 3A
LOAD = 6A
LOAD = 9A
INPUT VOLTAGE (V)
2
2.5
3
3.5
4
4.5
5
5.5
1.188
1.190
1.192
1.194
1.196
1.198
1.200
1.202
1.204
1.206
1.208
1.210
1.212
V
OUT
(V)
OUT
3310S1 G02
VIN = 2.5V
VIN = 3.3V
VIN = 5V
DUTY CYCLE (%)
0
10
20
30
40
50
60
70
80
90
100
10.0
12.0
14.0
16.0
18.0
20.0
PMOS CURRENT (A)
3310S1 G05
fSW = 2MHz
COILCRAFT XEL4030-101MEC
VOUT = 0.5V
VOUT = 1.2V
VOUT = 1.8V
I
LOAD
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
Forced Continuous Mode Operation
3310S1 G06
I
LOAD
0.01
0.1
1
10
50
60
70
80
90
100
EFFICIENCY (%)
3310S1 G07
fSW = 2MHz
COILCRAFT XEL4030-101MEC
VOUT = 0.5V
VOUT = 1.2V
VOUT = 1.8V
2MHz COILCRAFT XEL4030-101MEC
4MHz XFMRS XF303020-50NM
FSW = 2MHz
FSW = 4MHz
I
LOAD
(A)
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
Pulse Skip Mode
3310S1 G08
I
LOAD
0.01
0.1
1
10
50
55
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
Pulse Skip Mode Operation
3310S1 G09
fSW = 2MHz COILCRAFT
XEL4030-101MEC
VIN = 2.5V
VIN = 3.3V
VIN = 5.0V
VOUT Load Regulation
(LTC3310S-1, LTC3310-1)
VOUT Line Regulation
(LTC3310S-1, LTC3310-1)
25°C
–45°C
125°C
ILOAD (A)
0
1
2
3
4
5
6
7
8
9
10
0.90
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
VOUT (V)
Vout Load Regulation
3310S1 G03
1A
5A
9A
INPUT VOLTAGE (V)
2
2.5
3
3.5
4
4.5
5
5.5
0.90
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
VOUT (V)
Vout Line Regulation
3310S4 G04
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
6
Rev. E
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.3V, unless otherwise noted.
Feedback Reference Voltage Switch On-Resistance
Switch On-Resistance Switch Leakage Default Switching Frequency
VIN UVLO Switching Frequency EN Pin Thresholds
TEMPERATURE (°C)
–50
REFERENCE VOLTAGE (mV)
505
496
504
502
500
498
503
501
499
497
495 7525
3310S1 G10
125500 100–25
INPUT VOLTAGE (V)
2.0
RDS(ON) (mΩ)
24
22
18
14
20
16
8
4
10
6
12
24.53.5
3310S1 G12
5.54.03.0 502.5
PMOS
NMOS
TEMPERATURE (°C)
RDS(ON) (mΩ)
25
10
20
15
5
0
3310S1 G13
–50 7525 125500 100–25
VIN = 3.3V
PMOS
NMOS
TEMPERATURE (°C)
SWITCH LEAKAGE CURRENT (µA)
6
3
5
4
2
1
–1
0
3310S1 G14
25 75 12550 100
PMOS
NMOS
TEMPERATURE (°C)
DEFAULT FREQUENCY (MHz)
2.4
2.0
2.3
2.2
1.8
1.9
2.1
1.7
1.6
3310S1 G15
–50 7525 125500 100–25
TEMPERATURE (°C)
VIN UVLO (V)
2.5
1.9
2.3
2.1
1.7
1.5
3310S1 G16
–50 7525 125500 100–25
RISING
FALLING
TEMPERATURE (°C)
FREQUENCY (MHz)
2.20
1.95
2.15
2.05
1.90
2.10
2.00
1.85
1.80
3310S1 G17
–50 7525 125500 100–25
RT = 274kΩ
TEMPERATURE (°C)
EN THRESHOLD (mV)
410
370
400
390
360
380
350
340
3310S1 G18
–50 7525 125500 100–25
EN RISING
EN FALLING
VOUT Voltage vs Temperature
0A
5A
10A
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
VOUT (V)
3310S1 G11
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
7
Rev. E
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.3V, unless otherwise noted.
Soft-Start Current Soft-Start Tracking VIN Quiescent Current
VIN Shutdown Current Switch Current Limit UV PGOOD Threshold
TEMPERATURE (°C)
SOFT-START CURRENT (µA)
10.8
10.4
10.7
10.6
10.3
10.5
10.2
10.0
10.1
3310S1 G19
–50 7525 125500 100–25
SSTT VOLTAGE (mV)
FB VOLTAGE (mV)
600
200
500
400
100
300
0
3310S1 G20
0 500300 600400200100
TEMPERATURE (°C)
VIN CURRENT (mA)
2.5
1.0
2.0
1.5
0.5
0
3310S1 G21
–50 7525 125500 100–25
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
TEMPERATURE (°C)
VIN CURRENT (µA)
2.5
1.0
2.0
1.5
0.5
0
3310S1 G22
–50 7525 125500 100–25
TEMPERATURE (°C)
CURRENT (A)
16
18
12
6
14
8
2
10
4
0
3310S1 G23
–50 7525 125500 100–25
NMOS I LIMIT
PMOS I LIMIT
TEMPERATURE (°C)
PGOOD THRESHOLD OFFSET FROM VREF (%)
–3.5
–3.0
–1.0
–2.5
–2.0
–1.5
–0.5
0
3310S1 G24
–50 7525 125500 100–25
FB RISING
FB FALLING
Minimum On-Time
OV PGOOD Threshold
TEMPERATURE (°C)
PGOOD THRESHOLD OFFSET FROM VREF (%)
10.0
9.0
6.5
8.5
9.5
8.0
6.0
7.0
7.5
5.5
5.0
3310S1 G25
–50 7525 125500 100–25
FB RISING
FB FALLING
TEMPERATURE (°C)
MINIMUM ON-TIME (ns)
80
60
10
50
70
40
20
30
0
3310S1 G26
–50 7525 125500 100–25
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
8
Rev. E
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.3V, unless otherwise noted.
Switching Waveforms,
Pulse-Skipping Mode
Switching Waveforms, Forced
Continuous Mode
Load Transient Response
Pulse-Skipping Mode
Load Transient Response Forced
Continuous Mode
200ns/DIV
3310S1 G29
VOUT
10mV/DIV
SW
2V/DIV
IL
500mA/DIV
200ns/DIV
3310S1 G30
VOUT
10mV/DIV
SW
2V/DIV
IL
1A/DIV
3.3V
IN
TO 1.2V
OUT
, 2MHz
C
OUT
= 110µF, L = 100nH
LOAD STEP: 0.1A TO 9A
1A/μs SLEW RATE
40µs/DIV
3310S1 G31
VOUT
20mV/DIV
ILOAD
5A/DIV
IL
5A/DIV
3.3V
IN
TO 1.2V
OUT
, 2MHz
C
OUT
= 110µF, L = 100nH
LOAD STEP: 1A TO 9A
1A/µs SLEW RATE
40µs/DIV
VOUT
20mV/DIV
ILOAD
5A/DIV
IL
5A/DIV
3310S1 G32
Start-Up Waveforms
Pulse-Skipping Mode
Start-Up Waveforms Forced
Continuous Mode
400µs/DIV
3310S1 G27
VOUT
1V/DIV
EN
2V/DIV
IL
1A/DIV
PGOOD
5V/DIV
400µs/DIV
3310S1 G28
VOUT
1V/DIV
EN
2V/DIV
IL
1A/DIV
PGOOD
5V/DIV
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
9
Rev. E
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.3V, unless otherwise noted.
Radiated EMI Performance (CISPR25 Radiated Emissions
Test with Class 5 Peak Limits)
Radiated EMI Performance (CISPR25 Radiated Emissions
Test with Class 5 Peak Limits)
CISPR25 Conducted EMI Emissions with Class 5 Peak
Limits (Voltage Method)
FREQUENCY (MHz)
AMPLITUDE (dBµV/m)
60
50
30
10
40
20
0
–10
–20
3310S1 G33
0 50 9030 70 11010040 8020 6010
PEAK LIMIT
PEAK
LTC3310S
DC2629A DEMO BOARD
(WITH EMI FILTER INSTALLED)
3.3V INPUT TO 1.2V OUTPUT AT 7.5A, fSW = 2MHz
FREQUENCY (MHz)
AMPLITUDE (dBµV/m)
50
5
45
35
25
15
40
30
20
10
0
3310S1 G34
0 500 900300 700 1000400 800200 600100
HORIZONTAL POLARIZATION
PEAK DETECTOR
PEAK LIMIT
PEAK
LTC3310S
DC2629A DEMO BOARD
(WITH EMI FILTER INSTALLED)
3.3V INPUT TO 1.2V OUTPUT AT 7.5A, fSW = 2MHz
FREQUENCY (MHz)
AMPLITUDE (dBµV/m)
50
5
45
35
25
15
40
30
20
10
0
3310S1 G35
0 500 900300 700 1000400 800200 600100
VERTICAL POLARIZATION
PEAK DETECTOR
PEAK LIMIT
PEAK
LTC3310S
DC2629A DEMO BOARD
(WITH EMI FILTER INSTALLED)
3.3V INPUT TO 1.2V OUTPUT AT 7.5A, fSW = 2MHz
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
10
Rev. E
For more information www.analog.com
PIN FUNCTIONS
EN (Pin 1): The EN pin has a precision enable threshold
with hysteresis. An external resistor divider, from VIN or
from another supply, programs the threshold below which
the LTC3310S will shut down. If the precision threshold
is not used, directly connect the pin to VIN. When the EN
pin is low, the LTC3310S enters a low current shutdown
mode where all internal circuitry is disabled.
AGND (Pin 2): The AGND pin is the output voltage remote
ground sense. Connect the AGND pin directly to the neg-
ative terminal of the output capacitor at the load and to
the feedback divider resistor.
VIN (Pins 3, 4, 11, 12): The VIN pins supply current to the
internal circuitry and topside power switch. All of the VIN
pins must be connected together with short, wide traces
and bypassed to PGND with low ESR capacitors located
as close as possible to the pins.
The Silent Switcher 2 LTC3310S/LTC3310S-1 include
internal bypass capacitors between V
IN
and PGND and
V
IN
and AGND. The Silent Switcher 1 LTC3310/LTC3310-1
do not include these capacitors. It is recommended to
include them externally. See the Applications Information
section for more details.
PGND (Pins 5, 10, 19): The PGND pins are the return
path of the internal bottom side power switch. Connect
the PGND pins together and to the exposed pad. Connect
the negative terminal of the input capacitors as close to
the PGND pins as possible. The PGND node is the main
thermal highway and should be connected to a large PCB
ground plane with many large vias.
SW (Pins 6–9): The SW pins are the switching outputs of
the internal power switches. Connect these pins together
to the inductor with short, wide traces.
MODE/SYNC (Pin 13): The MODE/SYNC pin facilitates
multiphase operation and synchronization to an external
clock. Depending on the mode of operation, the MODE/
SYNC pin either accepts an input clock pulse or outputs
a clock pulse at its operating frequency. (see Multiphase
Operation in Applications Information). The MODE/SYNC
pin also programs the mode of operation: pulse skip or
forced continuous.
PGOOD (Pin 14): The PGOOD pin is a power good pin and
is the open drain output of an internal comparator. The
PGOOD output is pulled low when VIN is above 2.25V and
the part is in shutdown.
RT (Pin 15): The RT pin sets the oscillator frequency
with an external resistor to AGND or sets the phasing
for multiphase operation. (see Multiphase Operation in
Applications Information).
SSTT (Pin 16): Soft-Start, Track, Temperature Monitor.
An internal 10µA current into an external capacitor on
the soft-start pin programs the output voltage ramp rate
during start-up. During the soft-start cycle, the FB pin
voltage will track the SSTT pin voltage. When the soft-start
cycle is complete, the tracking function is disabled, the
internal reference resumes control of the error amplifier
and the SSTT pin servos to a voltage representative of
junction temperature. For a clean recovery from an output
short circuit condition, the SSTT pin is pulled down to
approximately 140mV above the VFB voltage and a new
soft-start cycle is initiated. During shutdown and fault
conditions, the SSTT pin is pulled to ground.
ITH (Pin 17): The ITH pin is the compensation node for
the output voltage regulation control loop. Compensation
components connected to this pin are referenced to AGND.
FB (Pin 18): The LTC3310S output voltage feedback pin is
externally connected to the output voltage via a resistive
divider and is internally connected to the inverting input
of the error amplifier. The LTC3310S regulates the FB pin
to 500mV. A phase lead capacitor connected between VFB
and VOUT is used to optimize the transient response.
VOUT (Pin 18): The output voltage pin is externally con-
nected to the output voltage and is internally connected
to a resistive divider. The LTC3310S-1 regulates the VOUT
pin to 1.0V.
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
11
Rev. E
For more information www.analog.com
BLOCK DIAGRAM
0.55V
0.49V
3310S1 BD
+
–
+
–
+
–
SENSE+
SENSE–
+
–
+
–
+
–
FAULT
FAULT
10µA
RA
RB
R1
R2
CFF
COUT
V
OUT
VIN
CIN
0.1µF
×2
RT
RC
CC
CSS
SW
PGND
FB
AGND
PGOOD
VIN
+
V
IN
ERROR
AMP
0.5V
0.5V
0.55V
0.49V
0.4V
VTEMP
OSCILLATOR
S Q
R
SWITCH LOGIC
AND
ANTI-SHOOT THROUGH
VIN
SLOPE COMP
INTERNAL
REFERENCE
MODE/SYNC
RT
EN
ITH
SSTT
L
Note 1: On the LTC3310S-1 the RA and RB resistors are internal.
Note 2: The LTC3310/LTC3310-1 do not include internal bypass capacitors.
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
12
Rev. E
For more information www.analog.com
OPERATION
Voltage Regulation
The LTC3310S is a monolithic, constant frequency, cur-
rent mode step-down DC/DC converter. An oscillator turns
on the internal top power switch at the beginning of each
clock cycle. Current in the inductor increases until the
top switch current comparator trips and turns off the top
power switch. The peak inductor current at which the top
switch turns off is controlled by the voltage on the ITH
node. The error amplifier servos the ITH node by com-
paring the voltage on the FB pin with an internal 500mV
reference. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference
leading the error amplifier to raise the ITH voltage until the
average inductor current matches the new load current.
When the top power switch turns off, the synchronous
power switch turns on until the next clock cycle begins
or, in pulse-skipping mode, inductor current falls to zero.
If overload conditions result in excessive current flowing
through the bottom switch, the next clock cycle will be
delayed until switch current returns to a safe level.
The output voltage is resistively divided externally to cre-
ate a feedback voltage for the regulator. In high current
operation, a ground offset may be present between the
LTC3310S local ground and ground at the load. To over-
come this offset, AGND should have a Kelvin connection
to the load ground, and the lowest potential node of the
resistor divider should be connected to AGND. The inter-
nal error amplifier senses the difference between this
feedback voltage and a 0.5V AGND referenced voltage.
This scheme overcomes any ground offsets between
local ground and remote output ground, resulting in a
more accurate output voltage. The LTC3310S allows for
remote output ground deviations as much as ±100mV
with respect to local ground.
If the EN pin is low, the LTC3310S is shut down and in a
low quiescent current state. When the EN pin is above its
threshold, the switching regulator will be enabled.
Silent Switcher
The “S” in LTC3310S/LTC3310S-1 refers to the second
generation Silent Switcher 2 technology, allowing fast
switching edges for high efficiency at high switching
frequencies, while simultaneously achieving good EMI
performance. Ceramic capacitors on VIN keep all the fast
AC current loops small, improving EMI performance.
The LTC3310S/LTC3310S-1 also include an internal
bypass capacitor connected between VIN and AGND. The
Silent Switcher 1 LTC3310/LTC3310-1 do not include any
ceramiccapacitors.
Synchronizing the Oscillator to an External Clock
The LTC3310S’s internal oscillator is synchronized
through an internal PLL circuit to an external frequency
by applying a square wave clock signal to the MODE/
SYNC pin.
During synchronization, the top power switch turn-on is
locked to the rising edge of the external frequency source.
While synchronizing, the switcher operates in pulse skip
mode. The slope compensation is automatically adapted
to the external clock frequency.
After detecting an external clock on the first rising edge
of the MODE/SYNC pin, the internal PLL gradually adjusts
its operating frequency to match the frequency and phase
of the signal on the MODE/SYNC pin. When the exter-
nal clock is removed, the LTC3310S detects the absence
of the external clock within approximately 20µs. During
this time, the PLL will continue to provide clock cycles.
Oncethe external clock removal has been detected, the
oscillator gradually adjusts its operating frequency back
to the default frequency.
Mode Selection
The MODE/SYNC pin either synchronizes the switching
frequency to an external clock, is a clock output, or sets
the PWM mode. The PWM modes of operation are either
pulse skip or forced continuous. See Table6 or Table7 in
the Applications Information section. In pulse skip mode,
switching cycles are skipped at light loads to regulate the
output voltage. During forced continuous mode, the top
switch turns on every cycle and light load regulation is
achieved by allowing negative inductor current.
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
13
Rev. E
For more information www.analog.com
OPERATION
Output Power Good
Comparators monitoring the FB pin voltage pull the
PGOOD pin low if the output voltage varies from the
nominal set point or if a fault condition is present. The
comparator includes voltage hysteresis. A time delay
to report PGOOD is used to filter short duration output
voltage transients.
Soft-Start/Tracking/Temperature Monitor
The soft-start tracking function facilitates supply sequenc-
ing, limits VIN inrush current and reduces start-up output
overshoot. When soft-starting is completed, the SSTT pin
parks itself at a voltage representative of the LTC3310S
die junction temperature. The SSTT capacitor is reset
during shutdown, VIN UVLO and thermal shutdown. See
Application section.
Dropout Operation
As the input supply voltage approaches the output voltage,
the duty cycle increases. Further reduction of the supply
voltage forces the main switch to remain on for more
than one cycle, eventually reaching 100% duty cycle.
The output voltage will then be determined by the input
voltage minus the DC voltage drop across the internal
main P-channel MOSFET and the inductor.
In many designs when the input voltage approaches the
output voltage, the amplitude of the output ripple voltage
increases from its normally low value. To avoid any
increase in output ripple voltage under these conditions,
it is recommended to utilize a resistor divider on the EN
input and limit the VIN turn-on and turn-off thresholds to
where the output ripple voltage is acceptable for the given
application (typically 500mV above VOUT).
Low Supply Operation
The LTC3310S is designed to operate down to an input
supply voltage of 2.25V. An important thermal design
consideration is that the RDS(ON) of the power switches
increase at low VIN. Calculate the worst case LTC3310S
power dissipation and die junction temperature at the
lowest input voltages.
Output Short-Circuit Protection and Recovery
The peak inductor current level, at which the current com-
parator shuts off the top power switch, is controlled by the
voltage on the ITH pin. If the output current increases, the
error amplifier raises the ITH pin voltage until the average
inductor current matches the load current. The LTC3310S
clamps the maximum ITH pin voltage, thereby limiting the
peak inductor current.
When the output is shorted to ground, the inductor cur-
rent decays very slowly during a single switching cycle
because the voltage across the inductor is low. To keep
the inductor current in control, a secondary limit is
imposed on the valley of the inductor current. If the induc-
tor current measured through the bottom power switch
is greater than the IVALLEY(MAX) the top power switch will
be held off. Subsequent switching cycles will be skipped
until the inductor current is reduced below IVALLEY(MAX).
Recovery from an output short circuit goes through a
soft-start cycle. When V
OUT
goes below regulation, as
defined by the PGOOD threshold, the SSTT voltage is
pulled to a voltage just above the FB voltage. Because
the SSTT pin is pulled low, a soft-start cycle is initiated
once the output short is removed.
Active Voltage Positioning
The LTC3310S-1/LTC3310-1 includes Active Voltage
Positioning (AVP) where the output voltage is dependent
on load current. At light loads the output voltage is reg-
ulated above the nominal value. At full load the output
voltage is regulated below the nominal value. The DC load
regulation is adjusted to improve transient performance
and reduce output capacitor requirements.
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
14
Rev. E
For more information www.analog.com
Refer to the Block Diagram for reference.
FB Resistor Network
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the resistor
values according to:
RA=RB
VOUT
500mV – 1
⎛
⎝
⎜⎞
⎠
⎟
(1)
as shown in Figure1:
Figure1.
C
OUT
CFF
RA
VOUT
FB
3310S1 F01
BUCK
SWITCHING
REGULATOR (OPTIONAL)
+
RB
Feedback Resistor Network
Reference designators refer to the Block Diagram. 1%
resistors are recommended to maintain output voltage
accuracy. When optimizing the control loop for high band-
width and optimal transient response add a phase-lead
capacitor connected from VOUT to FB.
Operating Frequency Selection and Trade-Offs
Selection of the operating frequency is a trade-off between
efficiency, component size, transient response and input
voltage range.
The advantage of high frequency operation is that smaller
inductor and capacitor values may be used. Higher
switching frequencies allow for higher control loop
bandwidth and, therefore, faster transient response. The
disadvantages of higher switching frequencies are lower
efficiency, because of increased switching losses, and a
smaller input voltage range, because of minimum switch
on-time limitations.
Although the maximum programmable switching fre-
quency is 5MHz, the minimum on-time of the LTC3310S
imposes a minimum operating duty cycle. The highest
APPLICATIONS INFORMATION
switching frequency (fSW(MAX)) for a given application
can be calculated as follows:
fSW MAX
( )
=
VOUT +VSW BOT
()
tON MIN
( )
VIN MAX
( )
– VSW TOP
()
+VSW BOT
()
( )
(3)
where VIN(MAX) is the maximum input voltage, VOUT is
the output voltage, VSW(TOP) and VSW(BOT) are the inter-
nal switch drops and tON(MIN) is the minimum top switch
on-time. This equation shows that a slower switching
frequency is necessary to accommodate a high VIN/VOUT
ratio.
The LTC3310S is capable of a maximum duty cycle of
100%, therefore, the VIN-to-VOUT dropout is limited by
the RDS(ON) of the top switch, the inductor DCR and the
load current.
Setting the Switching Frequency
The LTC3310S uses a constant frequency PWM archi-
tecture. There are three methods to set the switching fre-
quency. The first method is with a resistor (RT) tied from
the RT pin to ground. The frequency can be programmed
to switch from 500kHz to 5MHz. Table1 shows the nec-
essary RT value for a desired switching frequency.
The R
T
resistor required for a desired switching frequency
is calculated using the following formula:
RT = 568 • fSW(–1.08) (2)
where RT is in kΩ and fSW is the desired switching fre-
quency in MHz.
Table1. SW Frequency vs RT Value
fSW (MHz) RT (kΩ)
0.5 1210
1 549
2 274
2.2 243
3 178
4 130
5 100
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
15
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
The second method to set the LTC3310S switching fre-
quency is by synchronizing the internal PLL circuit to an
external frequency applied to the MODE/SYNC pin. The
synchronization frequency range is 0.5MHz to 2.25MHz.
The internal PLL starts up at the 2MHz default frequency.
After detecting an external clock on the first rising edge
of the MODE/SYNC pin, the internal PLL gradually adjusts
its operating frequency to match the frequency and phase
of the MODE/SYNC signal.
The LTC3310S detects when the external clock is removed
and will gradually adjust its operating frequency to the
2MHz default frequency.
The third method of setting the LTC3310S switching fre-
quency is to use the internal nominal 2MHz default clock.
See Table4 for pin configuration.
Inductor Selection and Maximum Output Current
Considerations in choosing an inductor are inductance,
RMS current rating, saturation current rating, DCR and
core loss.
A good first choice for the inductor value is:
L
VOUT
3A • f
SW
• 1 VOUT
V
IN MAX
( )
for VOUT
V
IN MAX
( )
0.
5
(4)
L0.25 • V
IN MAX
( )
3A • fSW
for
V
OUT
V
IN MAX
( )
>0.
5
(5)
where fSW is the switching frequency in MHz, VIN is the
input voltage and L is the inductor value in μH.
To avoid overheating of the inductor, choose an inductor
with an RMS current rating that is greater than the max-
imum expected output load of the application. Overload
and short circuit conditions may need to be taken into
consideration.
In addition, the saturation current (ISAT) rating of the
inductor must be higher than the load current plus 1/2 of
the inductor ripple current:
ISAT ≥ILOAD MAX
( )
+
1
2
∆IL
(6)
where I
LOAD(MAX)
is the maximum output load current for
a given application and ΔIL is the inductor ripple current
calculated as:
∆IL=VOUT
L•fSW
• 1– VOUT
VIN(MAX)
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
(7)
where VIN(MAX) is the maximum application input voltage.
To keep the efficiency high, choose an inductor with the
lowest series resistance (DCR). The core material should
be intended for high frequency applications.
The LTC3310S limits the peak switch current in order
to protect the switches and the system from overload
faults. The inductor value must then be sufficiently large
to supply the desired maximum output current, IOUT(MAX),
which is a function of the switch current limit, ILIM, and
the ripple current.
I
OUT MAX
( )
=I
LIM
– ΔI
L
(8)
Therefore, the maximum output current that the LTC3310S
will deliver depends on the switch current limit, the induc-
tor value, and the input and output voltages. The inductor
value may have to be increased if the inductor ripple cur-
rent does not allow sufficient maximum output current
(IOUT(MAX)) given the switching frequency, and maximum
input voltage used in the desired application.
Table2. Inductor Manufacturers
VENDOR URL
Coilcraft www.coilcraft.com
Sumida www.sumida.com
Toko www.toko.com
Wurth Elektronik www.we-online.com
Vishay www.vishay.com
XFMRS www.xfmrs.com
Input Capacitors
Bypass the input of the LTC3310S with at least two
ceramic capacitors close to the part, one on each side
from VIN to PGND. These capacitors should be 0603 or
0805 in size. See layout section for more detail. X7R or
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
16
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
X5R capacitors are recommended for best performance
across temperature and input voltage variations. Note
that larger input capacitance is required when a lower
switching frequency is used. If the input power source has
high impedance, or there is significant inductance due to
long wires or cables, additional bulk capacitance may be
necessary. This can be provided with a low performance
electrolytic capacitor.
A ceramic input capacitor combined with trace or cable
inductance forms a high quality (under damped) tank
circuit. If the LTC3310S circuit is plugged into a live sup-
ply, the input voltage can ring to twice its nominal value,
possibly exceeding the LTC3310S’s voltage rating. This
situation is easily avoided (see Analog Devices Application
Note 88).
Table3. Ceramic Capacitor Manufacturers
VENDOR URL
AVX www.avxcorp.com
Murata www.murata.com
TDK www.tdk.com
Taiyo Yuden www.t-yuden.com
Samsung www.samsungsem.com
Output Capacitor and Output Ripple
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave, generated by
the LTC3310S, to produce the DC output. In this role it
determines the output ripple, thus, low impedance at the
switching frequency is important. The second function
is to store energy in order to satisfy transient loads and
stabilize the LTC3310S’s control loop. Ceramic capacitors
have very low equivalent series resistance (ESR) and pro-
vide the best ripple performance. For good starting val-
ues, see the Typical Application section.
X5R or X7R type capacitors will provide low output rip-
ple and good transient response. Transient performance
is improved with a higher value output capacitor and
the addition of a feedforward capacitor placed between
VOUT and FB. Increasing the output capacitance will also
decrease the output voltage ripple. A lower value of output
capacitor saves space and cost but transient performance
will suffer and may cause loop instability. See the Typical
Application in this data sheet for suggested capacitor
values.
Multiphase Operation
The LTC3310S is easily configurable for multiphase oper-
ation. See Table4.
Connecting the RT pin, of the master phase, to a resis-
tor to AGND programs the frequency and configures the
MODE/SYNC pin to become clock output used to drive
the MODE/SYNC pin of the slave phase(s).
Connecting the RT pin of the master phase to VIN con-
figures the MODE/SYNC pin to become an input capable
of accepting an external clock. The switching frequency
defaults to the nominal 2MHz internal frequency when
the external clock is unavailable, such as during start-up.
Connecting the FB pin to VIN configures a phase as a
slave. The MODE/SYNC becomes an input and the voltage
control loop is disabled. The slave phase current control
loop is still active and the peak current is controlled via
the shared ITH node.
Table4. LTC3310S Multiphase Configuration
Master/Slave RT Pin FB Pin MODE/SYNC Pin Switching Frequency (fSW)
Master VIN VOUT Divider Clock Input External Clock/2MHz Default
Master Resistor to AGND VOUT Divider Clock Output RT programmed
Slave VIN Divider VIN Clock Input External Clock
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
17
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
The phasing of a slave phase relative to the master phase
is programmed with a resistor divider on the RT pin. Use
of 1% resistors is recommended. See Table5 for more
information.
Table5. LTC3310S Programming Slave Phase Angle
SYNC
Phase
Angle
R3
Ratio
R4
Ratio
R3
Example
R4
Example
0° 0Ω NA 0Ω NA
90° 3 • R R 301k 100k
120° 7 • R 5 • R 243k 174k
180° NA 0Ω NA 0Ω
240° 5 • R 7 • R 174k 243k
270° R 3 • R 100k 300k
When configured for master/slave operation, the slave
regulator(s) operates in pulse skip mode where negative
inductor currents are disallowed and regulation at low
currents is achieved by skipping switching cycles.
Figure2.
LTC3310S
VIN
RT
FB
3310S1 F02
R4
R3
AGND
Phase Programming
LTC3310S Mode of Operation
For most configurations, the LTC3310S operates in pulse
skip mode where negative inductor current is disallowed
and regulation at low currents is achieved by skipping
switching cycles.
The LTC3310S operates in forced continuous mode when
both the RT and MODE/SYNC pins are connected to V
IN
. In
this mode, the switching frequency is set with the nominal
2MHz internal clock. While in forced continuous mode,
regulation at low currents is achieved by allowing negative
inductor current. Switching cycles are not skipped.
Table6. LTC3310S Single Phase Configuration
RT Pin
Connection
MODE/SYNC
Pin Connection
MODE of
Operation
Switching
Frequency
VIN Clock Input Pulse Skip External Clock
VIN AGND Pulse Skip 2MHz Default
VIN VIN Forced
Continuous
2MHz Default
Resistor to AGND Clock Output Pulse Skip RT Programmed
LTC3310S-1 Mode of Operation
For most configurations, the LTC3310S-1 operates in
forced continuous mode. While in forced continuous mode,
regulation at low currents is achieved by allowing negative
inductor current. Switching cycles are not skipped.
The LTC3310S-1 operates in pulse skip mode when both
RT and MODE/SYNC pins are connected to VIN. In this
mode, the switching frequency is set with the nominal
2MHz internal clock. While in pulse skip mode negative
current is disallowed and regulation at low currents is
achieved by skipping switching cycles.
Table7. LTC3310S-1 Single Phase Configuration
RT Pin
Connection
MODE/SYNC
Pin Connection
MODE of
Operation
Switching
Frequency
VIN Clock Input Forced
Continuous
External Clock
VIN AGND Forced
Continuous
2MHz Default
VIN VIN Pulse Skip 2MHz Default
Resistor to AGND Clock Output Forced
Continuous
RT Programmed
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
18
Rev. E
For more information www.analog.com
Synchronization
To synchronize the LTC3310S oscillator to an external
frequency, configure the MODE/SYNC pin as an input by
connecting the RT pin to VIN. Drive the MODE/SYNC pin
with a square wave in the frequency range of 500 kHz to
2.25MHz range, an amplitude greater than 1.2V and less
than 0.4V with a pulse width greater than 40ns.
The LTC3310S phase locked loop (PLL) will synchronize
the internal oscillator to the clock applied to the MODE/
SYNC pin. At start up, before the LTC3310S recognizes
the external clock applied to MODE/SYNC, the LTC3310S
will switch at its default frequency of 2MHz. Once the
externally applied clock is recognized, the switching fre-
quency will gradually transition from the default frequency
to the applied frequency. If the external clock is removed,
the LTC3310S will slowly transition back to the default
frequency.
The LTC3310S operates in pulse skip mode during syn-
chronization. An internal 200kΩ resistor on MODE/SYNC
pin to AGND allows the MODE/SYNC pin to be left floating.
Transient Response and Loop Compensation
When determining the compensation components, CFF,
RC, and CC, control loop stability and transient response
are the two main considerations.
The LTC3310S has been designed to operate at a high
bandwidth for fast transient response capability. Operating
at a high loop bandwidth reduces the output capacitance
required to meet transient response requirements.
Applying a load transient and monitoring the response of
the system or using a network analyzer to measure the
actual loop response are two ways to verify and optimize
the control loop stability. LTpowerCAD
®
is a useful tool to
help optimize the compensation components.
When using the load transient response method to sta-
bilize the control loop, apply an output current pulse of
20% to 100% of full load current having a rise time of
1µs. This will produce a transient on the output voltage
and ITH pin waveforms.
APPLICATIONS INFORMATION
Switching regulators take multiple cycles to respond
to a step in load current. When a load step occurs,
VOUT is immediately perturbed, generating a feedback
error signal used by the regulator to return VOUT to its
steady-statevalue.
During this recovery time, monitor VOUT for overshoot
or ringing that would indicate a stability problem. The
initial output voltage step may not be within the band-
width of the feedback loop, so the standard second order
overshoot/DC ratio cannot be used to determine phase
margin. The gain of the loop increases with the RC and the
bandwidth of the loop increases with decreasing CC. If RC
is increased by the same factor that CC is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, adding a feed forward capaci-
tor, CFF, improves the high frequency response. Capacitor
CFF provides phase lead by creating a high frequency zero
with RA to improve the phase margin. The compensation
components of the typical application circuits are a good
starting point for component values.
On the LTC3310S-1 an internal voltage regulation adjust-
ment circuit modifies the regulated output voltage based
on load current. This circuit effectively increases the out-
put impedance of the supply, reducing the output voltage
during a heavy load, and raising the voltage during light
loads. The output is centered at 1V at an average load cur-
rent of 4.5A; the regulated output voltage varies typically,
2.4mV per Amp of average load current. This variation in
output voltage helps compensate for the short-duration
voltage spikes created during a fast load step, reducing
the overall voltage perturbation in response to these
loadsteps.
The output voltage settling behavior is related to the sta-
bility of the closed-loop system. For a detailed explanation
of optimizing the compensation components, including
a review of control loop theory, refer to Analog Devices
Application Note 76.
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
19
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
Output Overvoltage Protection
During an output overvoltage event, when the FB pin
voltage is greater than 110% of nominal, the LTC3310S
top power switch will be turned off. If the output remains
out of regulation for more than 100µs, the PGOOD pin
will be pulled low.
An output overvoltage event should not happen under
normal operating conditions.
Output Voltage Sensing
The LTC3310S AGND pin is the ground reference for the
internal analog circuitry, including the bandgap voltage
reference. To achieve good load regulation, connect the
AGND pin to the negative terminal of the output capaci-
tor (COUT) at the load. A drop in the high current power
ground return path will be compensated. All of the signal
components, such as the FB resistor dividers and soft-
start capacitor, should be referenced to the AGND node.
The AGND node carries very little current and, therefore,
can be a minimal size trace. See the example PCB Layout
for more information.
Enable Threshold Programming
The LTC3310S has a precision threshold enable pin
to enable or disable switching. When forced low, the
LTC3310S enters a low current shutdown mode.
The rising threshold of the EN comparator is 400mV, with
60mV of hysteresis. Connect the EN pin to VIN if the shut-
down feature is not used. Adding a resistor divider from
VIN to EN programs the LTC3310S to regulate the output
only when VIN is above a desired voltage (see the Block
Diagram). Typically, this threshold, VIN(EN), is used in sit-
uations where the input supply is current limited or has
a relatively high source resistance. A switching regulator
draws constant power from the source, so source current
increases as source voltage drops. This looks like a nega-
tive resistance load to the source and can cause the source
to current limit or latch low under low source voltage con-
ditions. The VIN(EN) threshold prevents the regulator from
operating at source voltages where problems may occur.
This threshold can be adjusted by setting the values R1
and R2 such that they satisfy the followingequation:
VIN EN
( )
=R1
R2 +1
⎛
⎝
⎜⎞
⎠
⎟• 400mV
(9)
where the LTC3310S will remain off until VIN is above
V
IN(EN)
. Due to the comparator’s hysteresis, switching
will not stop until the input falls slightly below VIN(EN).
Alternatively, a resistor divider from an output of another
regulator to the enable pin of the LTC3310S pro-
vides event-based power-up sequencing, enabling the
LTC3310S when the output of the other regulator reaches
a predetermined level.
Output Voltage Tracking and Soft-Start
The LTC3310S allows the user to program its output
voltage ramp rate by means of the SSTT pin.
An internal 10μA pulls up the SSTT pin. Putting an exter-
nal capacitor on SSTT enables soft-starting the output
to prevent current surge on the input supply and output
voltage overshoot. During the soft-start ramp, the output
voltage will proportionally track the SSTT pin voltage.
When the soft-start is complete, the pin will servo to a
voltage proportional to the LTC3310S junction tempera-
ture. See Figure3 showing the SSTT pin operating range.
The soft-start time is calculated as follows:
tSS =CSS •500mV
10µA
(10)
For output tracking applications, SSTT can be externally
driven by another voltage source. From 0V to 0.5V, the
SSTT voltage will override the internal 0.5V reference
input to the error amplifier, thus regulating the FB pin
voltage to that of SSTT pin. When SSTT is above 0.5V,
tracking is disabled and the feedback voltage will regulate
to the internal reference voltage
An active pull-down circuit is connected to the SSTT pin
to discharge the external soft-start capacitor in the case
of fault conditions. The ramp will restart when the fault is
cleared. Fault conditions that clear the soft-start capacitor
are the EN/UV pin transitioning low, V
IN
voltage falling too
low or thermal shutdown.
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
20
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
Temperature Monitor
Once the soft-start cycle has completed and the output
power good flag thrown, the SSTT pin reports the die
junction temperature. The LTC3310S regulates the SSTT
pin to a voltage proportional to the junction temperature.
While reporting the temperature, the SSTT voltage is not
valid below 1V. The junction temperature is calculated
with the following formula:
TJ (°C)=
V
SSTT
4mV
– 273
The following procedure is used for a more accurate mea-
surement of the junction temperature:
1. Measure the ambient temperature TA.
2. Measure the SSTT voltage while in pulse skip mode
with the VOUT pulled up slightly higher than the
regulatedVOUT.
3. Calculate the slope of the temperature sensing circuit
as follows:
Slope (mV / °C)=
V
SSTT
T
A
+273
4. Calculate the junction temperature with the new cali-
brated slope.
When the output voltage goes out of regulation and the
power good pin is pulled low, the soft-start pin no longer
reports the temperature.
Figure3. Soft-Start and Temperature Monitor Operation
0
DIE TEMP
(°C)
FB
(V)
150
0.1
125
75
0.6
0.3
100
50
0.5
25
0.4
0.2
00.5 1.50.6 1.60.3 1.3
3310S1 F03
1.70.4 1.40.2 1.20.1
SSTT (V)
TEMP
MONITOR
~4mV/°C
SSTT PIN VOLTAGE
OPERATING RANGE
SOFT-START
AND TRACKING
Output Power Good
When the LTC3310S’s output voltage is within the
–2/+10% window of the nominal regulation voltage the
output is considered good and the open-drain PGOOD pin
goes high impedance and is typically pulled high with an
external resistor. Otherwise, the internal pull-down device
will pull the PGOOD pin low. To prevent glitching both the
upper and lower thresholds, include 1% of hysteresis as
well as a built in time delay, typically 100µs. The PGOOD
pin is also actively pulled low during fault conditions: EN
pin is low, VIN is too low or in thermal shutdown.
Output Short Circuit Protection and Recovery
The peak inductor current at which the current compar-
ator shuts off the top power switch is controlled by the
voltage on the ITH pin. If the output current increases,
the error amplifier raises the ITH pin voltage until the
average inductor current matches the new load current.
In normal operation, the LTC3310S clamps the maximum
ITH pin voltage.
When the output is shorted to ground, the inductor cur-
rent decays very slowly during the switch off time because
of the low voltage across the inductor. To keep the current
in control, a secondary limit is also imposed on the valley
inductor current. If the inductor current measured through
the bottom power switch increases beyond IVALLEY(MAX),
the top power switch will be held off and switching cycles
will be skipped until the inductor current is reduced.
Recovery from a short circuit can be abrupt and because
the output is shorted and below regulation the regulator
is requesting the maximum current to charge the output.
When the short circuit condition is removed, the inductor
current could cause an extreme voltage overshoot in the
output. The LTC3310S addresses this potential issue by
regulating the SSTT voltage just above the FB voltage any-
time the output is out of regulation. Therefore, a recovery
from an output short circuit goes through a soft-start
cycle. The output ramp is controlled and the overshoot
is minimized.
Figure4. Recommended PCB Layout for the LTC3310S
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
21
Rev. E
For more information www.analog.com
APPLICATIONS INFORMATION
Low EMI PCB Layout
The LTC3310S is specifically designed to minimize EMI/
EMC emissions and also to maximize efficiency when
switching at high frequencies. For optimal performance,
the LTC3310S/LTC3310 requires the use of multiple VIN
bypass capacitors.
Many designs will benefit from additional 0402 ceramic
capacitors (CIN3 and CIN4) placed between the larger bulk
input ceramic capacitors as shown in Figure4. These
capacitors range from 0.1μF to 0.47μF and are often
needed for high frequency designs. If the additional 0402
capacitors are not added to the layout then the bulk input
ceramic capacitors should be moved as close as possible
to the VIN pins.
The LTC3310/LTC3310-1 does not have any internal
bypass capacitors and hence requires three additional
0201 external capacitors (CIN5, CIN6, and CIN7), as shown
in Figure 5. Place these capacitors as close as possible
to the ICs.
To avoid noise coupling into FB, the resistor divider should
be placed near the FB and AGND pins and physically
close to the LTC3310S. The remote output and ground
traces should be routed together as a differential pair to
the remote output. These traces should be terminated as
close as physically possible to the remote output point
that is to be accurately regulated through remote differ-
ential sensing.
See Figure4 and Figure5 for a recommended PCB layouts.
Large, switched currents flow in the LTC3310S VIN, SW
and PGND pins and the input capacitors. The loops formed
by the input capacitors should be as small as possible by
placing the capacitors adjacent to the VIN and PGND pins.
Place the input capacitors, inductor and output capaci-
tors on the same layer of the circuit board. Place a local,
unbroken ground plane under the application circuit on
the layer closest to the surface layer.
The SW node should be as short as possible. Finally,
keep the FB and RT nodes small and away from the noisy
SWnode.
Figure5. Recommended PCB Layout for the LTC3310
COUT1 COUT2
L
CIN1
RB
RA
CFF
CIN2
CIN4
CIN3
GND
TO VOUT & GND
REMOTE SENSE
GND
VIN
GROUND PLANE ON LAYER 2
VOUT
CSS
RC
CC2
CC1
RT
3310S1 F04
1 14
5 10
18 15
19
6 9
(OPT)(OPT)
COUT1 COUT2
L
CIN1
RB
RA
CFF
CIN2
CIN6
CIN5
CIN7
GND GND
VIN
GROUND PLANE ON LAYER 2
VOUT
CSS
RC
CC2
CC1
RT
3310S1 F05
1 14
5 10
18 15
19
6 9
TO VOUT & GND
REMOTE SENSE
heat dissipated by the LTC3310S. Placing additional vias
can reduce thermal resistance further. The maximum load
current should be derated as the ambient temperature
approaches the maximum junction rating. Power dissipa-
tion within the LTC3310S can be estimated by calculating
the total power loss from an efficiency measurement and
subtracting the inductor loss. The die temperature is mon-
itored with the SSTT pin.
High Temperature Considerations
For higher ambient temperatures, care should be taken in
the layout of the PCB to ensure good heat sinking of the
LTC3310S. The PGND pins and the exposed pad on the
bottom of the package should be soldered to a ground
plane. This ground should be tied to large copper layers
below with many thermal vias; these layers will spread
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
22
Rev. E
For more information www.analog.com
Dual Phase 5V to 3.3V, 20A
LTC3310S
LTC3310S
3310S1 TA03
V
OUT
3.3V
20A
PGOOD
SW
FB
RT
EN
PGOOD
SW
FB
RT
EN
MODE/SYNC
ITH
22µF
x2
47µF
22µF
x2
47µF
0.22µF0.22µF
0.22µF
4.7pF
1µF
1µF
47µF
47µF 0.22µF
1.0pF
1.0pF
200nH
200nH
15k
1M
100k
390pF 0.1µF
PGOOD
VIN
V
IN
4.5V TO 5.5V
PGNDAGNDSSTT
VIN
VIN
VIN
PGNDAGND
274k
100k
48.7k
274k
180°
L = COILCRAFT, XEL4030-201ME
MODE/SYNC
ITH
APPLICATIONS INFORMATION
TYPICAL APPLICATIONS
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
23
Rev. E
For more information www.analog.com
TYPICAL APPLICATIONS
Three Phase, 0.6V, 30A
LTC3310S
LTC3310S
LTC3310S
3310S1 TA04
V
OUT
0.6V
30A
47µF
47µF
47µF
PGOOD
SW
FB
RT
EN
MODE/SYNC
ITH
PGOOD
SW
FB
RT
EN
MODE/SYNC
ITH
PGOOD
SW
FB
RT
EN
MODE/SYNC
ITH
47µF
x2
10µF
x2
47µF
47µF
x2
10µF
x2
47µF
47µF
x2
10µF
x2
47µF
1µF
1µF
0.22µF
0.22µF
0.22µF
0.22µF
12pF
0.22µF
0.22µF
1µF
100nH
100nH
100nH
100k
10k
390pF
0.1µF
VIN
V
IN
2.25V TO 4.5V
PGNDAGNDSSTT
VIN
VIN
VIN
VIN
PGNDAGND
VIN
VIN
PGNDAGND
243k
174k
86.6k
432k
174k
274K
243k
120°
240°
L = WURTH ELEKTRONIK, 744373240010
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
24
Rev. E
For more information www.analog.com
TYPICAL APPLICATIONS
Four Phase, 2MHz, 1.2V, 40A
LTC3310S
LTC3310S
LTC3310S
LTC3310S
3310S1 TA05
V
OUT
1.2V
40A
PGOOD
SW
FB
RT
EN
MODE/SYNC
ITH
PGOOD
SW
FB
RT
EN
MODE/SYNC
ITH
PGOOD
SW
FB
RT
EN
MODE/SYNC
ITH
PGOOD
SW
FB
RT
EN
MODE/SYNC
ITH
22µF
x2
10µF
x2
22µF
x2
10µF
x2
22µF
x2
10µF
x2
22µF
x2
10µF
x2
0.22µF
0.22µF
0.22µF
0.22µF
0.22µF
0.22µF
0.22µF
0.22µF
47µF1µF
100nH
47µF1µF
100nH
47µF1µF
100nH
47µF1µF
47µF
47µF
47µF
47µF
100nH
0.1µF
10k
390pF
VIN
V
IN
2.25V TO 5.5V
PGNDAGNDSSTT
VIN
VIN
VIN
VIN
VIN
PGNDAGND
VIN
VIN
PGNDAGND
VIN
VIN
PGNDAGND
301k
100k
100k
301k
180°
90°
270°
140k
100k
6.8pF
274k
L = COILCRAFT, XEL4030-101ME
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
25
Rev. E
For more information www.analog.com
TYPICAL APPLICATIONS
Four Phase, 2MHz, 1.2V, 40A Driven with External Clock
EXTERNAL
CLOCK LTC3310S
LTC3310S
LTC3310S
LTC3310S
3310S1 TA06
V
OUT
1.2V
40A
PGOOD
SW
FB
RT
EN
MODE/SYNC
ITH
PGOOD
SW
FB
RT
EN
MODE/SYNC
ITH
PGOOD
SW
FB
RT
EN
MODE/SYNC
ITH
PGOOD
SW
FB
RT
EN
MODE/SYNC
ITH
22µF
x2
10µF
x2
22µF
x2
10µF
x2
22µF
x2
10µF
x2
22µF
x2
10µF
x2
0.22µF
0.22µF
0.22µF
0.22µF
0.22µF
0.22µF
0.22µF
0.22µF
47µF1µF
100nH
47µF1µF
100nH
47µF1µF
100nH
47µF1µF
47µF
47µF
47µF
47µF
100nH
0.1µF
10k
390pF
VIN
V
IN
2.25V TO 5.5V
PGNDAGNDSSTT
VIN
VIN
VIN
VIN
VIN
PGNDAGND
VIN
VIN
PGNDAGND
VIN
VIN
PGNDAGND
301k
100k
100k
301k
180°
90°
270°
140k
100k
6.8pF
VIN
L = COILCRAFT, XEL4030-101ME
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
26
Rev. E
For more information www.analog.com
TYPICAL APPLICATIONS
LTC3310S, 5MHz, 1V, 10A
3310S1 TA07
VOUT
1V
10A
EN
MODE/SYNC
SSTT
ITH
PGOOD
SW
FB
AGND
RT
22µF
×3
L = XF303020LT-50NM, XFMR INC.
VIN
PGND
LTC3310S
100k
V
IN
3.0V TO 3.6V
649k
100k
22µF
15k10pF
220pF
22µF 0.22µF0.22µF
0.1µF
100k10pF
100k
50nH
LTC3310S, 2MHz, 3.3V, 10A, Forced Continuous
3310S1 TA08
EN
MODE/SYNC
SSTT
ITH
V
OUT
3.3V
10A
PGOOD
SW
FB
AGND
RT
PGOOD
VIN
V
IN
4.5V TO 5.5V
PGND
LTC3310S
1M
100k
22µF
562k15pF
100k
200nH
100k
VIN
VIN
VOUT
10k
220pF
22µF
0.1µF 22µF
x2
L = COILCRAFT, XEL4030-201ME
LTC3310, 1.2V 10A, Step-Down Converter
3310S1 TA09
140k
22µF
×3
100k
V
OUT
1.2V
10A
15pF
274k
L = XEL4030-101ME, COILCRAFT
22µF 22µF
0.1µF
SW
FB
AGND
RT
EN
MODE/SYNC
PGOOD
SSTT
ITH
0.1µF 0.1µF
10k
220pF
VIN
V
IN
2.25V TO 5.5V
PGND
LTC3310
100nH
0.1μF
VIN
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
27
Rev. E
For more information www.analog.com
TYPICAL APPLICATIONS
3310S1 TA11
EN
MODE/SYNC
SSTT
ITH
VOUT
1V
10A
PGOOD
SW
VOUT
AGND
RT
PGOOD
VIN
VIN
3.3V ±10%
PGND
LTC3310S-1
1M
249k
22µF
100nH
VIN
13.3k
330pF
22µF 0.1µF 0.1µF
0.1µF 47µF
x5
L = COILCRAFT, XEL4030-101ME
100k
VOUT
LTC3310S-1, 2MHz, 1.0V, Forced Continuous
1.5A DC to 7.5A Step Load 6A/µs Transient, <3% Total Variation
LTC3310S, High Efficiency, 2MHz, 0.5V, 10A, Pulse Skip, Low Part Count
3310S1 TA10
VOUT
0.5V
10A
PGOOD
SW
FB
AGND
RT
EN
47µF
×4 1MΩ
VIN
PGND
LTC3310S
VIN
2.25V TO 4.3V 22µF 22µF
15k
VIN
270pF
0.1µF
100nH
L = COILCRAFT, XEL4030-101ME
MODE/SYNC
SSTT
ITH
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
28
Rev. E
For more information www.analog.com
LTC3310-1, 2MHz, 1.0V, Forced Continuous
1.5A DC to 7.5A Step Load 6A/µs Transient, <3% Total Variation
3310S1 TA12a
EN
MODE/SYNC
SSTT
ITH
VOUT
1V
10A
PGOOD
SW
VOUT
AGND
RT
PGOOD
VIN
VIN
3.3V ±10%
PGND
LTC3310-1
1M
249k
22µF
100nH
VIN
15k
330pF3.3pF
22µF 0.1µF 0.1µF
0.1µF 47µF
x5
0.1µF
L = COILCRAFT, XEL4030-101ME
100k
VOUT
VIN
TYPICAL APPLICATIONS
Forced Continuous Mode
LTC3310–1
3.3V
IN TO 1.0V
OUT
LOADSTEP 1.5A TO 7.5A 6A/µs
10µs/DIV
I
OUT
2A/DIV
1.0V
V
OUT
10mV/DIV
3310S1 TA12b
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
29
Rev. E
For more information www.analog.com
3310S1 TA13
VOUT
1.0V
10A
PGOOD
SW
VOUT
AGND
RT
EN
22µF
×3
VIN
PGND
LTC3310S-1
VIN
2.25V TO 5.5V 22µF 0.1µF 0.1µF 22µF
2.80k
178k
680pF
0.1µF
72nH
L = COILCRAFT, XEL3515-720MEB
MODE/SYNC
SSTT
ITH
LTC3310S-1, 3MHz, 1.0V, 10A
TYPICAL APPLICATIONS
LTC3310S-1, 5MHz, 1.0V, 10A
3310S1 TA14
22µF
×3
VOUT
1.0V
10A
100k
L = XF303020LT-50NM, XFMR INC.
22µF 22µF
0.1µF
SW
VOUT
AGND
RT
EN
MODE/SYNC
PGOOD
SSTT
ITH
0.1µF 0.1µF
3.74k
1.5pF
VIN
VIN
2.25V TO 5V
PGND
LTC3310S-1
50nH
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
30
Rev. E
For more information www.analog.com
PACKAGE DESCRIPTION
LQFN Package
18-Lead (3mm × 3mm × 0.94mm)
(Reference LTC DWG # 05-08-1548 Rev C)
DETAIL B
A
PACKAGE TOP VIEW
4
PIN 1
CORNER
X
Y
aaa Z2×
PACKAGE BOTTOM VIEW
3
6
SEE NOTES
D
E
be
e
b
D1
E1
DETAIL B
SUBSTRATE
MOLD
CAP
// bbb Z
Z
H2
H1
DETAIL C
SUGGESTED PCB LAYOUT
TOP VIEW
0.0000
0.0000
1.0000
0.5000
0.5000
1.0000
0.7500
0.2500
0.2500
0.7500
PIN 1 NOTCH
0.25 × 45°
15 18
9 6
1
5
14
10
aaa Z
2×
MX YZccc
MX YZccc
PACKAGE
OUTLINE
0.25
0.70
3.50 ±0.05
3.50 ±0.05
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN
SO AS NOT TO OBSCURE THESE TERMINIALS AND HEAT FEATURES
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE
LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER
MAY BE EITHER A MOLD OR MARKED FEATURE
LQFN 18 1218 REV C
TRAY PIN 1
BEVEL PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN 1
6 THE EXPOSED HEAT FEATURE MAY HAVE OPTIONAL CORNER RADII
LTXXXXXX
0.250
0.440
0.250
DETAIL A
ddd Z
18×
18b e
SYMBOL
A
A1
L
b
D
E
D1
E1
e
H1
H2
aaa
bbb
ccc
ddd
eee
fff
MIN
0.85
0.01
0.30
0.22
NOM
0.94
0.02
0.40
0.25
3.00
3.00
1.51
1.70
0.50
0.24 REF
0.70 REF
MAX
1.03
0.03
0.50
0.28
0.10
0.10
0.08
0.10
0.15
0.08
NOTES
DIMENSIONS
Z
A1
DETAIL C
DETAIL A
MX YZeee
MZfff L
e/2
SUBSTRATE THK
MOLD CAP HT
0.20
0.39
0.20
1.51
1.70
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
31
Rev. E
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 12/18 Added Thermal Package Information
Modified Order Information
Changed Pin Configuration Package Description
Changed Inductor
2
2
2
23
B 06/19 Added Typical Performance Curves
Modified Package Drawing
5-9
28
C 03/20 Added LTC3310S-1 Option to Order Information
Modify Pin Configuration, Abs Max Ratings
Added LTC3310S-1 Option Specifications
Added LTC3310S-1 Option Typ Performance Curves
Added LTC3310S-1 Option VOUT Pin Function
Modified Block Diagram for LTC3310S-1 Option
Modified Operation Section for LTC3310S-1 Option
Modified Applications Section for LTC3310S-1 Option
Added LTC3310S-1 Option Application Circuits
2
2
3
4-8
10
11
13
14-21
28
D 06/20 Added LTC3310 and LTC3310-1 Part Numbers
Added Condition IOUT = 4A to Regulated Output Voltage LTC3310S-1
Modified VIN Pin Functions Section
Added Note 2 on Block Diagram
Modified Voltage Regulation Section
Modified Low EMI PCB Layout Section
All
3
10
11
12
21
E 09/20 Added LTC3310-1 #W in Order Info
Figs 4 & 5, added line drawings with label “To VOUT & GND Remote Sense” on PCB layout
3
21
LTC3310S/LTC3310S-1
LTC3310/LTC3310-1
32
Rev. E
For more information www.analog.com
ANALOG DEVICES, INC. 2018-2020
www.analog.com
09/20
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3310S1 TA02
VOUT
1.0V
10A
PGOOD
SW
FB
AGND
RT
EN
22µF
×3
VIN
PGND
LTC3310S
VIN
2.25V TO 5.5V 22µF 22µF
100k10pF
100k
15k
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220pF
0.1µF
72nH
L = COILCRAFT, XEL3515-720MEB
MODE/SYNC
SSTT
ITH