BUE D MH 2614130 0007452 S36 MEDAL DS5001FP DALLAS SEMICONDUCTOR CORP DALLAS SEMICONDUCTOR DS5001FP 128K Soft Micro Chip FEATURES 8051 compatible uC adapts to its task Accesses up to 128K bytes of nonvolatile SRAM In-system programming via onchip serial port Can modify its own program or data memory Accesses memory on a separate Bytewide bus Performs CRC16 check of NVRAM memory Decodes memory and peripheral chip enables Crashproof Operation Maintains all nonvolatile resources for over 10 years Power-fail Reset Early Warning Powerfail Interrupt Watchdog Timer Lithium backs user SRAM for program/data storage Precision band-gap reference for power monitor Fully 8051 Compatible 128 bytes scratchpad RAM Two timer/counters On-chip serial port 32 parallel VO port pins Software Security Available (DS5002FP) DESCRIPTION The DS5001FP is an 8051 compatible microcontroller based on nonvolatile RAM technology. It is designed for systems that need large quantities of nonvolatile memory. Like its predecessor the DS5000, the DS5001FP is substantially more flexible than a stan- dard 8051. It provides full compatibility with the 8051 instruction set, timers, serial port, and parallel /O ports. By using NVRAM instead of ROM, the user can pro- PIN ASSIGNMENT 80 79 76 77 78 75 7473 7271 70 60 68.67 66 OS O ODER ON = DS5001FP ZBELESSESSLRASSRSAITSSABRE gram, then reprogram the microcontroller while in~sys- tem. The application software can even change its own operation. This allows frequent software upgrades, adaptive programs, customized systems, etc. In addi- tion, by using NVSRAM, the DS5001 FP is ideal for data logging applications. It also connects easily to a Dallas Realtime Clock for time stamp and date. 267 082893 1/23E ee bHE D DSS001FP The DS5001FP provides the benefits of NVRAM with- out using VO resources. It uses a nonmultiplexed Bytewide address and data bus for memory access. This bus can perform all memory access and provides decoded chip enables for SRAM. This leaves the 32 I/O port pins free for application use. The DS5001FP uses ordinary SRAM and battery backs the memory contents with an user's external lithium cell. Data is maintained for over 10 years with a very small lithium cell. A DS5001 FP also provides crashproof operation in porta- ble systems or systems with unreliable power. These features inctude the ability to save the operating state, Power-fail Reset, Power-fail Interrupt, and Watchdog Timer. A user loads programs into the DS5001FP via its on- chip Serial Bootstrap Loader. This function supervises the loading of software into NVRAM, validates it, then becomes transparent to the user. Software can be stored in multiple 32K or one 128K byte CMOS SRAM(s). Using its internal Partitioning, the DSS001FP can divide a common RAM into user selectable pro- gram and data segments. This Partition canbe selected at program loading time, but can be modified anytime later. The micro will decode memory access to the SRAM, access memory via its Byte-wide bus and write-protect the memory portion designated as ROM. Combining program and data storage in one device saves board space and cost. The DS5001 FP offers several bank switches for access to even more memory. In addition to the primary data MB 2614130 00074935 472 BDAL area of 64K bytes, a peripheral selector creates a second 64K byte data space with four accompanying chip enables. This area can be used for memory mapped peripherals or more data storage. The DS5001FP can also use its Expanded bus on Ports 0 and 2 (like an 8051) to access an additional 64K bytes of data space. Lastly, the DS5001FP provides one addi- tional bank switch that changes up to 60K bytes of the NVRAM program spaca into data memory. Thus with a small amount of logic, the DS5001 accesses up to 252K bytes of data memory. For a user that wants a preconstructed module using the DS5001FP, RAM, lithium cell, and optional clock; the DS2251(T) is available and described in separate data sheet. More details are also contained in the Users Guide section of the Soft Microcontroller Data Biook. For users that desire software security, the DS5002FP is functionally identical to the DS5001 FP but provides the best firmware security available, ORDERING INFORMATION Part Number Max. Crystal Speed DS5001FP-12 12 MHz DS5001FP-16 16 MHz Operating information is contained in the User's Guide saction of the Soft Microcontroller Data Book. This data sheet provides ordering information, pinout, and olec- trical specifications. DALLAS SEMICONDUCTOR CORP 052893 2/23 268BYE D MM 2644330 0007494 309 MEDAL DSS001FP DS5001FP BLOCK DIAGRAM Figure 1 DALLAS SEMICONDUCTOR CORP XTAL4 WATCHDOG TIMER RW XTAL2 CE4 BAISO RST ALE 8 BD7-0 PSEN 9 8 EA 25 9 g _ go PE1-4 fad voco REGISTERS DATA REGISTERS (128 BYTES) PL.7 Vu P10 P2.7 BOOTSTRAP P2.0 LOADER ROM P3.7 P3.0 052893 23 269BYE D WM 263443350 0007495 245 MMDAL DS5001FP PIN DESCRIPTION DALLAS SEMICONDUCTOR CORP PIN NUMBER DESCRIPTION 11,9, 7,5, 1,79, 77, 75 P0.0-P0.7 General purpose I/O Port 0. This port is open-drain and can not drive a logic 1. It requires external pull-ups. Port 0 is also the multiplexed Expanded Address/Data bus. When used in this mode, it does not require pull-ups. 15, 17, 19, 21, 25, 27, 29, 31 P1.0-P1.7 General purpose I/O Port 1. 49, 50, 51, 56, 58, 60, 64, 66 P2.0P2.7 General purpose lO Port 2. Also serves as the MSB of the address in expanded memory accesses, and as pins of the RPC mode when used. 36 P3.0 RXD General purpose VO port pin 3.0. Also serves as the receive signal for the on board UART. This pin should NOT be connected directly to a PC COM port. 38 P3.1 TXD General purpose I/O port pin 3.1. Also serves as the transmit signal for the on board UART. This pin should NOT be connected directly toa PC COM port. 39 P3.2 INTO General purpose I/O port pin 3.2. Also serves as the active low External Inter- 0. rupt 40 P3.3 INTT General purpose I/O port pin 3.3. Also serves as the active low External Inter- rupt 1. 41 P3.4 TO General purpose VO port pin 3.4. Also serves as the Timer 0 input. 44 P3.5 T1 General purpose V/O port pin 3.5. Also serves as the Timer 1 input. 45 P3.6 WR General purpose I/O port pin. Also serves as the write strobe for Expanded bus operation. 46 P3.7 RB General purpose I/O port pin. Also serves as the read strobe for Expanded bus operation. 34 RST Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin is pulled down internally so this pin can be left unconnected if not used. An RC power-on reset circuit is not needed and is NOTrecommended. 68 PSEN Program Store Enable. This active low signal is used to enable an external program memory when using the Expanded bus. It is normally an output and should be unconnected if not used. PSEN also is used to invoke the Boot- strap Loader. At this time, PSEN will be pulled down externally. This should only be done once the DS5001FP is already in a reset state. The device that pulls down should be open drain since it must not interfere with PSEN under normal operation. 70 ALE Address Latch Enable. Used to demultiplex the multiplexed Expanded Address/Data bus on Port 0. This pin is normally connected to the clock input on a '373 type transparent latch. 052893 4/23 270BYE D MB 2614130 0007456 181 MEDAL DS5001FP DALLAS SEMICONDUCTOR CORP PIN NUMBER DESCRIPTION 47, 48 XTAL2, XTAL1 Used to connect an external crystal to the internal oscillator. XTAL1 is the input to an inverting amplifier and XTAL2 is the output. 52 GND Logic ground. 13 Veo +5V 12 Veco Voc Output. This is switched between Voc and V_; by internal circuits based on the level of Ver. When power is above the lithium input, power will be drawn from Vec. The lithium call remains isolated from a load. When Voc is below V;, the Voco switches to the V_; source. Veco should be connected to the Voc pin of an SRAM. 54 Vu Lithium Voltage Input. Connect to a lithium cell greater than Vijmin and no greater than V__\max a5 shown in the electrical specifications. Nominal value is +3V. 3, 16, 8, 18, 80, 76, 4, 6, 20, 24, | BA15~0 26, 28, 30, 33, 35, 37 Bytewide Address bus bits 15-0. This bus is combined with the nonmulkti- plexed data bus (BD70) to access NVSRAM. Decoding is performed using CE1 through CE4. Therefore, BA15 is not actually needed except for moni- toring and debugging. Read/write access is controlled by R/W. BA140 con- nect directly to an 8K, 32K, or 128K SRAM. If an 8K RAM is used, BA13 and BA14 will be unconnected. if a 128K SRAM is used, the micro converts CE2 and CES to serve as A16 and A15 respectively. 71, 69, 67, 65, 61, 59, 57, 55 BD7-0 Bytewide Data bus bits 7-0. This 8 bit bi-directional bus is combined with the nonmultiplexed address bus (BA14~0) to access NVSRAM. BD7-0 connect directly to an SRAM, and optionally to a Realtime Clock or other peripheral. 10 RW Read/Write. This signal provides the write enable to the SRAMs on the Byte wide bus. It is controlled by the memory map and Partition. The blocks selected as Program (ROM) will be write protected. 74 CET Chip Enable 1. This is the primary decoded chip enable for memory access on the Bytewide bus. it connects to the chip enable input of one SRAM. CET is lithium backed. It will remain in a logic high inactive state when Vcc falls below Vi). 72 CEIN Non battery backed version of chip enable 1. This can be used with a 32K byte EPROM. It should not be used with a battery backed chip. CE2 Chip Enable 2. This chip enable is provided to access a second 32K block of memory. It connects to the chip enable input of one SRAM. When MSEL=0, the micro converts CEZ into A16 for a 128K x 8 SRAM.CE2 is lith- ium backed and will remain at a logic high when Vcc falls below V\). CE3 Chip Enable 3. This chip enable is provided to access a third 32K block of memory. It connects to the chip enable input of one SRAM. When MSEL=0, the micro converts CE3 into A15 for a 128K x 8 SRAM. CE3is lithium backed and will remain at a logic high when Vcc falls below V_). 052893 5/23 271b4YE D MM 2614130 OO0749? O16 MMDAL DS5001 FP DALLAS SEMICONDUCTOR CORP PIN NUMBER DESCRIPTION 62 CE4 Chip Enable 4. This chip enable is provided to access a fourth 32K block of memory. It connects to the chip enable input of one SRAM. When MSEL=0, this signal is unused. CE4 is lithium backed and will remain at a logic high when Vcc falls below V_. 78 PET Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh when the PES bit is set to a logic 1. Commonly used to chip enable a Bytewide real-time Clock such as the DS1283. PE? is lithium backed and will remain at a logic high when Vcc falls below V,;. Connect PE1 to battery backed functions only. 3 PE2 Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh when the PES bit is set to a logic 1. PE2 is lithium backed and will remain at a logic high when Voc falls below V,). Connect PE2 to battery backed functions only. 22 PES Peripheral Enable3. Accesses data memory between addresses 8000h and BFFFh when the PES bit is set to a logic 1. PE3 is not lithium backiad and can be connected to any type of peripheral function. If connected to a battery backed chip, it will need additional circuitry to maintain the chip enable in an inactive state when Vcc < Vij. 23 PE4 Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when the PES bit is set to a logic 1. PE4 is not lithium backed and can be connected to any type of peripheral function. If connected to a battery backed chip, it will need additional circuitry to maintain the chip enable in an inactivestate when Voc < VL. 32 PROG Invokes the Bootstrap loader on a falling edge. This signal should be debounced so that only one edge is detected. If connected to ground, the micro will enter Bootstrap loading on power up. This signal is pulled up internally. 42 VRST This VO pin indicates that the power supply (Vcc) has fallen below the Vocmin level and the micro is in a reset state. When this occurs, the DS5001 FP will drive this pin to a logic 0. Because the microis lithium backed, this signal is guaranteed even when Vcc=0V. Because it is an I/O pin, it will also force a reset if pulled low externally. This allows multiple parts to syn- chronize their powerdown resets. 43 PF This output goes to a logic 0 to indicate that the micro has switched to lithium backup. This corresponds to Vcc < Vi). Because the micro is lithium backed, this signal is guaranteed even when Vcc=0V. The normal application of this signal is to control lithium powered current to isolate battery backed functions from non-battery backed functions. 14 MSEL Memory select. This signal controls the memory size selection. When MSEL= +5V, the DS5001FP expects to use 32K x 8 SRAMs. When MSEL = OV, the DS5001FP expects to use a 128K x 8 SRAM. MSEL must be con- nected regardiess of Partition, Mode, ate. 73 NC Do not connect. 052893 6/23 272BYE D WM 26441430 0007498 TS4Y MMDAL DS5001FP DALLAS SEMICONDUCTOR CORP INSTRUCTION SET MEMORY ORGANIZATION The DSS5001FP executes an instruction set that is object code compatible with the industry standard 8051 microcontroller. As a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the DS5001FP. A complete description of the instruction set and operation are provided in the User's Guide sec- tion of the Soft Microcontroller Data Book. Also note that the DS5001FP is embodied in the DS2251(T) module. The DS2251(T) combines the DS5001FP with between 32K and 128K of SRAM, anda lithium cell. An optional Realtime Clock is also avail- able in the DS2251T. This is packaged ina 72-pin SIMM module. Figure 2 illustrates the memory map accessed by the DSS5001FP. The entire 64K of program and 64K of data are potentially available to the Bytewide bus. This pre- serves the I/O ports for application use. The user con- trols the portion of memory that is actually mapped to the Byte-wide bus by selecting the Program Range and Data Range. Any area not mapped into the NVRAM is reached via the Expanded bus on Ports 0 and 2. An alternate configuration allows dynamic Partitioning of a 64K space as shown in Figure 3. Selecting PES=1 pro- vides another 64K of potential data storage or memory mapped peripheral space as shown in Figure 4. These selections are made using Special Function Registers. The memory map and its controls are covered in detail in the Users Guide section of the Soft Microcontroller Data Book. MEMORY MAP OF THE DS5001FP WITH PM=1 Figure 2 PROGRAM __ RANGE 255 127 128 o SPECIAL DATA FUNCTION REGISTERS REGISTERS LEGEND: [| = ON-CHIP REGISTERS 64K DATA RANGE NONVOLATILE - PROGRAM / fees : - NONVOLATILE DATA _RAM PROGRAM DATA MEMORY MEMORY PROGRAM RANGE EITHER 32K OR 64K DATA RANGE EITHER 32K OR 64K ACCESSED VIA BYTEWIDE BUS ~ ACCESSED VIAEXPANDED BUS (PORTS 0 AND 2) 052893 7/23BYE D MM 2614130 0007499 950 MBDAL DS5001FP DALLAN SEMICONDUCTOR CORP MEMORY MAP OF THE DS5001FP WITH PM-0 Figure 3 64K RANGE NONVOLATILE DATA RAM PARTITION pesssstiunate NONVOLATILE ass procs 127 128 0 SPECIAL PROGRAM DATA DATA FUNCTION MEMORY MEMORY REGISTERS REGISTERS LEGEND: [ = ON-CHIP REGISTERS = ACCESSED VIA BYTEWIDE BUS ACCESSED VIA EXPANDED BUS {PORTS 0 AND 2} MEMORY MAP OF THE DS5001FP WITH PES=1 Figure 4 PROGRAM MEMORY DATA MEMORY (MOVX} FFFH See TET] Bak mea cooth 48k ae UY a000h 32K Uj} 4000h 16K o000h Re NOT ACCESSIBLE 052809 8/23 274DS001 FP b4YE D M@M@ 2614130 0007500 43c MMDAL DALLAS SEMICONDUCTOR CORP Figure 5 illustrates a typical memory connection for a using two 32K byte SRAMs. The Bytewide Address system using a 128K byte SRAM. Note that in this con- bus connects to the SRAM addrass lines. The bi-direc- figuration, both program and data are stored in a com- tional Bytewide data bus connects the data I/O lines of mon RAM chip Figure 6 shows a similar system with the SRAM. DS5001FP CONNECTION TO 128K X 8 SRAM Figure 5 DS5001FP HM628128 PLO] Bau BD?7-BDo 052803 a/23 275BYE D DS5001FP MB 2644130 0007501 3759 MMDAL DALLAN SEMICONDUCTOR CORP DS5001FP CONNECTION TO 64K X 8 SRAM Figure 6 DS5001FP 12 HM62256 10 +3V LITHIUM Vv eo NE oe adAU0) 12] By = Bie) POWER MANAGEMENT The DS5001FP monitors Vcc to provide Power-fail Reset, early warning Power-fail Interrupt, and switch over to lithium backup. It uses an internal band-gap ref- erence in determining the switch points. These are called Vprw, Vocmin; and V,| respectively. When Voc drops below Vpry, the DS001 FP will perform an inter- rupt vector to location 2Bh if the power fail warning was enabled. Full processor operation continues regard- less. When power falls further to Vocmin, the DS5001FP invokes a reset state. No further code execution will be performed unless power rises back above Vocmin. All decoded chip enables and the R/W signal go to an inactive (logic 1) state. Voc is still the power source at this time. When Vcc drops further to | num below V_), internal circuitry will switch to the lithium cell for power. The majority of internal circuits will be dis- abled and the remaining nonvolatile states will be retained. Any devices connected to Veco will be pow- ered by the lithium call at this time. Veco will be at the lithium battery voltage less a diode drop. This: drop will vary depending on the load. Low power SRAMs should be used for this reason. When using the DS5001FP, the user must select the appropriate hattery to rnatch the RAM data retention current and the desired backup life- time. Note that the lithium cell is only loaded when Vcc < Vi. The Users Guide has more information on this topic. The trip points Vecqin and Vppy are listed in the electrical specifications. 052893 10/23 276BYE D MM 2bb41350 0007502 205 MMDAL DALLAS SEMICONDUCTOR CORP DS5001FP ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.3V to 7.0V Operating Temperature 0C to +70C Storage Temperature 40C to 70C Sokering Temperature 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. DC CHARACTERISTICS (ta=0C to 70C; Voo=5V + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Low Voltage Vit 0.3 0.8 Vv 1 Input High Voltage Vina 2.0 Vect+0.3 Vv 1 Input High Voltage (RST, XTAL1, Vine 3.6 Vect0.3 Vv 1 PROG) Output Low Voltage Vou 0.15 0.45 Vv @ Iqu=1.6 mA (Ports 1, 2, 3) Output Low Voltage Voie 0.15 0.45 Vv 1 @ '!q.=3.2mA (Port 0, ALE, PSEN, PF, BA150, BD7-0, R/W, CEIN, CE1-4, PE1-4) Output High Voltage Vou 2.4 4.8 Vv 1 @ loy=80 mA (Ports 1,2, 3) Output High Voltage Vou2 2.4 4.8 Vv 1 @ Ioy=~400 pA (Ports 0, ALE, PSEN, PF, BA15-0, BD7-0, R/W, CEIN, CE14, PE14) Input Low Current Ie 50 pA Vin=0.45V (Ports 1, 2, 3) Transition Current; 1 to 0 I 500 pA Vin=2.0V (Ports 1, 2, 3) 052893 11/23 277BYE D MM 2614130 0007503 141 MMDAL DS5001FP DALLAS SEMICONDUCTOR CORP DC CHARACTERISTICS (cont'd) (ta=O0C to 70C; Voo=5V + 10%) PARAMETER SYMBOL MiN TYP MAX UNITS NOTES Input Leakage Current tie +10 pA 0.45<Vin, Voc (Port 0, MSEL) RST Pulkdown Resistor Rre 40 150 KQ. VRST Pullup Resistor Rvr_ 4.7 KQ PROG Pullup Resistor Rer 40 KO Power Fail Warning Voltage Verw 4.25 4.37 4.50 Vv 1 Minimum Operating Voltage VocmIN 4.00 4.12 4.25 Vv 1 Lithium Supply Voltage Vit 2.5 4.0 Vv 1 Operating Current loc 36 mA 2 Idle Mode Current hoLe 7.0 mA 3 Stop Mode Current Istop 80 pA 4 Pin Capacitance Cin 10 pF 5 Output Supply Voltage (Veco) Voco1 . Vec0.3 v 1,2 Output Supply Batterybacked Veco2 Vir-0.55 Vv 1,8 Mode (Veco, CE14, PE12) ; Output Supply Current lecot 75 mA 6 @ Veco=Vec 0.3V Lithiumbacked Quiescent Current I 5 75 nA 7 Reset Trip Point in Stop Mode 1 w/BAT=3.0V 4.0 4.25 w/BAT=3.3V 4.4 4.65 052809 12/23 278bYE D MM 2614130 0007504 O86 MMDAL DS5001FP DALLAS SEMICONDUCTOR CORP AC CHARACTERISTICS EXPANDED BUS MODE TIMING SPECIFICATIONS {ta=0C to70C; Voc=5V + 10%) # =|PARAMETER SYMBOL MIN MAX UNITS 1 | Oscillator Frequency Wek 1.0 12 (-12) MHz 16 (-16) 2 {ALE Pulse Width taLpw 2tcL K-40 ns 3 | Address Valid to ALE Low taVALL toiK -40 ns 4 | Address Hold After ALE Low tavAAV terk -35 ns 5 | ALE Low to Valid Instr. In @12 MHz tarivi 4tctK -150 ns @16 MHz Ato -90 6 | ALE Low to PSEN Low taLLPSL toLK -25 ns PSEN Pulse Width tpspw 3toLK -35 ns 8 | PSEN Low to Valid Instr. In @12 MHz tpsivi 3teLK -150 ns @16 MHz 3toLK -90 ns 9 | Input Instr. Hold after PSEN Going High tpsiv ) ns 10 | Input Instr. Fioat after PSEN Going High tesix terk -20 ns 11 | Address Hold after PSEN Going High tpsay toiK -8 ns 12 | Address Valid to Valid Instr. In @12 MHz tavvi Stok -150 ns @16 MHz 5terk -90 ns 13 | PSEN Low to Address Float tps_az 0 ns 14 | RD Pulse Width tropw toi -100 ns 15 | WR Pulse Width twrpw 6tcLK -100 ns 16 | RD Low to Valid Data In @12 MHz troLbv 5toik -165 ns @16 MHz Stork -105 ns 17 | Data Hold after RD High troHpv 0 ns 18 | Data Float after RD High tapHpz 2teiK -70 ns 19 | ALE Low to Valid Data In @12 MHz tattvb 8toLK -150 ns @16 MHz 8to1 K -90 ns 20 | Valid Addr. to Valid Data In @12 MHz tavpv OtcoLk -165 ns @16 MHz Stor -105 ns 21 | ALE Low to RD or WR Low taLLRDL 3toi -50 3tciK +50 ns 22 | Address Valid to RD or WR Low tavADL 4tor -130 ns 23 | Data Valid to WR Going Low tovwe\L terk -60 ns 24 | Data Valid to WR High @12 MHz tovwRH TtoLk -150 ns @16 MHz Ttor x -90 ns 25 | Data Valid after WR High tWwRHDV tork ~50 ns 26 | RD Low to Address Float trDLaz 0 ns 27 | RD or WR High to ALE High tROHALH toLk -40 tor +50 ns 052893 19/23 279err a a BYE D MM 2614150 0007505 TL4Y MDAL DS5001FP ICONDUCTOR CORP EXPANDED PROGRAM MEMORY READ CYCLE DALLAS SEM -@| ue / fo Ne }-_o + PsN / @) KO + @ 3 ORNTON - PORT 0 A7-A0 INSTR IN AT-AO @) EXPANDED DATA MEMORY READ CYCLE . a -/ - \ RD > tO. Os @- A7-AO 1 A7-AO INSTA PORT 0 (An OR DPL) DATAIN (PCL) . IN (B (20 PORT 2 P2.7-P2,0 OR A15-A8 FROM DPH x A15-A8 FROM PCH 2899 14/23 280BYE D Mi 2614130 0007506 950 MDAL OSS001FP DALLAS SEMICONDUCTOR CORP EXPANDED DATA MEMORY WRITE CYCLE ALE PSEN / \__/ ] @ WR foa\ -(3;>_@) C4) A7~AO0 A?7AO0 INSTR PORT 0 (Rn OR DPL) DATA OUT x (Pot) \{ IN PORT 2 P2.7~P2.0 OR A15A3 FROM PDH x A15-A8 FROM PCH 281 052803 15/23pssootrP BYE D MM 2614130 0007507 897 MMDAL DALLAS SEMICONDUCTOR CORP AC CHARACTERISTICS (cont'd) EXTERNAL CLOCK DRIVE (ta = 0C to70C; Voc = 5V +1 0%) # | PARAMETER SYMBOL MIN MAX UNITS 28 | External Clock High Time toLKHPW 20 ns @16 MHz 15 ns 29 | External Clock Low Time tcoLKLPW 20 ns @16 MHz 15 ns 30 } External Clock Rise Time toLKR 20 ns @16 MHz 15 ns 31 | External Clock Fall Time tcLKF 20 rs @16 MHz 15 ns EXTERNAL CLOCK TIMING 3 f/f > @) 6) a es O aad 052803 16/23 282BYE D MM 26144350 OO0O7508 723 MDAL DS5001FP DALLAS SEMICONDUCTOR CORP AC CHARACTERISTICS (cont'd) POWER CYCLING TIMING (ta = 0C to70C; Veg = 5V + 10%) # | PARAMETER SYMBOL MIN MAX UNITS 32 | Slew Rate from Vecmin to Vin te 130 ps 33 | Crystal Start up Time tcsu (note 9) 34 | Power On Reset Delay tpor 21504 tok POWER CYCLE TIMING Veo _~ Veprw Veemn - Vir - INTERRUPT SERVICE ROUTINE se UU ML_, UCU INTERNAL ) RESET LITHIUM CURRENT 052803 17/23 283BYE D MM 26144130 0007509 BET MMDAL DS5001FP DALLAS SEMICONDUCTOR CORP AC CHARACTERISTICS (contd) SERIAL PORT TIMING MODE 0 (ta = 0C to70C; Veco = 5V + 10%) # | PARAMETER SYMBOL MIN MAX UNITS 35 | Serial Port Clock Cycle Time tspcLk 12teLK ps 36 | Output Data Setup to Rising Clock Edge tpocH 10te, -133 rs 37 | Output Data Hold after Rising Clock Edge tcHDo 2torK -117 ns 38 | Clock Rising Edge to Input Data Valid tcHDv 10to_K -133 ns 39 | Input Data Hold after Rising Clock Edge tcoypiv 0 rs SERIAL PORT TIMING MODE 0 O44 CLOCK {| [| [| Ors Le DATA OUT 0 1 2 3 XxX 4 x 5 Xs 4 7? SE&TTI WRITE TO SBUF REGISTER @ INPUT DATA CX MN XX XXX KX KX XK 8 oo VALID VALID VALID VALID VALID VALID VALID CLEAR RI 052893 18/23 284B4YE D MM 26144130 0007510 381 MEDAL DSS5001FP DALLAS SEMICONDUCTOR CORP AC CHARACTERISTICS BYTEWIDE ADDRESS/DATA BUS TIMING (ta = 0C to70C; Veg = 5V 4 10%) # | PARAMETER SYMBOL MIN MAX UNITS 40 | Delay to Bytewide Address Valid from tCEILPA 30 ns CET, CE2 or CEIN Low During Opcode Fetch 41 | Pulse Width of CE1-4, PE14 or GEIN tcepw 4to 1-35 ns 42 | Byte-wide Address Hold After CE1, CE2 tcE1HPA 2toLK-20 ns or CEN High During Opcode Fetch 43 | Byto-wide Data Setup to CET, CE2 or tovceiH Itc K+40 ns CEIN High During Opcode Fetch 44 | Bytewide Data Hold After CET, CE? or tcE1HOV 10 ns CE1N High During Opcode Fetch 45 | Byte-wide Address Hold After GE1-4, tcEHDA 4tot K-30 ns PE14, or CE1N High During MOVX 46 | Delay from Bytewide Address Valid tcELDA Ato 35 ns CE14, PE14, or CE1N Low During MOVX 47 Bytewice Data Setup to CE1-4, PE14, or tpacEH ttoLK+40 ns CE1N High During MOVX (read) 48 | Bytawide Data Hold After CE1-4, PE14, tceHDy 10 ns or CETN High During MOVX (read) 49 | Bytewide Address Valid to R/W Active tavAWL 3toi K-35 ns During MOVX (write) 50 | Delay from R/W Low to Valid Data Out trwipv 20 ns During MOVX (write) 51 | Valid Data Out Hold Time from CE1-4, tcEHDV ItotK-15 ns PE14, or CETN High 52 | Valid Data Out Hold Time from R/W High tawHpv 0 ns 53 | Write Pulse Width (R/W Low Time) trwLpw 8tcL K-20 ns 052893 19723 285pssoo1FP b4YE D MM 2614130 0007511 214 MEDAL DALLAS SEMICONDUCTOR CORF BYTEWIDE BUS TIMING je actin overs pf MACHINE CLE _-+ je machine cree - Prt 2tapets torr Pepeds ls tei fefrfefapega lel ee SUSU, RW as 2 re BAD. BAIe POouT X<| _Pcour |X] _DeLAND (PHORPZSFROUT! PC OUT DPL AND (OPH OF P2 SER OUT) PG OUT _ Oye Aol nme tw 35 ree mace pT \ Gen BEY. Pe s5 On CeIn or Or) .@ @le aASe BDO- BD7 OATAIN DATAIN DATAIN DATA, s<__ vara) -C RPC AC CHARACTERISTICS DBB READ (ta = 0C to70C; Vog = 5V + 10%) # | PARAMETER SYMBOL MIN MAX UNITS 54 | CS, Ag Setup to RD tan 0 ns 55 | CS, Ao Hold After RD tra 0 ns 56 | RD Pulse Width tar 160 ns 57 | CS, Ag to Data Out Delay tap 130 ns 58 | RD to Data Out Delay trap 0 130 ns 59 | RD to Data Float Delay tapz 85 ns 052893 20/23 286BYE D RPC AC CHARACTERISTICS DBB WRITE MM 2634130 0007512 154 MDAL DS5001FP (ta = 0C to70C; Veg = 5V + 10%) # | PARAMETER SYMBOL MIN MAX UNITS 60 | CS, Ag Setup to WR taw 0 ns 61A | CS, Hold After WR twa 0 ns 61B | Ap, Hold After WR twa 20 ns 62 | WR Pulse Width tww 160 ns 63 | Data Setup to WR tow 130 ns 64 | Data Hold After WR two 20 ns AC CHARACTERISTICS DMA (ta = 0C 070C; Voc = 5V + 10%) # | PARAMETER SYMBOL MIN MAX UNITS 65 | DACK to WR or RD tacc 0 ns 66 | RD or WRto DACK tcac 0 ns 67 | DACK to Data Valid tacp 0 130 ns 68 | RD or WR to DRO Cleared tcra 110 ns AC CHARACTERISTICS ~ PROG {ta = 0C to70C; Veg = 5V + 10%) # | PARAMETER SYMBOL MIN MAX UNITS 69 | PROG Low to Active tpra 48 CLKS 70 | PROG High to Inactive teri 48 CLKS DALLAS SEMICONDUCTOR CORP 287 052893 21/23BYE D MM 2614130 0007513 O90 MEDAL D$5001FP / DALLAS SEMICONDUCTOR CORP RPC TIMING MODE READ OPERATION CSORAO = a 5 a eal G2) C2) ey DATA DATA VALID WRITE OPERATION SOR AO 60 | wa ++ i : -}-@)>"+-@) DATA _ DATA VALID ' DMA mx 8 fo om we Re DRQ NOTES: 1. All voltages are referenced to ground. 2. Maximum operating icc is measured with all output pins disconnected; XTAL1 driven with tc_kr, te_kF=10 ns, Vir = 0.5V; XTAL2 disconnected; RST = PORTO = Voc. MSEL = Vgs. 3. Idle mode lip_E is measured with all output pins disconnected; XTAL1 driven with torr: tcLKe = 10 ns, Vir = 0.5V; XTAL2 disconnected; PORTO = Voc. RST = MSEL = Vgs. 4. Stop mode Istop is measured with all output pins disconnected; PORTO = Voc; XTAL2 not connected; RST = MSEL = XTAL1 = Vss. 5. Pin Capacitance is measured with a test frequency 1 MHz, ta = 26C. 052893 22/23 288BYE D DALLAS SEMICONDUCTOR CORP MB 2614130 COO7544 T2? MEDAL DS5001FP . locor is the maximum average operating current that can be drawn from Veco in normal operation. - Voecoe is measured with Voc < Vij, and a maximum load of 10 HA on Veco. 6 7. | is the current drawn from V\; input when Veg = OV and Voco is disconnected. 8 9. . Crystal start-up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. The user should check with the crystal vendor for a worst case specification on this time. DS5001FP CMOS MICROCONTROLLER O D Taf fe ele Cc B DIM MILLIMETERS MIN NOM MAX 2.91 3.15 0.25 0.35 0.45 0.80 19.85 20.00 20.15 13.85 14.00 14.15 17.40 17.86 18.20 23.40 23.86 24.20 XIpoOtnim; oo] oOo] wo] 0.40 1.3 10 Gg ____________ 25 - Th 289 052893 23/23