1
Precision Edge®
SY89873L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
■Guaranteed AC performance
•> 2.0GHz fMAX output toggle
•> 3.0GHz fMAX input
•<800ps tPD (matched-delay between banks)
•<15ps within-device skew
•<190ps rise/fall time
■Low jitter design
•<1psRMS cycle-to-cycle jitter
•<10psPP total jitter
■Unique input termination and VT pin for DC-coupled
and AC-coupled inputs: any differential inputs
(LVPECL, LVDS, CML, HSTL)
■Precision differential LVDS outputs
■Matched delay: all outputs have matched delay,
independent of divider setting
■TTL/CMOS inputs for select and reset/disable
■Two LVDS output banks (matched delay)
•Bank A: Buffered copy of input clock (undivided)
•Bank B: Divided output (÷2, ÷4, ÷8, ÷16),
two copies
■3.3V power supply
■Wide operating temperature range: –40°C to +85°C
■Available in 16-pin (3mm ××
××
× 3mm) MLF® package
FEATURES
3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS
PROGRAMMABLE CLOCK DIVIDER
FANOUT BUFFER W/ INTERNAL TERMINATION
Precision Edge®
SY89873L
APPLICATIONS
■SONET/SDH line cards
■Transponders
■High-end, multiprocessor servers
Rev.: F Amendment: /0
Issue Date: February 2007
This 3.3V low-skew, low-jitter, precision LVDS output clock
divider accepts any high-speed differential clock input (AC- or
DC-coupled) CML, LVPECL, HSTL or LVDS and divides down
the frequency using a programmable divider ratio to create a
frequency-locked, lower speed version of the input clock. The
SY89873L includes two output banks. Bank A is an exact
copy of the input clock (pass through) with matched
propagation delay to Bank B, the divided output bank. Available
divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock
system this would provide availability of 311MHz, 155MHz,
77MHz or 38MHz auxiliary clock components.
The differential input buffer has a unique internal termination
design that allows access to the termination network through
a VT pin. This feature allows the device to easily interface to
all AC- or DC-coupled differential logic standards. A VREF-AC
reference is included for AC-coupled applications.
The SY89873L is part of Micrel’s high-speed Precision
Edge® timing and distribution family. For 2.5V applications,
consider the SY89872U. For applications that require an
LVPECL output, consider the SY89871U.
The /RESET input asynchronously resets the divider outputs
(Bank B). In the pass-through function (Bank A) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /N). Refer to the Timing
Diagram.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
FUNCTIONAL BLOCK DIAGRAM TYPICAL APPLICATION
Precision Edge is a registered trademark of Micrel, Inc.
Micro
LeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
IN
50Ω
50Ω
/IN
S0
S1
QB1
/QB1
QB0
/QB0
QA
/QA
/RESET
V
T
V
REF-AC
Divided
by
2, 4, 8
or 16
Decoder
Enable
FF
Enable
MUX
Precision Edge®
IN
/IN
QA
/QA 622MHz LVDS
Clock Out
622MHz LVPECL
Clock In
622MHz/155.5MHz
SONET Clock Generator
Bank B: 155.5MHz: For OC-3 line card
Set to divide-by-4
Bank A: 622MHz: For OC-12 line card
Set to pass-through
155.5MHz LVDS
Clock Out
OC-12 or
OC-3
Clock Gen QB
/QB
2
Precision Edge®
SY89873L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Pin Number Pin Name Pin Function
1, 2, 3, 4 QB0, /QB0 Differential Buffered Output Clocks: Divide by 2, 4, 8, 16.
QB1, /QB1 LVDS compatible.
5, 6 QA, /QA Differential Buffered Undivided Output Clock: LVDS compatible.
7, 14 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors.
8/RESET, TTL/CMOS Compatible Output Reset and Disable: Internal 25kΩ pull-up. Input threshold
/DISABLE is VCC/2. Logic LOW will reset the divider select, and align Bank A and Bank B edges. In
addition, when LOW, Banks A and B will be disabled.
12, 9 IN, /IN Differential Input: Internal 50Ω termination resistors to VT input.
See
“Input Interface Applications”
section.
10 VREF-AC Reference Voltage: Equal to VCC–1.4V (approx.), and used for AC-coupled applications.
Maximum sink/source current is 0.5mA. See
“Input Interface Applications”
section.
11 VT Termination Center-Tap: For CML and LVDS inputs, leave this pin floating. Otherwise,
see
“Input Interface Applications”
section.
13 GND Ground: Exposed pad is internally connected to GND and must be connected to a ground
plane for proper thermal operation.
16, 15 S0, S1 Select Pins: LVTTL/CMOS logic levels. Internal 25kΩ pull-up resistor. Logic HIGH if left
unconnected (divided by 16 mode). S0 = LSB. Input threshold is VCC/2.
PIN DESCRIPTION
13141516
12
11
10
9
1
2
3
4
8765
QB0
/QB0
QB1
/QB1
IN
VT
VREF-AC
/IN
S0
S1
VCC
GND
QA
/QA
VCC
/RESET
/DISABLE
16-Pin MLF® (MLF-16)
/RESET S1 S0 Bank A Output Bank B Outputs
/DISABLE
10 0 Input Clock Input Clock ÷ 2
10 1 Input Clock Input Clock ÷ 4
11 0 Input Clock Input Clock ÷ 8
11 1 Input Clock Input Clock ÷ 16
0X X QA = LOW, /QA = HIGH(1) QB0 = LOW, /QB0 = HIGH(2)
QB1 = LOW, /QB1 = HIGH(2)
Notes:
1. On the next negative transition of the input signal.
2. Asynchronous Reset/Disable function. See
"Timing Diagram."
TRUTH TABLE
Ordering Information(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY89873LMI MLF-16 Industrial 873L Sn-Pb
SY89873LMITR(2) MLF-16 Industrial 873L Sb-Pb
SY89873LMG(3) MLF-16 Industrial 873L with NiPdAu
Pb-Free bar line indicator Pb-Free
SY89873LMGTR(2, 3) MLF-16 Industrial 873L with NiPdAu
Pb-Free bar line indicator Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
3
Precision Edge®
SY89873L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings(1)
Supply Voltage (VCC).................................. –0.5V to +4.0V
Input Voltage (VIN).................................. –0.5V to VCC+0.3
LVDS Output Current (IOUT) ....................................±10mA
Input Current IN, /IN (IIN)..........................................±50mA
VREF-AC Input Sink/Source Current (IVREF-AC)(3) ............ ±2mA
Lead Temperature (soldering, 20 sec.) ..................... 260°C
Storage Temperature (TS) .......................–65°C to +150°C
Operating Ratings(2)
Supply Voltage (VCC) ...................................... +3.3V ±10%
Ambient Temperature (TA).........................–40°C to +85°C
Package Thermal Resistance
MLF® (θJA)
Still-Air .............................................................60°C/W
500 lfpm...........................................................54°C/W
MLF® (ΨJB)(4)
Junction-to-Board ............................................38°C/W
TA= –40°C to +85°C; Unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VCC Power Supply 3.0 3.3 3.6 V
ICC Power Supply Current No load, Max VCC 85 115 mA
RIN Differential Input Resistance 90 100 110 Ω
(IN-to-/IN)
VIH Input High Voltage Note 6 0.1 VCC+0.3 V
IN, /IN
VIL Input Low Voltage Note 6 –0.3 VCC V
IN, /IN
VIN Input Voltage Swing Notes 6, 7 0.1 3.6 V
VDIFF_IN Differential Input Voltage Swing Notes 6, 7, 8 0.2 V
|IIN|Input Current Note 6 45 mA
IN, /IN
VREF-AC Reference Voltage Note 9
V
CC
–1.525 V
CC
–1.425 V
CC
–1.325
V
Notes:
1. Permanent device damage may occur if
“Absolute Maximum Ratings”
are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to
“Absolute Maximum Ratings”
conditions for extended
periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. Due to the internal termination (see
“Input Buffer Structure”
) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a
combination of voltages that causes the input current to exceed the maximum limit!
7. See
“Timing Diagram”
for VIN definition. VIN(max) is specified when VT is floating.
8. See Figures 1c and 1d for VDIFF definition.
9. Operating using VIN is limited to AC-coupled PECL or CML applications only. Connect directly to VT pin.
DC ELECTRICAL CHARACTERISTICS(5)
4
Precision Edge®
SY89873L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
VCC = 3.3V ±10%; TA = –40°C to +85°C; Unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
IIH Input HIGH Current –125 20 µA
IIL Input LOW Current –300 µA
Notes:
10. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
11. Measured as per Figure 1a, 100Ω across Q and /Q outputs.
12. See Figure 1c.
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(10)
VCC = 3.3V ±10%; TA = –40°C to +85°C; Unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VOUT Output Voltage Swing Notes 11, 12 250 350 450 mV
VOH Output High Voltage Note 11 1.475 V
VOL Output Low Voltage Note 11 0.925 V
VOCM Output Common Mode Voltage Note 11 1.125 1.275 V
∆VOCM Change in Common Mode Voltage –50 50 mV
LVDS OUTPUT DC ELECTRICAL CHARACTERISTICS(10)
5
Precision Edge®
SY89873L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
VCC = 3.3V ±10%; TA = –40°C to +85°C; Unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
fMAX Maximum Output Toggle Frequency Output Swing: ≥ 200mV 2.0 GHz
(Bank A and Bank B)
Maximum Input Frequency Note 14 3.2 GHz
tPD Differential Propagation Delay Input Swing < 400mV 550 660 800 ps
(IN-to-Q) Input Swing ≥ 400mV 500 610 750 ps
tSKEW Within-Device Skew (diff.) Note 15 7 15 ps
(QB0-to-QB1)
Within-Device Skew (diff.) Note 15 12 30 ps
(Bank A-to-Bank B)
Part-to-Part Skew (diff.) Note 15 250 ps
trr Reset Recovery Time Note 16 600 ps
Tjitter Cycle-to-Cycle Jitter Note 17 1 psRMS
Total Jitter Note 18 10 psPP
tr, tfRise / Fall Time (20% to 80%) 60 110 190 ps
Notes:
13. Measured with 400mV input signal, 50% duty cycle. All outputs terminated with 100Ω between Q and /Q, unless otherwise stated.
14. Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output ÷2, ÷4, ÷8, ÷16) can accept an input frequency >3GHz,
while Bank A will be slew-rate limited.
15. Skew is measured between outputs under identical transitions.
16. See
“Timing Diagram.”
17. Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc=Tn–Tn+1, where T
is the time between rising edges of the output signal.
18. Total jitter definition: with an ideal clock input, of frequency ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by more than
the specified peak-to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS(13)
6
Precision Edge®
SY89873L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
TIMING DIAGRAM
V
IN
(Swing)
V
OUT
(Swing)
/RESET
IN
/IN
QB
/QB
QA
/QA
t
PD
t
RR
V
CC/2
LVDS OUTPUT
VOUT 100Ω
±1%
VOH, VOL
VOH, VOL
GND
Figure 1a. LVDS Differential Measurement
GND
50Ω ±1%
50Ω ±1% V
OCM,
∆V
OCM
Figure 1b. LVDS Common Mode Measurement
VIN, VOUT
350mV (Typical)
Figure 1c. Single-Ended Swing
V
DIFF_IN,
V
DIFF_OUT
700mV (Typical)
Figure 1d. Differential Swing
DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING
7
Precision Edge®
SY89873L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
TYPICAL OPERATING CHARACTERISTICS
VCC = 3.3V, VIN = 400mV, TA = 25°C, unless otherwise stated.
0
50
100
150
200
250
300
350
0 500 1000 1500 2000 2500
QA AMPLITUDE (mV)
FREQUENCY (MHz)
Output Amplitude
vs. Frequency
400
500
600
700
800
0 200 400 600 800 1000 1200
PROPAGATION DELAY (ps)
INPUT SWING (mV)
Nominal Propagation Delay
vs. Input Swing
400
500
600
700
800
-40 -20 0 20 40 60 80 100 120
PROPAGATION DELAY (ps)
TEMPERATURE (°C)
Nominal Propagation Delay
vs. Temperature
8
Precision Edge®
SY89873L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL CHARACTERISTICS
QA @ 622MHz and QB @ 155.5MHz (Divided-by-4)
/QA
QB
QA
622MHz
÷4
155MHz
/QB
TIME (1ns/div.)
Output Swing
(100mV/div.)
QA Output @ 1.25GHz
TIME (100ps/div.)
Output Swing
(50mV/div.)
QA Output @ 2.0GHz
TIME (100ps/div.)
Output Swing
(50mV/div.)
Q
/Q
Conditions: VCC = 3.3V, TA = 25°C, unless otherwise stated.
9
Precision Edge®
SY89873L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
INPUT BUFFER STRUCTURE
V
CC
GND
50Ω
50Ω
IN
V
T
/IN
1.86kΩ
1.86kΩ1.86kΩ
1.86kΩ
Figure 2a. Simplified Differential Input Stage
V
CC
GND
S0
S1
/RESET
R25kΩ
R
Figure 2b. Simplified TTL/CMOS Input
10
Precision Edge®
SY89873L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
Part Number Function Data Sheet Link
SY89871U 2.5GHz Any Diff. In-to-LVPECL Programmable www.micrel.com/product-info/products/sy89871u.shtml
Clock Divider/Fanout Buffer w/Internal Termination
SY89872U 2.5V 2GHz Any Diff. In-to-LVDS Programmable www.micrel.com/product-info/products/sy89872u.shtml
Clock Divider/Fanout Buffer w/Internal Termination
MLF® Application Note
www.amkor.com/products/notes_papers/MLF_AppNote_0902.pdf
HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml
RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION
INPUT INTERFACE APPLICATIONS
CML IN
/IN
V
T
NC
GND
SY89873L
V
CC
= 3.3V V
CC
= 3.3V
V
REF-AC
NC
Figure 3a. DC-Coupled CML
Input Interface
V
CC
0.01µF
CML IN
/IN
V
T
GND
SY89873L
V
CC
= 3.3V V
CC
= 3.3V
V
REF-AC
Figure 3b. AC-Coupled CML
Input Interface
VCC = 3.3V VCC = 3.3V
IN
/IN
VT
GND SY89873L
VREF-AC
NC
VCC
* Bypass with 0.01µF to V
CC
50Ω.01µF
VCC
–
2V*
LVPECL
Figure 3c. DC-Coupled LVPECL
Input Interface
LVPECL
IN
/IN
V
T
GND
SY89873L
V
CC
= 3.3V V
CC
= 3.3V
V
CC
GND
100Ω100Ω
V
REF-AC
0.01µF
Figure 3d. AC-Coupled LVPECL
Input Interface
LVDS IN
/IN
V
T
NC
GND
SY89873L
V
CC
= 3.3V V
CC
= 3.3V
V
REF-AC
NC
Figure 3e. LVDS
Input Interface Figure 3f. HSTL
Input Interface
11
Precision Edge®
SY89873L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
16-PIN MicroLeadFrame® (MLF-16)
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heavy Copper Plane
Heavy Copper Plane
VEE
VEE
Heat Dissipation
PCB Thermal Consideration for 16-Pin MLF® Package
(Always solder, or equivalent, the exposed pad to the PCB)
Package Notes:
1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form.
2. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
