MC32PF1550A1EP - NXP SEMICONDUCTORS

PF1550

Power management integrated circuit (PMIC) for low power

application processors

Rev. 4.0 — 28 September 2018 Data sheet: advance information

1 General description

The PF1550 is a power management integrated circuit (PMIC) designed specifically for

use with i.MX processors on low-power portable, smart wearable and Internet-of-Things

(IoT) applications. It is also capable of providing full power solution to i.MX 7ULP, i.MX

6SL, 6UL, 6ULL and 6SX processors.

With three high efficiency buck converter, three linear regulators, RTC supply, and

battery linear charger, the PF1550 can provide power for a complete battery-powered

system, including application processors, memory, and system peripherals.

1.1 Features and benefits

This section summarizes the PF1550 features:

•Input voltage range to PMIC VBUSIN pin via USB bus or AC adapter: 4.1 V to 6.0 V

•Buck converters:

–SW1, 1.0 A; 0.6 V to 1.3875 V in 12.5 mV steps, or 1.1 V to 3.3 V in variable steps

–SW2, 1.0 A; 0.6 V to 1.3875 V in 12.5 mV steps, or 1.1 V to 3.3 V in variable steps

–SW3, 1.0 A; 1.8 V to 3.3 V in 100 mV steps

–Soft start

–Quiescent current 1.0 μA in ULP mode with light load

–Peak efficiency > 90 %

–Dynamic voltage scaling on SW1 and SW2

–Modes: forced PWM quasi-fixed frequency mode, adaptive variable-frequency mode

–Programmable output voltage, current limit and soft start

•LDO regulators

–LDO1, 0.75 to 1.5 V/1.8 to 3.3 V, 300 mA with load switch mode

–LDO2, 1.8 to 3.3 V, 400 mA

–LDO3, 0.75 to 1.5 V/1.8 to 3.3 V, 300 mA with load switch mode

–Quiescent current < 1.5 μA in Low-power mode

–Programmable output voltage

–Soft start and ramp

–Current limit protection

•Battery charger

–Supports single-cell Lithium Ion/Lithium Polymer batteries

–Linear charging (10 mA to 1500 mA input limit)

–Up to 6.5 V input operating range

–VSYS regulator can withstand transient and DC inputs from 0 V up to +22 V

–Programmable charge voltage (3.5 V to 4.44 V)

–Programmable charge current (100 mA to 1000 mA)

–Programmable charge termination current (5.0 mA to 50 mA)

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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–Integrated 50 mΩ battery isolation MOSFET for operation with no/low battery

–Battery supplement mode

–Battery discharge overcurrent protection, up to 3.0 A

–USB_PHY low dropout linear regulator

–Programmable LED driver (status indicator)

–JEITA compliant battery temp sensing and charger control

–Key charging parameters can be configured and permanently stored in OTP

–I2C Control Interface permitting processor control and event detection

•LDO/switch supply

–RTC supply VSNVS 3.0 V, 2.0 mA

–Battery backed memory including coin cell charger

•DDR memory reference voltage, VREFDDR, 0.5 to 0.9 V, 10 mA

•OTP (One time programmable) memory for device configuration

–User programmable start-up sequence, timing, soft-start and power-down sequence

–Programmable regulator output voltages and charger parameters

•I2C interface

•User programmable Standby, Sleep/Low-power, and Off (REGS_DISABLE) modes

•Ambient temperature range −40 °C to 105 °C

1.2 Applications

•Smart mobile/wearable devices

•Low-power IoT applications

•Wireless game controllers

•Embedded monitoring systems

•Home automation

•POS

•E-Read

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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2 Application diagram

Low-power application

processor

DDR memory

GPS

MIPI

VREFDDR

SW2

PF1550

SW1

SW3

LDO1

LDO3

LDO2

VSNVS

Control signals

C communication

Li-cell

charger

Mini-USB

linear charger

USB_PHY

Mini-USB connector

Coin cell

I2C communication

Parallel control / GPIO

SNVS_IN

Bluetooth

FLASH

NAND - NOR

interfaces

Processor real-time

SOC/GPU

Processor ARM core

DDR memory Interface

External AMP

microphones

speakers

Audio codec

Sensors

aaa-023872

WiFi

SD/MMC/

NAND memory

Figure 1. Application diagram

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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2.1 Functional block diagram

Logic and Control

I2C/processor interface/

regulator control/

OTP

(flexible configuration)

Linear Li-ion battery charger

(22 V surge, power path,

100 mA to 1000 mA charging current)

aaa-023873

PF1550 functional block diagram

LDO1

(0.75 V to 3.3 V, 300 mA)

LDO2

(1.8 V to 3.3 V, 400 mA)

LDO3

(0.75 V to 3.3 V, 300 mA)

BUCK3

(1.8 V to 3.3 V, no DVS)

VSNVS (RTC supply)

(3.0 V, 2.0 mA)

DDR voltage reference

(VINREFDDR/2, 10 mA)

BUCK1

(0.6 V to 1.3875 V, 1.0 A, DVS;

1.1 V to 3.3 V, 1.0 A, no DVS)

BUCK2

(0.6 V to 1.3875 V, 1.0 A, DVS;

1.1 V to 3.3 V, 1.0 A, no DVS)

Figure 2. Functional block diagram

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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2.2 Internal block diagram

aaa-023874

SW2 DVS

and misc

reference

SW3

and misc

reference

SW1IN

SW1LX

EPAD

SW2FB

SW2IN

SW2LX

EPAD

SW3FB

SW3IN

SW3LX

EPAD

VINREFDDR

VREFDDR

LDO1IN

LDO1OUT

LDO2IN

LDO2OUT

LDO3IN

LDO3OUT

THM

VBUSIN

USBPHY

INT2P7

VBATT

LICELL

VSNVS

VSYS

VCORE

VDIG

EA and

driver

SW1 DVS

and misc

reference

EA and

driver

EA and

driver

Watchdog

timer

VREFDDR

divide input by 2

LDO1 LDO2 LDO3

Thermistor

monitor

INT2P7

LDO

USBPHY

LDO

16 MHz clock

32 kHz clock

OTP memory

PF1550 digital core

and state machine

PF1550 analog core

(reference and bias current)

VCORE

LDO

VDIG

LDO

coin cell

charger

VSNVS

Digital signal(s)

Analog reference(s)

16 MHz clock / derivative

32 kHz clock / derivative

SW1FB

Figure 3. Internal block diagram

3 Orderable parts

The PF1550 is available only with preprogrammed configurations. These preprogrammed

devices are identified using the program codes from Table 1, which also list the

associated NXP reference designs where applicable. Details of the OTP programming for

each device can be found in Table 83.

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 1. Orderable part variations

Part number[1] Temperature (TA) Package Programming options

MC32PF1550A0EP 0 - Not programmed

MC32PF1550A1EP 1 (Default)

MC32PF1550A2EP 2 (i.MX 7ULP with LPDDR3) [2]

MC32PF1550A3EP 3 (i.MX 6UL with DDR3L)

MC32PF1550A4EP 4 (i.MX 7ULP with LPDDR3)

MC32PF1550A5EP 5 (i.MX 6UL with DDR3)

MC32PF1550A6EP 6 (i.MX 6ULL with DDR3L)

MC32PF1550A7EP 7 (i.MX 6UL with LPDDR2)

MC32PF1550A8EP

−40 °C to 85 °C (for use

in consumer applications)

8 (i.MX 6UL with DDR3L, Edge

Sensitive)

MC34PF1550A0EP 0 - Not programmed

MC34PF1550A1EP 1 (Default)

MC34PF1550A2EP 2 (i.MX 7ULP with LPDDR3) [2]

MC34PF1550A3EP 3 (i.MX 6UL with DDR3L)

MC34PF1550A4EP 4 (i.MX 7ULP with LPDDR3)

MC34PF1550A5EP 5 (i.MX 6UL with DDR3)

MC34PF1550A6EP 6 (i.MX 6ULL with DDR3L)

MC34PF1550A7EP 7 (i.MX 6UL with LPDDR2)

MC34PF1550A8EP

−40 °C to 105 °C (for use

in industrial applications)

98ASA00913D, 40-pin QFN 5.0

mm x 5.0 mm with exposed pad

8 (i.MX 6UL with DDR3L, Edge

Sensitive)

[1] For tape and reel, add an R2 suffix to the part number.

[2] For internal validation only

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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4 Pinning information

4.1 Pinning

EPAD

(41)

SW1IN

SW1LX

SW2FB

SW2IN

SW2LX

SW3FB

SW3IN

SW3LX

VINREFDDR

VREFDDR

VLDO1IN

VSNVS

VCORE

VDIG

BUSI

SW1FB

40 37 36 35 34 33 31323839

11 14 15 16 17 18 20191312

VLDO1

VDDOTP

PWRON

INTB

RESETBMCU

SCL

WDI

STANDBY

ONKEY

VDDIO

SDA

VLDO3

VLDO2

VLDO2IN

aaa-023875Transparent top view

PF1550

Figure 4. Pinout diagram

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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4.2 Pin definitions

Table 2. Pin description

Pin number Pin name Block Description

1 WDI Watchdog input from processor

2 SDA SDA when used in I2C mode

3 SCL SCL when used in I2C mode

4 VDDIO

I/Os

I/O supply voltage

Connect to voltage rail between 1.7 V and 3.3 V

5 VDDOTP VDDOTP Connect to ground in application

6 PWRON PWRON input

7 STANDBY STANDBY input

8 ONKEY ONKEY push button input

9 INTB INTB open-drain output

10 RESETBMCU

I/Os

RESETBMCU open-drain output

11 VLDO3IN LDO3 input supply

12 VLDO3

LDO3

LDO3 output

13 SW3LX Buck 3 switching node

14 SW3IN Buck 3 input supply

15 SW3FB

Buck 3

Buck 3 output voltage feedback

16 SW2FB Buck 2 output voltage feedback

17 SW2IN Buck 2 input supply

18 SW2LX

Buck 2

Buck 2 switching node

19 VLDO2 LDO2 output

20 VLDO2IN

LDO2

LDO2 input supply

21 VREFDDR VREFDDR output

22 VINREFDDR

VREFDDR

VREFDDR input supply

23 VDIG VDIG regulator output (used within PF1550)

24 VCORE

IC core

VCORE regulator output (used within PF1550)

25 SW1LX Buck 1 switching node

26 SW1IN Buck 1 input supply

27 SW1FB

Buck 1

Buck 1 feedback input

28 VLDO1IN LDO1 input supply

29 VLDO1

LDO1

LDO1 output

30 VSNVS VSNVS regulator output

31 LICELL

VSNVS

Coin cell input

32 THM Thermistor connection

Connect thermistor to ground from this pin

VBATT

CHARGER Battery input

VSYS IC Core

Main input voltage to PMIC and output of charger

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Pin number Pin name Block Description

37 VBUSIN Charger input

38 INT2P7 INT2P7 regulator output (used within PF1550 and as thermistor bias)

39 USBPHY USBPHY regulator output

40 CHGB

CHARGER

Charger LED input connection

Connect LED from VSYS to this pin

41 EPAD EPAD Exposed pad

Connect to ground

5 General product characteristics

5.1 Thermal characteristics

Table 3. Thermal ratings

Symbol Description (Rating) Min Max Unit

THERMAL RATINGS

TAAmbient operating temperature range (industrial)

Ambient operating temperature range (consumer)

−40

105

°C

TJOperating junction temperature range [1] −40 125 °C

TST Storage temperature range −65 150 °C

TPPRT Peak package reflow temperature [2] [3] — — °C

QFN40 THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS

RΘJA Junction to ambient thermal resistance, natural convection

Four layer board (2s2p)

Six layer board (2s4p)

Eight layer board (2s6p)

[4] [5] [6] —

20.6

17.8

°C/W

RΘJMA Junction to ambient (@200ft/min)

Four layer board (2s2p)

[4] [6] —

21.4

°C/W

RΘJB Junction to board [7] — 8.8 °C/W

RΘJCBOTTOM Junction to case bottom [8] — 1.4 °C/W

ΨJT Junction to package top – Natural convection [9] — 0.6 °C/W

[1] Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Thermal Protection

Thresholds for thermal protection features.

[2] Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a

malfunction or permanent damage to the device.

[3] NXP's package reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For peak package reflow temperature and moisture

sensitivity levels (MSL), go to http://www.nxp.com, search by part number [ remove prefixes/suffixes and enter the core ID to view all orderable parts (for

MC33xxxD enter 33xxx), and review parametrics.

[4] Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

[5] The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5.

[6] Per JEDEC JESD51-6 with the board horizontal.

[7] Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board

near the package.

[8] Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

[9] Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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5.2 Absolute maximum ratings

Table 4. Maximum ratings

Symbol Description (Rating) Min Max Unit

I/Os

VDDIO I/O supply voltage. Connect to voltage rail between 1.7 V and 3.3 V. −0.3 3.6 V

SCL SCL when used in I2C mode. SCLK when used in SPI mode. −0.3 3.6 V

SDA SDA when used in I2C mode. MISO when used in SPI mode. −0.3 3.6 V

RESETBMCU RESETBMCU open drain output −0.3 3.6 V

PWRON PWRON input −0.3 3.6 V

STANDBY STANDBY input −0.3 3.6 V

ONKEY ONKEY push button input −0.3 4.8 V

INTB INTB open-drain output −0.3 3.6 V

WDI Watchdog input from processor −0.3 3.6 V

VDDOTP

VDDOTP Connect to ground in the application −0.3 10 V

BUCK 1

SW1IN Buck 1 input supply −0.3 4.8 V

SW1LX Buck 1 switching node −0.3 4.8 V

SW1FB Buck 1 feedback input −0.3 3.6 V

BUCK 2

SW2IN Buck 2 input supply −0.3 4.8 V

SW2LX Buck 2 switching node −0.3 4.8 V

SW2FB Buck 2 output voltage feedback −0.3 3.6 V

BUCK 3

SW3IN Buck 3 input supply −0.3 4.8 V

SW3LX Buck 3 switching node −0.3 4.8 V

SW3FB Buck 3 output voltage feedback −0.3 3.6 V

LDO1

VLDO1IN LDO1 input supply −0.3 4.8 V

VLDO1 LDO1 output −0.3 3.6 V

LDO2

VLDO2IN LDO2 input supply −0.3 4.8 V

VLDO2 LDO2 output −0.3 3.6 V

LDO3

VLDO3IN LDO3 input supply −0.3 4.8 V

VLDO3 LDO3 output −0.3 3.6 V

VSNVS

VSNVS VSNVS regulator output −0.3 3.6 V

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Symbol Description (Rating) Min Max Unit

LICELL Coin cell input −0.3 3.6 V

CHARGER

VBATT Battery input −0.3 4.8 V

INT2P7 INT2P7 regulator output (used within PF1550 and as thermistor bias) −0.3 3.6 V

THM Thermistor connection. Connect thermistor to ground from this pin. −0.3 3.6 V

VBUSIN Charger input −0.3 24 V

USBPHY USBPHY regulator output −0.3 5.5 V

CHGB Charger LED input connection. Connect LED from VSYS to this pin. −0.3 4.8 V

INPUT/OUTPUT SUPPLY

VINREFDDR VREFDDR input supply −0.3 3.6 V

VREFDDR VREFDDR output −0.3 3.6 V

IC CORE

VSYS Main input voltage to PMIC and output of charger −0.3 4.8 V

VDIG VCOREDIG regulator output (used within PF1550) −0.3 1.65

VCORE VCORE regulator output (used within PF1550) −0.3 1.65 V

ELECTRICAL RATINGS

VESD

ESD ratings

Human body model

Charge device model (corner pins)

Charge device model (all other pins)

[1]

—

±2000

±750

±500

[1] Testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM), Robotic

(CZAP = 4.0 pF).

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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5.3 Electrical characteristics

5.3.1 Electrical characteristics – Battery charger

All parameters are specified at TA = −40 to 105 °C, VBUSIN = 5.0 V, VSYS = 3.7 V,

typical external component values, unless otherwise noted. Typical values are

characterized at VBUSIN = 5.0 V, VSYS = 3.7 V and 25 °C, unless otherwise noted.

Table 5. Global conditions

Symbol Parameter Measurement condition Min Typ Max Unit

CHARGER INPUTS

VBUS VBUSIN voltage range Operating voltage VUVLO — VOVLO V

VBUS_WITHSTAND VBUSIN maximum withstand

voltage rating

— — 22 V

VBUS_OVLO VBUSIN overvoltage threshold Rising 6.0 6.5 7.0 V

VOVLO_HYS VBUSIN overvoltage threshold

hysteresis

Falling 50 150 250 mV

tD-OVLO VBUSIN overvoltage delay 5.0 10 15 µs

VUVLO VBUSIN to GND minimum turn

on threshold accuracy

VBUS rising 3.8 4.0 4.2 V

VUVLO-HYS VBUSIN UVLO hysteresis 400 500 600 mV

VIN2SYS_50 VBUSIN to VSYS minimum turn

on threshold accuracy

VBUS_LIN rising, 50 mV setting 20 50 80 mV

VIN2SYS_175 VBUSIN to VSYS minimum turn

on threshold accuracy

VBUS_LIN rising, 175 mV

setting

100 175 250 mV

VBUS_LIN_DPM_REG VBUSIN adaptive voltage

regulation threshold

4.4 V setting (default) 4.3 4.4 4.5 V

VDPM_REG VBUSIN adaptive voltage

regulation threshold accuracy

Programmable at 3.9 V to 4.6 V −100 — 100 mV

Table 6. Input currents

Symbol Parameter Measurement condition Min Typ Max Unit

VBUSIN INPUT CURRENT LIMIT

ILIM10 Charger input current limit (10

mA settings)

10 mA 6.0 8.5 11 mA

ILIM15 Charger input current limit (15

mA settings)

15 mA 10.5 12.75 16 mA

ILIM20 Charger input current limit (20

mA settings)

20 mA 14 17 21 mA

ILIM25 Charger input current limit (25

mA settings)

25 mA 17.5 21.25 26 mA

ILIM30 Charger Input Current Limit

(30mA setting)

30 mA 21 25.5 30 mA

ILIM35 Charger input current limit (35

mA settings)

35 mA 24.5 29.75 35 mA

ILIM40 Charger input current limit

(40mA settings)

40 mA 28 34 40 mA

ILIM45 Charger input current limit (45

mA settings)

45 mA 31.5 38.25 45 mA

ILIM50 Charger input current limit (50

mA settings)

50 mA 35 42.5 50 mA

ILIM100 Charger input current limit (100

mA settings)

100 mA 85 95 105 mA

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Symbol Parameter Measurement condition Min Typ Max Unit

ILIM150 Charger input current limit (150

mA settings)

150 mA 125 137.5 160 mA

ILIM200 Charger input current limit (200

mA settings)

200 mA 170 190 210 mA

ILIM300 Charger input current limit (300

mA setting)

300 mA 260 285 320 mA

ILIM400 Charger input current limit (400

mA settings)

400 mA 345 380 425 mA

ILIM500 Charger input current limit (500

mA settings)

500 mA 430 475 530 mA

ILIM600 Charger input current limit (600

mA settings)

600 mA 520 570 640 mA

ILIM700 Charger input current limit (700

mA settings)

700 mA 610 665 750 mA

ILIM800 Charger input current limit (800

mA settings)

800 mA 690 760 850 mA

ILIM900 Charger input current limit (900

mA settings)

900 mA 780 855 950 mA

ILIM1000 Charger input current limit (1000

mA settings)

1000 mA 855 950 1100 mA

ILIM1500 Charger input current limit (1500

mA settings)

1500 mA 1260 1400 1700 mA

RINSD Input self discharge resistance 18 30 42 kΩ

IBATTLEAK Leakage current Leakage current from VBATT

to VBUSIN. VBATT = 4.2 V,

BATFET closed, VBUSIN = 0 V.

Current measured into VBATT

pin at 25 °C

0 — 5.0 µA

IQ_CHARGER Charger quiescent current

(BATFET enabled, normal

mode)

25 °C only; charger in CC state;

ICC = 100 mA

0 2.5 5.0 mA

IQ_CHARGER_LQM Charger quiescent current (low

power mode, charging enabled,

10 to 50 mA input current limit

setting, VBATT > 2.8 V and

LED driver OFF)

25 °C only; charger in CC state 0 1.5 3.0 mA

TSSVBUS_LIN Soft start time (VBUSIN = 5.0

V, time between input LDO

enabled and VSYS going to 90

% of regulation

No input current limitation event,

measured in Normal mode

— — 30 ms

Table 7. Internal 2.7 V Regulator (INT2P7)

Symbol Parameter Measurement condition Min Typ Max Unit

VGDRV Output voltage 2.6 2.7 2.8 V

IGDRV Output current 5.0 — — mA

VDO(GDRV) Dropout voltage 0 — 800 mV

Table 8. Switch impedances and leakage currents

Symbol Parameter Measurement Condition Min Typ Max Unit

RVBUS_LIN2SYS VBUSIN to VSYS resistance 100 250 550 mΩ

RBATFET_QFN VBATT to VSYS resistance 50 75 120 mΩ

ISYS VSYS leakage current VSYS = 0 V, VBATT = 4.2 V,

SHIP mode

0 0.2 10 µA

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Symbol Parameter Measurement Condition Min Typ Max Unit

IBATT_OC VBATT reverse ILIM quiescent

current when VBUSIN = 0 V

VBUSIN = 0 V, VSYS = VBATT

= 4.2 V, BATFET enabled,

battery overcurrent enabled

— — 100 µA

Table 9. Linear transients

Symbol Parameter Measurement condition Min Typ Max Unit

VPK-PK Load transient peak-to-peak VBUSIN = 5.0 V, VBATT = 3.6

V, ICHG = 500 mA, VSYS load

step 1.0 A/µs

10 400 850 mV

VOV_SHT Load transient overshoot VBUSIN = 5.0 V, VBATT = 3.6

V, ICHG = 500 mA, VSYS load

step 1.0 A/µs

0 200 500 mV

VUND_SHT Load transient undershoot VBUSIN = 5.0 V, VBATT = 3.6

V, ICHG = 500 mA, VSYS load

step 1.0 A/µs

0 200 500 mV

Table 10. Charger characteristics

Symbol Parameter Measurement condition Min Typ Max Unit

VCHGCV_RANGE CHGCV output voltage range See register map for constant

voltage programmable range

3.5 — 4.44 V

CVACC CHGCV output accuracy in

normal charging

— — ±1 %

VSYSMIN0 VSYS output voltage (3.5 V

option)

VSYSMIN = 0x00 (3.5 V option) 3.395 3.5 3.605 V

VSYSMIN1 VSYS output voltage (3.7 V

option)

VSYSMIN = 0x01 (3.7 V option) 3.589 3.7 3.811 V

VSYSMIN2 VSYS output voltage (4.3 V

option)

VSYSMIN = 0x02 (4.3 V option) 4.171 4.3 4.429 V

VSYSMINLOOP0 VSYSMIN loop threshold (3.5 V

option)

3.0 3.2 3.39 V

VSYSMINLOOP1 VSYSMIN loop threshold (3.7 V

option)

3.2 3.4 3.585 V

VSYSMINLOOP2 VSYSMIN loop threshold (4.3 V

option)

3.83 4.0 4.17 V

IFC Output current range Constant current programmable

range CHG_CC[4:0]

100 — 1000 mA

IFCACC1 Output current accuracy −10 — 10 %

IEOC Charger IEOC range 5.0 — 50 mA

tDB(IEOC) Debounce time for charge

termination

20 32 44 ms

IEOC_ACC_5mA Charger IEOC accuracy (5.0 mA

settings)

IEOC = 5 mA 1.0 5.0 12 mA

IEOC_ACC_10mA Charger IEOC accuracy (10 mA

settings)

IEOC = 10 mA 4.0 10 16 mA

IEOC_ACC_50mA Charger IEOC accuracy (50 mA

setting)

IEOC = 50 mA 40 50 60 mA

VPRECHG Precharge threshold VBATT rising 2.7 2.8 2.9 V

VPRECHG_HYS Precharge threshold hysteresis 50 100 150 mV

IPRECHG Precharge current 30 45 60 mA

IPRECHG.LPM Charging current in LPM and 2.8

V < VBATT < 3.1 V

0.75 1.0 1.25 mA

VRESTART Charger restart threshold (100

mV settings)

VBATT below CHGCV[5:0] 50 100 150 mV

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Symbol Parameter Measurement condition Min Typ Max Unit

VRESTART Charger restart threshold (150

mV setting)

VBATT below CHGCV[5:0] 100 150 200 mV

VRESTART Charger restart threshold (200

mV settings)

VBATT below CHGCV[5:0] 150 200 250 mV

tDB(VRCH) Debounce time on VRESTART 20 32 44 ms

VBATOV BATTOVP range CHGCV x

1.025

CHGCV x 1.05 CHGCV x

1.075

VBATOV_HYS BATTOVP hysteresis VBATT falling from BATTOVP CHGCV x

0.015

CHGCV x

0.025

CHGCV x

0.035

Table 11. Power-path management

Symbol Parameter Measurement condition Min Typ Max Unit

VSPLM Supplement mode voltage

threshold

Entering supplement mode

when VSYS < VBATT

10 40 75 mV

Table 12. Watchdog timer

Symbol Parameter Measurement condition Min Typ Max Unit

tWD Watchdog timer period — 80 — s

tWDACC Watchdog timer accuracy −20 0 20 %

Table 13. Charger timer

Symbol Parameter Measurement condition Min Typ Max Unit

tPRECHG Precharge time (fixed 45 mA) Applies to low battery

prequalification mode, 500 mA

settings

— 30 — min

tFC Fast charge constant current

and constant voltage time

Adjustable from 2 to 14 in 2 hour

steps

— 4.0 — hrs

tEOC End-of-charge time Adjustable from 0 to 70 in 10 min

steps

— 30 — min

tacc Timer accuracy All timers associated with the

charger block

−20 — 20 %

tSCIDG Charger state change interrupt

delay

0 1.0 2.0 ms

tINLIM VBUS_VOK delay from VDIG

ready following VBUSIN

insertion (see charger startup

diagram)

0 100 200 µs

Table 14. Battery overcurrent protection

Symbol Parameter Measurement condition Min Typ Max Unit

tBOVCR Battery overcurrent debounce

time

Response time to BATFET open

(OTP option)

12.8 16 19.2 ms

tBOVCRI Battery overcurrent interrupt

debounce time

Response time to generate

interrupt

2.4 3.0 3.6 ms

IBOVCR Battery overcurrent threshold

range

Programmable from 2.0 A to 4.0

A in three steps

2.0 — 4.0 A

IBOVCRACC_2A Battery overcurrent threshold

accuracy (2.2 A setting)

1.0 2.2 3.2 A

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Symbol Parameter Measurement condition Min Typ Max Unit

IBOVCRACC_3A Battery overcurrent threshold

accuracy (2.8 A setting)

1.6 2.8 4 A

IBOVCRACC_4A Battery overcurrent threshold

accuracy (3.2 A setting)

2.0 3.2 4.6 A

RSYSDISCH SYS self-discharge resistor in

SHIP mode

480 600 720 Ω

Table 15. Thermal regulation

Symbol Parameter Measurement condition Min Typ Max Unit

TREG Thermal regulation threshold (80

°C setting)

Temperature at which charge

current begins to decrease

— 80 — °C

TREG Thermal regulation threshold (95

°C Setting)

Temperature at which charge

current begins to decrease

— 95 — °C

TREG Thermal regulation threshold

(110 °C setting)

Temperature at which charge

current begins to decrease

— 110 — °C

Table 16. Battery thermistor monitor

Symbol Parameter Measurement Condition Min Typ Max Unit

VNTECREF NTECREF voltage 2.6 2.7 2.8 V

VTN10C Thermistor threshold (−10 °C

settings)

−10 °C 0.79*VNTECREF 0.82*VNTECREF 0.85*VNTECREF V

VT0C Thermistor threshold (0 °C

settings)

0 °C 0.71*VNTECREF 0.74*VNTECREF 0.77*VNTECREF V

VT10C Thermistor threshold (10 °C

settings)

10 °C 0.62*VNTECREF 0.65*VNTECREF 0.68*VNTECREF V

VT45C Thermistor threshold (45 °C

settings)

45 °C 0.31*VNTECREF 0.33*VNTECREF 0.35*VNTECREF V

VT55C Thermistor threshold (55 °C

settings)

55 °C 0.25*VNTECREF 0.26*VNTECREF 0.27*VNTECREF V

VT60C Thermistor threshold (60 °C

settings)

60 °C 0.22*VNTECREF 0.23*VNTECREF 0.24*VNTECREF V

VT_HYS Battery temperature hysteresis All settings 0.5 2.5 5.0 °C

Table 17. USBPHY LDO

Symbol Parameter Measurement condition Min Typ Max Unit

VUSB_PHY Output voltage IOUT = 10 mA; 3.3 V and 4.9 V

settings. VBUSIN = 5.5 V

−5.0 — 5.0 %

IUSB_PHY Maximum output current 60 — — mA

USBRDIS Internal discharge resistance 500 1000 1500 Ω

USBCAPSTA Output capacitor for stable

operation

0 µA < IOUT < 60 mA, MAX ESR

= 10 mΩ

0.7 1.0 2.2 µF

IQUSB Quiescent supply current — 35 — µA

USBPHYLDREG DC load regulation VBUSIN = 5.5 V, 30 µA < IOUT <

60 mA

0 5.0 13 mV

USBPHYDO Dropout voltage VBUSIN = 5.0 V, IOUT = 60 mA — 200 350 mV

USBPHYILIM Output current limit 65 150 200 mA

PSRRUSB_PHY PSRR VBUSIN = 5.5 V, COUT = 1.0 µF 55 60 75 dB

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

17 / 149

Table 18. LED characteristics

Symbol Parameter Measurement condition Min Typ Max Unit

VLED LED input voltage operating

range (anode to ground)

3.5 — VSYS V

VCHGB_IN CHGB input voltage operating

range, LED driver enabled

1.0 — 3.0 V

ILED LED current accuracy 4.0 6.0 8 mA

TON LED duty cycle range Programmable from 10 % to 100

% duty cycle in 10 % steps

10 — 100 %

TLEDRUP LED ramp up Settings depend on duty cycle 50 — 500 ms

TLEDRDN LED ramp down Settings depend on duty cycle 50 — 500 ms

FLED LED frequency Programmable from 0.5 Hz to

256 Hz

0.5 — 256 Hz

5.3.2 Electrical characteristics – SW1 and SW2

All parameters are specified at TA = −40 to 105 °C, VSYS = VSWxIN = 2.5 to 4.5 V, VSWx

= 1.2 V, ISWx = 200 mA, typical external component values, fSWx = 2.0 MHz, unless

otherwise noted. Typical values are characterized at VSYS = VSWxIN = 3.6 V, VSWx =

1.1 V, ISWx = 100 mA, and 25 °C, unless otherwise noted.

Table 19. SW1 and SW2 electrical characteristics

Symbol Parameter Min Typ Max Unit

VSWxIN Operating input voltage 2.5 — 4.5 V

ISWx Rated output current 1000 — — mA

VSWx Output voltage accuracy

DVS enabled mode (OTP_SWx_DVS_SEL = 0)

Normal power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 1.0 A

0.6 V ≤ VSWx ≤ 1.0 V

−15 — 15 mV

VSWx Output voltage accuracy

DVS enabled mode (OTP_SWx_DVS_SEL = 0)

Normal power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 1.0 A

1.0 V < VSWx ≤ 1.3875 V

−2.0 — 2.0 %

VSWx Output voltage accuracy

DVS enabled mode (OTP_SWx_DVS_SEL = 0)

Low-power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 0.1 A

0.6 V ≤ VSWx ≤ 1.0 V

−30 — 30 mV

VSWx Output voltage accuracy

DVS enabled mode (OTP_SWx_DVS_SEL = 0)

Low-power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 0.1 A

1.0 V < VSWx ≤ 1.3875 V

−3.0 — 3.0 %

VSWx Output voltage accuracy

DVS disabled mode (OTP_SWx_DVS_SEL = 1)

Normal power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 1.0 A

1.1 V ≤ VSWx ≤ 1.5 V

−45 — 45 mV

VSWx Output voltage accuracy

DVS disabled mode (OTP_SWx_DVS_SEL = 1)

Normal power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 1.0 A

1.8 V ≤ VSWx ≤ 3.3 V

−3.0 — 3.0 %

VSWx Output voltage accuracy

DVS disabled mode (OTP_SWx_DVS_SEL = 1)

Low-power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 0.1 A

1.1 V < VSWx ≤ 1.5 V

−55 — 55 mV

VSWx Output voltage accuracy

DVS disabled mode (OTP_SWx_DVS_SEL = 1)

Low-power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 0.1 A

1.8 V ≤ VSWx ≤ 3.3 V

−4.0 — 4.0 %

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Symbol Parameter Min Typ Max Unit

ΔVSWx Output ripple — 5.0 — mV

SWxEFF Efficiency

VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ

LP/ ULP mode, 1.2 V, 1.0 mA

— 88 — %

SWxEFF Efficiency

VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ

Normal power mode, 1.2 V, 50 mA

— 90 — %

SWxEFF Efficiency

VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ

Normal power mode, 1.2 V, 150 mA

— 92 — %

SWxEFF Efficiency

VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ

Normal power mode, 1.2 V, 400 mA

— 89 — %

SWxEFF Efficiency

VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ

Normal power mode, 1.2 V, 1000 mA

— 83 — %

ISWxLIMH Current limiter peak (high-side MOSFET) current detection

SWxILIM[1:0] = 00

SWxILIM[1:0] = 01

SWxILIM[1:0] = 10

SWxILIM[1:0] = 11

0.7

0.8

1.0

1.4

1.0

1.2

1.5

2.0

1.3

1.6

2.0

2.6

ISWxLIML Current limiter low-side MOSFET current detection (sinking current) 0.7 1.0 1.3 A

ISWxQ Quiescent current (at 25 °C)

Low-power mode with DVS disabled (OTP_SWx_DVS_SEL = 1)

—

1.0

—

µA

ISWxQ Quiescent current (at 25 °C)

Low-power mode with DVS enabled (OTP_SWx_DVS_SEL = 0)

—

6.0

—

µA

ISWxQ Quiescent current (at 25 °C)

Normal power mode with DVS disabled (OTP_SWx_DVS_SEL = 1)

—

5.5

—

µA

ISWxQ Quiescent current (at 25 °C)

Normal power mode with DVS enabled (OTP_SWx_DVS_SEL = 0)

—

µA

VSWxOSH Startup overshoot (Normal mode)

ISWx = 0 mA

DVS speed = 12.5 mV/4 µs, VSYS = VSWxIN = 3.6 V, VSWx = 1.35 V

— — 25 mV

tONSWx Turn on time

10 % to 90 % of end value

DVS speed = 12.5 mV/4 µs, VSYS = VSWxIN = 3.6 V, VSWx = 1.35 V

— — 500 µs

VSWxLOTR Transient load regulation (Normal power mode)

Transient load = 50 mA to 250 mA, di/dt = 200 mA/μs

Overshoot

Undershoot

—

RONSWxP SWx P-MOSFET RDS(on) at VSWxIN = 3.6 V — 200 — mΩ

RONSWxN SWx N-MOSFET RDS(on) at VSWxIN = 3.6 V — 150 — mΩ

RSWxDIS Turn off discharge resistance — 500 — Ω

5.3.3 Electrical characteristics – SW3

All parameters are specified at TA = −40 to 105 °C, VSYS = VSW3IN = 2.5 to 4.5 V, VSW3

= 1.8 V, ISW3 = 200 mA, typical external component values, fSW3 = 2.0 MHz, unless

otherwise noted. Typical values are characterized at VSYS = VSW3IN = 3.6 V, VSW3 =

1.8 V, ISW3 = 200 mA, and 25 °C, unless otherwise noted.

Table 20. SW3 electrical characteristics

Symbol Parameter Min Typ Max Unit

VSW3IN Operating input voltage 2.5 — 4.5 V

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Symbol Parameter Min Typ Max Unit

VSW3 Output voltage accuracy (all voltage settings)

Normal power mode, 2.5 V < VSW3IN < 4.5 V, 0 < ISW3 < 1.0 A

−2.0

—

2.0

VSW3 Output voltage accuracy (all voltage settings)

Low-power mode, 2.5 V < VSW3IN < 4.5 V, 0 < ISW3 < 0.1 A

−3.0

—

3.0

ΔVSW3 Output ripple — 5.0 — mV

SW3EFF

Efficiency

VSW3IN = 3.6 V, LSW3 = 1.0 µH, DCR = 50 mΩ

LP/ ULP Mode, 1.8 V, 1.0 mA

—

SW3EFF

Efficiency

VSW3IN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ

Normal power mode, 1.8 V, 50 mA

—

SW3EFF

Efficiency

VSW3IN = 3.6 V, LSWx = 1.0 mH, DCR = 50 mΩ

Normal power mode, 1.8 V, 100 mA

—

SW3EFF

Efficiency

VSW3IN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ

Normal power mode, 1.8 V, 400 mA

—

SW3EFF

Efficiency

VSW3IN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ

Normal power mode, 1.8 V, 1000 mA

—

ISW3LIMH Current limiter peak (high-side MOSFET) current detection

SW3ILIM[1:0] = 00

SW3ILIM[1:0] = 01

SW3ILIM[1:0] = 10

SW3ILIM[1:0] = 11

0.7

0.8

1.0

1.4

1.0

1.2

1.5

2.0

1.3

1.6

2.0

2.6

ISW3LIML Current limiter low-side MOSFET current detection (sinking current) 0.7 1.0 1.3 A

ISW3Q Quiescent current (at 25 °C)

Low-power mode

—

1.0

—

µA

VSW3OSH Start-up overshoot (Normal mode)

ISW3 = 0 mA

VSYS = VSW3IN = 3.6 V, VSW3 = 1.8 V

— — 50 mV

tONSW3 Turn on time

10 % to 90 % of end value

VSYS = VSW3IN = 3.6 V, VSW3 = 1.8 V

— — 500 µs

VSW3LOTR Transient load regulation (Normal power mode)

Transient load = 50 mA to 250 mA, di/dt = 200 mA/μs

Overshoot

Undershoot

—

RONSW3N SW3 N-MOSFET RDS(on) at VSW3IN = 3.6 V — 150 — mΩ

RONSW3P SW3 P-MOSFET RDS(on) at VSW3IN = 3.6 V — 200 — mΩ

RSW3DIS Turn off discharge resistance — 300 — Ω

5.3.4 Electrical characteristics – LDO1

All parameters are specified at TA = −40 to 105 °C, VSYS = 2.5 to 4.5 V, VLDOIN1 =

3.6 V, VLDO1[4:0] = 11111, ILDO1 = 10 mA, typical external component values, unless

otherwise noted. Typical values are characterized at VSYS = 3.6 V, VLDOIN1 = 3.6 V,

VLDO1[4:0] = 11111, ILDO1 = 10 mA, and 25 °C, unless otherwise noted.

Table 21. LDO1 electrical characteristics

Symbol Parameter Min Typ Max Unit

VLDO1IN Operating input voltage

VLDO1 + 250 mV ≤ VSYS ≤ 4.5 V

1.0

—

4.5

VLDO1NOM Nominal output voltage — See Table 41 — V

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Symbol Parameter Min Typ Max Unit

ILDO1MAX Rated output load current, Normal mode 300 — — mA

ILDO1MAXLPM Rated output load current, Low-power mode 10 — — mA

VLDO1TOL Output voltage tolerance, Normal mode

VLDO1INMIN < VLDO1IN < 4.5 V, 0 mA < ILDO1 ≤ 300 mA

0.8 V ≤ VLDO1 < 1.8 V

1.8 V ≤ VLDO1 ≤ 3.3 V

VLDO1INMIN < VLDO1IN < 4.5 V, 0 mA < ILDO1 < 10 mA (Low-power

mode)

−2.5

−4.0

—

2.5

4.0

ILDO1LIM Current limit

ILDO1 when VLDO1 is forced to VLDO1NOM/2

320 — 1000 mA

ILDO1OCP LDO1FAULTI threshold (also used to disable LDO1 when

REGSCPEN = 1)

320 — 1000 mA

ILDO1Q Quiescent current (at 25 °C)

No load, change in IVSYS and IVLDOIN1

When LDO1 enabled in Normal mode

When LDO1 enabled in Low-power mode

—

2.5

—

µA

RDSON_QFN_LDO1 Dropout on resistance — — 350 mΩ

PSRRLDO1 PSRR

ILDO1 = 150 mA, 20 Hz to 20 kHz

VLDO1 = 3.30 V, VLDO1IN = 3.8 V, VSYS = 4.2 V

—

TRVLDO1 Turn on time

10 % to 90 % of end value

VLDO1INMIN < VLDO1IN ≤ 4.5 V, ILDO1 = 0.0 mA

—

200

500

µs

RLDO1DIS Turn off discharge resistance — 250 — Ω

LDO1OUTOSHT Start-up overshoot (% of final value)

VLDO1INMIN < VLDO1IN ≤ 4.5 V, ILDO1 = 0.0 mA

—

1.0

2.0

VLDO1LOTR Transient load response

VLDO1INMIN < VLDO1IN ≤ 4.5 V, ILDO1 = 10 mA to 200 mA in 10 μs

Overshoot

Undershoot

—

5.3.5 Electrical characteristics – LDO2

All parameters are specified at TA = −40 to 105 °C, VSYS = 3.6 V, VLDOIN2 = 3.6 V,

VLDO2[3:0] = 1111, ILDO2 = 10 mA, typical external component values, unless otherwise

noted. Typical values are characterized at VSYS = 3.6 V, VLDOIN2 = 3.6 V, VLDO2[3:0] =

1111, ILDO2 = 10 mA, and 25 °C, unless otherwise noted.

Table 22. LDO2 electrical characteristics

Symbol Parameter Min Typ Max Unit

VLDO2IN Operating input voltage

1.8 V ≤ VLDO2NOM ≤ 2.5 V

2.6 V ≤ VLDO2NOM ≤ 3.3 V

2.8

VLDO2NOM + 0.250

–

4.5

VLDO2NOM Nominal output voltage — See Table 43 — V

ILDO2MAX Rated output load current, Normal mode 400 — — mA

ILDO2MAXLPM Rated output load current, Low-power mode 10 — — mA

VLDO2TOL Output voltage tolerance

VLDO2INMIN < VLDO2IN < 4.5 V

10.0 mA ≤ ILDO2 < 400 mA

0.0 mA < ILDO2 < 10 mA (Low-power mode)

−2.0

−4.0

—

2.0

4.0

ILDO2LIM Current limit

ILDO2 when VLDO2 is forced to VLDO2NOM/2

450 750 1050 mA

ILDO2OCP LDO2FAULTI threshold (also used to disable LDO2

when REGSCPEN = 1)

450 — 1050 mA

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

21 / 149

Symbol Parameter Min Typ Max Unit

ILDO2Q Quiescent Current (25 °C)

No load, change in IVSYS and IVLDO2IN

When VLDO2 enabled in Normal mode

When VLDO2 enabled in Low-power mode

—

1.5

—

µA

RDSON_QFN_LDO2 Dropout on resistance — — 300 mΩ

PSRRVLDO2 PSRR

ILDO2 = 200 mA, 20 Hz to 20 kHz

VLDO2 = 3.30 V, VLDO2IN = 3.9 V, VSYS = 4.2 V

—

tONLDO2 Turn on time

10 % to 90 % of end value

VLDO2INMIN < VLDO2IN ≤ 4.5 V, ILDO2 = 0.0 mA

— 200 500 µs

RLDO2DIS Turn off discharge resistance — 250 — Ω

LDO2OUTOSHT Start-up overshoot (% of final value)

VLDO2INMIN < VLDO2IN ≤ 4.5 V, ILDO2 = 0.0 mA

— 1.0 2.0 %

VLDO2LOTR Transient load response

VLDO2INMIN < VLDO2IN ≤ 4.5 V, ILDO2 = 10 mA to 100 mA in

10 μs

Overshoot

Undershoot

—

5.3.6 Electrical characteristics – LDO3

All parameters are specified at TA = −40 to 105 °C, VSYS = 2.5 to 4.5 V, VLDOIN3 =

3.6 V, VLDO3[4:0] = 11111, ILDO3 = 10 mA, typical external component values, unless

otherwise noted. Typical values are characterized at VSYS = 3.6 V, VLDOIN3 = 3.6 V,

VLDO3[4:0] = 11111, ILDO3 = 10 mA, and 25 °C, unless otherwise noted.

Table 23. LDO3 electrical characteristics

Symbol Parameter Min Typ Max Unit

VLDO3IN Operating input voltage

VLDO3 + 250 mV ≤ VSYS ≤ 4.5 V

1.0 — 4.5 V

VLDO3NOM Nominal output voltage — See Table 41 — V

ILDO3MAX Rated output load current, Normal mode 300 — — mA

ILDO3MAXLPM Rated output load current, Low-power mode 10 — — mA

VLDO3TOL Output voltage tolerance, Normal mode

VLDO3INMIN < VLDO3IN < 4.5 V, 0 mA < ILDO3 < 300 mA

0.8 V ≤ VLDO3 < 1.8 V

1.8 V ≤ VLDO3 ≤ 3.3 V

VLDO3INMIN < VLDO3IN < 4.5 V, 0 mA < ILDO3 < 10 mA

(Low-power mode)

−2.5

−4.0

—

2.5

4.0

ILDO3LIM Current limit

ILDO3 when VLDO3 is forced to VLDO3NOM/2

320 — 1000 mA

ILDO3OCP LDO3FAULTI threshold (also used to disable LDO3

when REGSCPEN = 1)

320 — 1000 mA

ILDO3Q Quiescent current (at 25 °C)

No load, change in IVSYS and IVLDOIN3

When LDO3 enabled in Normal mode

When LDO3 enabled in Low-power mode

—

2.5

—

µA

RDSON_QFN_LDO3 Dropout on resistance — — 350 mΩ

PSRRLDO3 PSRR

ILDO3 = 150 mA, 20 Hz to 20 kHz

VLDO3 = 3.30 V, VLDO3IN = 3.8 V, VSYS = 4.2 V

—

TRVLDO3 Turn on time

10 % to 90 % of end value

VLDO3INMIN < VLDO3IN < 4.5 V, ILDO3 = 0.0 mA

—

200

500

µs

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

22 / 149

Symbol Parameter Min Typ Max Unit

RLDO3DIS Turn off discharge resistance — 250 — Ω

LDO3OUTOSHT Start-up overshoot (% of final value)

VLDO3INMIN < VLDO3IN ≤ 4.5 V, ILDO3 = 0.0 mA

—

1.0

2.0

VLDO3LOTR Transient load response

VLDO3INMIN < VLDO3IN ≤ 4.5 V, ILDO3 = 10 mA to 100 mA in

10 μs

Overshoot

Undershoot

—

5.3.7 Electrical characteristics – VREFDDR

TA = −40 to 105 °C, VSYS = 2.5 to 4.5 V, IREFDDR = 0.0 mA, VINREFDDR = 1.35 V

and typical external component values, unless otherwise noted. Typical values are

characterized at VSYS = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.35 V, and 25 °C, unless

otherwise noted.

Table 24. VREFDDR electrical characteristics

Symbol Parameter Min Typ Max Unit

VINREFDDR Operating input voltage range 0.9 — 1.8 V

VREFDDR Output voltage, 0.9 V < VINREFDDR < 1.8 V, 0 mA < IREFDDR <

10 mA

— VINREFDDR/2 — V

VREFDDRTOL Output voltage tolerance, as a percentage of VINREFDDR, 1.2 V

< VINREFDDR < 1.65 V, 0 mA < IREFDDR < 10 mA

49.25 50 50.75 %

IREFDDRQ Quiescent current (at 25 °C) — 1.1 — µA

IREFDDRLM Current limit, IREFDDR when VREFDDR is forced to VINREFDDR/4 10.5 24 38 mA

tONREFDDR Turn on time, 10 % to 90 % of end value, VINREFDDR = 1.2 V to

1.65 V, IREFDDR = 0.0 mA

— — 100 µs

5.3.8 Electrical characteristics – VSNVS

All parameters are specified at TA = −40 to 105 °C, VSYS = 3.6 V, VSNVS = 3.0 V, ISNVS

= 5.0 μA, typical external component values, unless otherwise noted. Typical values

are characterized at VSYS = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless

otherwise noted.

Table 25. VSNVS electrical characteristics

Symbol Parameter Min Typ Max Unit

VSNVSIN Operating input voltage

Valid coin cell range

Valid VSYS

1.8

2.45

—

3.3

4.5

ISNVS Operating load current

VSNVSINMIN < VSNVSIN < VSNVSINMAX

2000 — — µA

VTL1 VSYS threshold (VSYS powered to coin cell powered) — UVDET failing — V

VTH1 VSYS threshold (coin cell powered to VSYS powered) — UVDET rising — V

VSNVS Output voltage (when running from VSYS)

0 µA < ISNVS < 2000 µA

Output voltage (when running from LICELL)

0 µA < ISNVS < 2000 µA

2.84 V < VCOIN < 3.3 V

−7.0 %

VCOIN − 0.20

3.0

—

7.0 %

—

VSNVSDROP Dropout voltage

VSYS = 2.9 V

ISNVS = 2000 µA

— — 220 mV

ISNVSLIM Current limit

VSYS > VTH1

5200

—

24000

µA

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

23 / 149

Symbol Parameter Min Typ Max Unit

VSNVSTON Turn on time (load capacitor, 0.47 µF)

10 % to 90 % of final value VSNVS

VCOIN = 0.0 V, ISNVS = 0 µA

—

3.0

VSNVSOSH Start-up overshoot

ISNVS = 5.0 µA

dVSYS/dt = 50 mV/µs

—

RDSONSNVS Internal switch RDS(on)

VCOIN = 2.6 V

—

100

5.3.9 Electrical characteristics – IC level bias currents

All parameters are specified at 25 °C, VSYS = 3.6 V, VBUSIN = 0 V, typical external

component values, unless otherwise noted. Typical values are characterized at VSYS =

3.6 V, VSNVS = 3.0 V, and 25 °C, unless otherwise noted.

Table 26. IC level electrical characteristics

Mode PF1550 conditions System conditions Typ Max Unit

Coin cell VSNVS from LICELL

All other blocks off

VSYS = 0.0 V

No load on VSNVS 1.5 4.0 µA

CORE_OFF VSNVS from VSYS

Wake-up from ONKEY active

All other blocks off

VSYS > UVDET

No load on VSNVS, PMIC able to wake-up 1.5 4.0 µA

Sleep VSNVS from VSYS

Wake-up from PWRON active

Trimmed reference active

DDR I/O rail in Low-power mode

VREFDDR disabled

No load on VSNVS. DDR memories in self

refresh.

12.5 25 µA

Standby/Suspend VSNVS from either VSYS or LICELL

SW1 in ultra Low-power mode

SW2 in ultra Low-power mode

SW3 in ultra Low-power mode

Trimmed reference active

VLDO1 is disabled

VLDO2 enabled in Low-power mode

VLDO3 enabled in Low-power mode

VREFDDR enabled

No load on VSNVS. Processor enabled in

Low-power mode.

23 46 µA

REGS_DISABLE VSNVS from VSYS

Wake-up from ONKEY active

Most other blocks off

VSYS > UVDET

No load on VSNVS, PMIC able to wake-up 14 20 µA

SHIP BATFET open, no LICELL connected

VSYS = 0 V, only awake from ONKEY

enabled

0.45 1.0 µA

6 Detailed description

The PF1550 PMIC features three high efficiency low quiescent current buck regulators,

three LDO regulators, a DDR voltage reference to supply voltages for the application

processor and peripheral devices.

Additionally, PF1550 incorporates a single cell Li-ion linear battery charger with a USB-

PHY regulator.

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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The buck regulators provide the supply to processor cores and to other low voltage

circuits such as I/O and memory. Dynamic voltage scaling is provided to allow controlled

supply rail adjustments for the processor cores for power optimization.

The three LDO regulators are general purpose to power various processor rails, system

connectivity devices and/or peripherals. Depending on the system power configuration,

the general purpose LDO regulators can be directly supplied from the main system

supply VSYS or from the switching regulators to power peripherals, such as audio,

camera, Bluetooth, Wireless LAN.

A specific VREFDDR voltage reference is included to provide accurate reference voltage

for DDR memories operation.

The VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS

(Secure Non-Volatile Storage) /RTC (Real Time Clock) circuitry on the processor.

VSNVS is powered from VSYS or from a coin cell.

To accommodate applications that do not include Li-ion battery, the PF1550 battery

charger regulates the input voltage at VBUSIN pin down to maximum of 4.5 V at VSYS

through the power path circuit.

Table 27. Voltage regulators

Supply Output voltage (V) Programming

step size (mV)

Load current

(mA)

SW1 / SW2 0.60 to 1.3875 / 1.1 to 3.3 12.5 / variable 1000

SW3 1.80 to 3.30 100 1000

LDO1 0.75 to 1.50

1.80 to 3.30

100

300

LDO2 1.80 to 3.30 100 400

LDO3 0.75 to 1.50

1.80 to 3.30

100

300

USBPHY 3.3 or 4.9 — 60

VSNVS 3.0 N/A 2

VREFDDR 0.5*VINREFDDR N/A 10

6.1 Buck regulators

The PF1550 features three high efficiency buck regulators with internal compensation.

Each buck regulator is capable of meeting optimum power efficiency operation using

reduced power variable-frequency pulse skip switching scheme at light loads as well

as operating in forced PWM quasi-fixed frequency switching mode at higher loads. The

switching regulator controller combines the advantages of hysteretic and voltage mode

control which provides outstanding load regulation and transient response, low output

ripple voltage and seamless transition between pulse-skip mode and Active Quasi-fixed

frequency switching mode. The control circuitry includes an AC loop which senses the

output voltage (at SWxFB pin) and directly feeds it to a fast comparator stage. This

comparator sets the switching frequency, which is almost constant for steady state

operating conditions. It also provides immediate response to dynamic load changes.

In order to achieve accurate DC load regulation, a voltage feedback loop is used. The

internally compensated regulation network achieves fast and stable operation with small

external components and low ESR capacitors. The transition into and out of low power

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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pulse-skip switching mode takes place automatically according to the load current to

maintain optimum power efficiency. Additionally, further power savings through cutting

the buck circuitry quiescent current can be achieved by activating a Low-power mode

upon entering either STANDBY or SLEEP PMIC power mode or as commanded via I2C

control bits. In SW1 and SW2. An OTP option enables or disables DVS in the regulators.

When DVS is disabled and the low-power bit is set, the regulator enters an Ultra Low

Power (ULP) mode cuts the operating quiescent current even in order to reach extremely

low standby power levels needed for ultra low power processors such as that from

Kinetis K and L series.

As indicated above, the buck controller supports PWM (Pulse Width Modulation) mode

for medium and high load conditions and low-power variable-frequency pulse skip mode

at light loads. During high current mode, it operates in continuous conduction and the

switching frequency is up to 2.0 MHz with a controlled on-time variation depending on the

input voltage and output voltage. If the load current decreases, the converter seamlessly

enters the pulse-skip mode to cut the operating quiescent current and maintain high

efficiency down to very light loads. In pulse-skip mode the switching frequency varies

linearly with the load current. Since the controller supports both power modes within one

single building block, the transition from normal power mode to lower power pulse-skip

mode and vice versa is seamless without dramatic effects on the output voltage.

In the adopted pulse-skip scheme, the device generates a single switching pulse to ramp

up the inductor current and recharge the output capacitor, followed by a non-switching

(pause) period where most of the internal circuits are shutdown to achieve a lowest

quiescent current. During this time, the load current is supported by the output capacitor.

The duration of the pause period depends on the load current and the inductor peak

current.

6.2 SW1 and SW2 detailed description

SW1 and SW2 are identical buck regulators designed to carry a nominal load current

of 1.0 A. Detailed characteristics and features of SW1 and SW2 are described in this

section. Being identical, reference is made only to SWx though the same specifications

apply to SW1 and SW2.

6.2.1 SWx dynamic voltage scaling description

SWx integrates an optional DVS circuit that is enabled via OTP. To reduce overall power

consumption, when DVS is enabled SWx output voltage can be varied depending on the

mode or activity level of the processor.

• Normal operation:

The output voltage is selected by I2C bits SWx_VOLT[5:0]. A voltage transition initiated

by I2C is governed by the SWx_DVSSPEED I2C bit as shown in Table 28.

• Standby mode:

The output voltage can be selected by I2C bits SWx_STBY_VOLT[5:0]. Voltage

transitions initiated by a Standby event are governed by the SWx_DVSSPEED I2C bit

as shown in Table 28. This applies only when DVS is enabled.

• Sleep mode:

The output voltage can be higher or lower than in normal operation, but is typically

selected to be the lowest state retention voltage of a given processor; it is selected

by I2C bits SWx_SLP_VOLT[5:0]. Voltage transitions initiated by a turn off event are

governed by the SWx_DVSSPEED I2C bit for SWx as shown in Table 28. This applies

only when DVS is enabled.

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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As shown in Figure 5, during a falling DVS transition, dv/dt of the output voltage depends

on the load current. Setting the SWx_FPWM_IN_DVS bit forces the regulator in the

FPWM mode during the falling transition allowing it to accurately track the DVS reference

removing the load dependency. The SWx_FPWM_IN_DVS bit is active only when

OTP_SWx_DVS_SEL = 0.

Table 28. SWx DVS setting selection

SWx_DVS speed Function

0 12.5 mV step each 2.0 µs

1 12.5 mV step each 4.0 µs

aaa-023876

Output

voltage

Internally

controlled steps

Internally

controlled steps

Requested

set point Output voltage

with light load

Example

actual output

voltage

Possible

output voltage

window

Request for

lower voltage

Initiated by I2C programming, standby control or DVS control

Request for

higher voltage

Actual

output voltage

Initial

set point

Voltage

change

request

Figure 5. SWx DVS transitions

6.2.2 SWx DVS and non-DVS operation

SWx has two distinct modes of operation selectable via OTP:

•DVS enabled: a DVS reference is activated and output accuracy of the regulator

is tight at the cost of slightly higher quiescent current. See Section 5.3 "Electrical

characteristics" for details. In Figure 6, DVS FB and DVS REF are enabled via OTP for

this mode of operation.

•DVS disabled: the regulator operates as a traditional buck converter with a fixed

reference and soft-start. The quiescent current in this mode is lower at the cost of

output accuracy and transient response. See Section 5.3 "Electrical characteristics"

for details. In Figure 6, VREF FB and VREF are enabled via OTP for this mode of

operation.

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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ibias

Programmable resistor divider VOUT: 1.1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.0, 3.3 (three bits)

Fixed DVS feedback and compensation

Programmable DVS feedback and compensation

Fixed bandgap reference with soft-start function

Reduced accuracy and transient capabilities

VREF FB

VREF

DVS FB

DVS REF

Bias control

VOUT

DVS FB

VREF FB

sel

COMP

DVS REF

VREF

sel

Low

PWR

Low

PWR

VIN

VOUT

TON

iLim

CTRL

logic

Driver

TOFF ZCD

iLim

aaa-023877

Figure 6. SWx DVS and non-DVS selection

6.2.3 Regulator control

To improve system efficiency the buck regulators can operate in different switching/

bias modes. The changing between DCM (Discontinuous Conduction Mode) / CCM

(Continuous Conduction Mode) takes place automatically based on detecting the load

current level. It can be enforced by one of the following means: I2C programming, exiting/

entering the Standby mode, exiting/entering Sleep/ Low-power mode.

Available modes for buck regulators are presented in Table 29. These switching modes

are available with OTP_SWx_DVS_SEL = 0 and OTP_SWx_DVS_SEL = 1. Table 30

shows the bit settings for operating the buck converter is these modes based on the

PMIC operating state.

Table 29. Buck regulator operating modes

Mode Description

OFF The regulator is switched off and the output voltage is discharged using an internal resistor.

Adaptive This is the default mode of operation of the buck regulator. In this mode, the regulator operates in a quasi-fixed

frequency switching mode at moderate and high loads, with pulse skip (variable switching frequency) scheme at light

load for optimized efficiency.

F-PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions.

Low-power To further extend power savings when the load current is minimal, this mode cuts the quiescent current of the buck

converter by reducing the bias to the comparator. The regulator is operated in low power modes (Standby and/or

Sleep) with the proper I2C setting. See Table 30.

The following table shows actions to control different bits for SW1 and SW2.

Table 30. Buck mode control

PMIC state SWx_EN SWx_STBY SWx_OMODE SWx_LPWR SWx_FPWM SWx operating mode

Run/Standby/Sleep 0 X X X X SW disabled

Run 1 X X 0 0 SW enabled. Operates in DCM at light

loads

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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PMIC state SWx_EN SWx_STBY SWx_OMODE SWx_LPWR SWx_FPWM SWx operating mode

Run 1 X X 0 1 SW enabled. Forced PWM mode

Run 1 X X 1 0 SW Enabled. Does not operate in Low-

power mode.

Run 1 X X 1 1 SW enabled. Forced PWM mode – not

Low-power mode.

Standby 1 0 X X X SW disabled

Standby 1 1 X 0 0 SW enabled. Operates in DCM at light

loads.

Standby 1 1 X 0 1 SW enabled. Forced PWM mode.

Standby 1 1 X 1 0 SW enabled. Operates in Low-power

mode.

Standby 1 1 X 1 1 SW enabled. Forced PWM mode – not

Low-power mode.

Sleep 1 X 0 X X SW disabled

Sleep 1 X 1 0 0 SW enabled. Operates in DCM at light

loads.

Sleep 1 X 1 0 1 SW enabled. Forced PWM mode.

Sleep 1 X 1 1 0 SW enabled. Operates in Low-power

mode.

Sleep 1 X 1 1 1 SW enabled. Forced PWM mode – not low

power mode.

6.2.4 Current limit protection

SWx features high and low-side FET current limit. When current through the FETs goes

above their respective thresholds, the FET is turned-off to prevent further increase in

current.

The protection is enabled in a cycle-by-cycle mode. Hitting either current limit sets

the corresponding interrupt sense bits. If the faults persist for longer than the 8.0 ms

debounce time, the interrupt status bit is set.

6.2.5 Output voltage setting in SWx

Output voltage of SWx is programmable via OTP. During startup (REGS_DISABLE

mode to RUN mode), contents of the OTP_SWx_VOLT[5:0] are mapped into the

SWx_VOLT[5:0], SWx_STBY_VOLT[5:0] and SWx_SLP_VOLT[5:0] register which set

the regulator output voltage during Run, Standby and Sleep modes respectively.

In the DVS enabled mode (OTP_SWx_DVS_SEL = 0), values of SWx_VOLT[5:0],

SWx_STBY[VOLT[5:0] and SWx_SLP_VOLT[5:0] can be changed via I2C after the PMIC

starts up (RESETBMCU is released).

In the DVS disabled mode (OTP_SWx_DVS_SEL = 1), value of SWx_VOLT[5:0],

SWx_STBY[VOLT[5:0] and SWx_SLP_VOLT[5:0] are read-only and must not be written

to.

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 31. SW1 and SW2 output voltage setting

Set

point

SWx_VOLT[5:0]

SWx_STBY_VOLT[5:0]

SWx_SLP_VOLT[5:0]

Output voltage

with DVS enabled

OTP_SWx_DVS_SEL = 0

Output voltage

with DVS disabled

OTP_SWx_DVS_SEL = 1

0 000000 0.6000 1.10

1 000001 0.6125 1.20

2 000010 0.6250 1.35

3 000011 0.6375 1.50

4 000100 0.6500 1.80

5 000101 0.6625 2.50

6 000110 0.6750 3.00

7 000111 0.6875 3.30

8 001000 0.7000 3.30

9 001001 0.7125 3.30

10 001010 0.7250 3.30

11 001011 0.7375 3.30

12 001100 0.7500 3.30

13 001101 0.7625 3.30

14 001110 0.7750 3.30

15 001111 0.7875 3.30

16 010000 0.8000 3.30

17 010001 0.8125 3.30

18 010010 0.8250 3.30

19 010011 0.8375 3.30

20 010100 0.8500 3.30

21 010101 0.8625 3.30

22 010110 0.8750 3.30

23 010111 0.8875 3.30

24 011000 0.9000 3.30

25 011001 0.9125 3.30

26 011010 0.9250 3.30

27 011011 0.9375 3.30

28 011100 0.9500 3.30

29 011101 0.9625 3.30

30 011110 0.9750 3.30

31 011111 0.9875 3.30

32 100000 1.0000 3.30

33 100001 1.0125 3.30

34 100010 1.0250 3.30

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Set

point

SWx_VOLT[5:0]

SWx_STBY_VOLT[5:0]

SWx_SLP_VOLT[5:0]

Output voltage

with DVS enabled

OTP_SWx_DVS_SEL = 0

Output voltage

with DVS disabled

OTP_SWx_DVS_SEL = 1

35 100011 1.0375 3.30

36 100100 1.0500 3.30

37 100101 1.0625 3.30

38 100110 1.0750 3.30

39 100111 1.0875 3.30

40 101000 1.1000 3.30

41 101001 1.1125 3.30

42 101010 1.125 3.30

43 101011 1.1375 3.30

44 101100 1.1500 3.30

45 101101 1.1625 3.30

46 101110 1.1750 3.30

47 101111 1.1875 3.30

48 110000 1.2000 3.30

49 110001 1.2125 3.30

50 110010 1.2250 3.30

51 110011 1.2375 3.30

52 110100 1.2500 3.30

53 110101 1.2625 3.30

54 110110 1.2750 3.30

55 110111 1.2875 3.30

56 111000 1.3000 3.30

57 111001 1.3125 3.30

58 111010 1.3250 3.30

59 111011 1.3375 3.30

60 111100 1.3500 3.30

61 111101 1.3625 3.30

62 111110 1.3750 3.30

63 111111 1.3875 3.30

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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6.2.6 SWx external components

Table 32 shows the combination of inductor and capacitor values that work with the SWx

regulator.

The design is optimized for a 1.0 µH inductor.

Table 32. Acceptable inductance and capacitance values

Inductance / capacitance 2 x 10 µF

1.0 µH

Table 33 and Table 34 show example inductor and capacitor part numbers respectively.

Table 33. Example inductor part numbers

Part number Size (mm) 1.0 µH

DFE201610E 2.0 x 1.6 57 mΩ, 3.6 A

DFE201610P 2.0 x 1.6 70 mΩ, 3.1 A

DFE201210U 2.0 x 1.2 95 mΩ, 3.1 A

DFE160810S 1.6 x 0.8 120 mΩ, 2.0 A

DFE201208S 2.0 x 1.2 86 mΩ, 2.4 A

DFE160808S 1.6 x 0.8 144 mΩ, 1.9 A

Table 34. Example capacitor part numbers

Murata part number Description

GRM188R60J106ME47D 6.3 V, 10 µF, 0402, X5R

GRM188D70J106MA73 6.3 V, 10 µF, 0402, X7R

GRM188R61A106KE69 10 µF 10 V 10 % X5R 0603 .95 mm

GRM219R61A106KE44 10 µF 10 V 10 % X5R 0805 .95 mm

6.3 SW3 detailed description

SW3 is a buck regulator designed to carry a nominal load current of 1.0 A. The output

voltage is programmable from 1.8 V to 3.3 V in 100 mV steps. Dynamic voltage scaling is

not supported in this regulator.

Programmable resistor divider VOUT (four bits): 1.8 V to 3.3 V in 100 mV steps

Fixed bandgap reference with soft-start function

Reduced accuracy and transient capabilities

VREF FB

VREF

Bias control

VREF FB

COMP

VREF

Low

PWR

ibias

Low

PWR

VIN

VOUT

TON iLim

CTRL

logic

Driver

TOFF ZCD

iLim

aaa-023878

VOUT

Figure 7. SW3 block diagram

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

32 / 149

6.3.1 Regulator control

To improve system efficiency the buck regulator can operate in different switching/

bias modes. The changing between DCM/CCM takes place automatically based on

detecting the load current level. It can be enforced by one of the following means: I2C

programming, exiting/entering the Standby mode, exiting/entering Sleep/ Low-power

mode.

Available modes for buck regulators are presented in Table 35 .

Table 36 shows the bit settings for operating the buck converter in these modes based

on the PMIC operating state.

Table 35. SW3 buck regulator operating modes

Mode Description

OFF The regulator is switched off and the output voltage is discharged using an internal resistor.

Adaptive This is the default mode of operation of the buck regulator. In this mode, the regulator

operates in a quasi-fixed frequency switching mode at moderate and high loads, with pulse

skip (variable switching frequency) scheme at light load for optimized efficiency.

F-PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions.

Low-power To further extend power savings when the load current is minimal, this mode cuts the

quiescent current of the buck converter by reducing the bias to the comparator. The regulator

is operated in low power modes (Standby and/or Sleep) with the proper I2C setting. See

Table 36.

Table 36. SW3 buck mode control

PMIC state SW3_EN SW3_STBY SW3_OMODE SW3_LPWR SW3_FPWM SW3 operating mode

Run/Stan

dby/Sleep

0 X X X X SW disabled

Run 1 X X 0 0 SW enabled

Operates in DCM at light

loads

Run 1 X X 0 1 SW enabled

Forced PWM mode

Run 1 X X 1 0 SW enabled

Does not operate in Low-

power mode

Run 1 X X 1 1 SW enabled

Forced PWM mode

Standby 1 0 X X X SW disabled

Standby 1 1 X 0 0 SW enabled

Operates in DCM at light

loads

Standby 1 1 X 0 1 SW enabled

Forced PWM mode

Standby 1 1 X 1 0 SW Enabled

Operates in Low-power mode

Standby 1 1 X 1 1 SW enabled

Forced PWM mode

Sleep 1 X 0 X X SW disabled

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Power management integrated circuit (PMIC) for low power application processors

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PMIC state SW3_EN SW3_STBY SW3_OMODE SW3_LPWR SW3_FPWM SW3 operating mode

Sleep 1 X 1 0 0 SW enabled

Operates in DCM at light

loads

Sleep 1 X 1 0 1 SW enabled

Forced PWM mode

Sleep 1 X 1 1 0 SW enabled

Operates in Low-power mode

Sleep 1 X 1 1 1 SW enabled

Forced PWM mode

6.3.2 Current limit protection

SW3 features high and low-side FET current limit. When current through the FETs goes

above their respective thresholds, the FET is turned-off to prevent further increase in

current.

The protection is enabled in a cycle-by-cycle mode. Hitting either current limit sets

the corresponding interrupt sense bits. If the faults persist for longer than the 8.0 ms

debounce time, the interrupt status bit is set.

6.3.3 Output voltage setting in SW3

Output voltage of SW3 is programmable via OTP. During start up (REGS_DISABLE

mode to RUN mode), contents of the OTP_SW3_VOLT[5:0] are mapped into the

SW3_VOLT[5:0], SW3_STBY_VOLT[5:0] and SW3_SLP_VOLT[5:0] register which set

the regulator output voltage during Run, Standby and Sleep modes respectively.

Values of SW3_VOLT[5:0], SW3_STBY[VOLT[5:0] and SW3_SLP_VOLT[5:0] are read-

only and cannot be written to.

Table 37. SW3 output voltage setting

Set point SW3_VOLT[3:0]

SW3_STBY_VOLT[3:0]

SW3_SLP_VOLT[3:0]

Output voltage (V)

0 0000 1.80

1 0001 1.90

2 0010 2.00

3 0011 2.10

4 0100 2.20

5 0101 2.30

6 0110 2.40

7 0111 2.50

8 1000 2.60

9 1001 2.70

10 1010 2.80

11 1011 2.90

12 1100 3.00

13 1101 3.10

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Set point SW3_VOLT[3:0]

SW3_STBY_VOLT[3:0]

SW3_SLP_VOLT[3:0]

Output voltage (V)

14 1110 3.20

15 1111 3.30

6.3.4 SW3 external components

Table 38 shows the combination of inductor and capacitor values that work with the SW3

regulator.

Table 38. Acceptable inductance and capacitance values

Inductance / capacitance 2 x 10 µF

1.0 µH

Table 39 and Table 40 show example inductor and capacitor part numbers respectively.

Table 39. Example inductor part numbers

Part number Size (mm) 1.0 µH

DFE201610E 2.0 x 1.6 57 mΩ, 3.6 A

DFE201610P 2.0 x 1.6 70 mΩ, 3.1 A

DFE201210U 2.0 x 1.2 95 mΩ, 3.1 A

DFE160810S 1.6 x 0.8 120 mΩ, 2.0 A

DFE201208S 2.0 x 1.2 86 mΩ, 2.4 A

DFE160808S 1.6 x 0.8 144 mΩ, 1.9 A

Table 40. Example capacitor part numbers

Murata part number Description

GRM188R60J106ME47D 6.3 V, 10 µF, 0402, X5R

GRM188D70J106MA73 6.3 V, 10 µF, 0402, X7R

GRM188R61A106KE69 10 µF 10 V 10 % X5R 0603 .95 mm

GRM219R61A106KE44 10 µF 10 V 10 % X5R 0805 .95 mm

7 Low dropout linear regulators, VREFDDR and VSNVS

7.1 General description

This section describes the LDO regulators provided by the PF1550. All regulators use the

main bandgap as reference.

When a regulator is disabled, the output is discharged by an internal pulldown.

VLDO1 and VLDO3 can be used as load switches by setting the corresponding Load

Switch enable bit OTP_VLDOx_LS.

All general purpose LDOs have short-circuit protection capability. The Short-circuit

Protection (SCP) system includes de-bounced fault condition detection, regulator

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

35 / 149

shutdown, and processor interrupt generation, to contain failures and minimize the

chance of product damage. If a short-circuit condition is detected and REGSCPEN

bit is set, the LDO is disabled by resetting its VLDOxEN bit, while at the same time,

an interrupt VLDOxFAULTI is generated to flag the fault to the system processor. The

VLDOxFAULTI interrupt is maskable through the VLDOxFAULTM mask bit.

The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the

regulators are not automatically be disabled upon a short-circuit detection. However,

the current limiter continues to limit the output current of the regulator. By default, the

REGSCPEN is not set; therefore, at start up none of the regulators are disabled if an

overloaded condition occurs. A fault interrupt, VLDOxFAULTI is generated in an overload

condition regardless of the state of the REGSCPEN bit. Each LDO features a Low-power

mode where the quiescent current consumed is significantly lower than in regulator

operation. In the Low-power mode, load current of each regulator is limited to 10 mA.

7.2 LDO1 and LDO3 detailed description

LDO1 and LDO3 are identical 300 mA low dropout (LDO) regulators that provide output

voltage with high accuracy and are programmable through I2C interface bits. Being

identical, reference is made to these LDOs as LDOy.

To support this wide input range, LDOy circuit incorporates a PMOS pass FET as well as

an NMOS pass FET. The LDO uses the main bandgap as its reference.

The regulator incorporates a soft-start circuit that ramps the internal reference in order

to provide smooth output waveform with minimal overshooting during power up. When

the regulator is disabled, the output is discharged by an internal pulldown resistor.

Additionally, the LDO can be used as a load switch by setting the corresponding Load

Switch enable bit OTP_LDOy_LS.

Moreover, LDOy includes current limit protection with the option to turn off the LDO when

an overcurrent is detected.

7.2.1 Features summary

•Input range LDO from 1.0 V to 4.5 V

•Programmable output voltage between 0.75 V to 1.5 V (uses NMOS) or 1.8 V and

3.3 V (uses PMOS) with 2 % accuracy

•Soft-start ramp control during power up and discharge mechanism during power down

•Low quiescent current (~ 2.5 µA) at Low-power mode

•Current limit protection

•Configurable into load switch via OTP bit

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

36 / 149

7.2.2 LDOy block diagram

Discharge

VDD

VINx

VREF

LDOxEN

LDOxLPWR

LDOx

I2C

interface

LDOxIN

LDOxOUT

CLDOx

aaa-023879

Figure 8. LDOy Block Diagram

7.2.3 LDOy external components

Use a 4.7 µF X5R/X7R capacitor from output to ground with a voltage rating at least 2

times the nominal output voltage.

7.2.4 LDOy output voltage setting

LDOy output voltage is programmed by setting the LDOy[4:0] bits as shown in Table 41.

Table 41. LDOy output voltage setting

Set point LDOy[4:0] LDOy output (V)

0 00000 0.7500

1 00001 0.8000

2 00010 0.8500

3 00011 0.9000

4 00100 0.9500

5 00101 1.0000

6 00110 1.0500

7 00111 1.1000

8 01000 1.1500

9 01001 1.2000

10 01010 1.2500

11 01011 1.3000

12 01100 1.3500

13 01101 1.4000

14 01110 1.4500

15 01111 1.5000

16 10000 1.8000

17 10001 1.9000

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Set point LDOy[4:0] LDOy output (V)

18 10010 2.0000

19 10011 2.1000

20 10100 2.2000

21 10101 2.3000

22 10110 2.4000

23 10111 2.5000

24 11000 2.6000

25 11001 2.7000

26 11010 2.8000

27 11011 2.9000

28 11100 3.0000

29 11101 3.1000

30 11110 3.2000

31 11111 3.3000

7.2.5 LDOy low power mode operation

LDOy can operate in a Low-power mode with reduced quiescent current. The Low-power

mode can be activated in Standby and Sleep modes by setting the LDOy_LPWR bit as

shown in Table 42. Maximum load current is limited to 10 mA when operating in the Low-

power mode.

Table 42. LDOy control bits

PMIC state LDOy_EN LDOy_STBY LDOy_OMODE LDOy_LPWR LDOy operating mode

Run/Standby/Sleep 0 X X X LDO disabled

Run 1 X X X LDO enabled

Standby 1 0 X X LDO disabled

Standby 1 1 X 0 LDO enabled

Standby 1 1 X 1 LDO enabled in Low-power mode

Sleep 1 X 0 X LDO disabled

Sleep 1 X 1 0 LDO enabled

Sleep 1 X 1 1 LDO enabled in Low-power mode

7.2.6 LDOy current limit protection

LDOy has built in current limit protection. When the load current exceeds the current

limit threshold, the regulator goes from a voltage regulation mode to a current regulation

mode that limits the available output current.

By setting the REGSCPEN bit, LDOy can be automatically disabled in the event of

an over current situation. In the event of an over current, the LDO will be disabled

by resetting its LDOy_EN bit, while at the same time an interrupt LDOy_FAULTI is

generated to flag the fault to the system processor. The LDOy_FAULTI interrupt is

maskable through the LDOy_FAULTM mask bit.

If REGSCPEN is not set, the regulator will not be automatically disabled, but will instead

enter the current limit mode. By default, the REGSCPEN is not set; therefore, at start-

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

38 / 149

up none of the regulators will be disabled if an overloaded condition occurs. A fault

interrupt, LDOy_FAULTI, is generated in an overload condition regardless of the state of

the REGSCPEN bit.

Current limit is not active when LDOy is operated in the load switch mode.

7.2.7 LDOy load switch mode

The LDOy path can be turned into a switch by setting the OTP_LDOy_LS bit. Setting this

bit fully turns on the LDO pass FET. This could be useful if power domain partitioning or

additional isolation is needed on the system application. Soft-start is engaged during start

up of the load switch to reduce inrush currents.

7.3 LDO2 detailed description

LDO2 is a 400 mA low dropout (LDO) regulator that provides output voltage with high

accuracy and programmable through I2C/ interface bits. To support this wide input range

the LDO circuit incorporates a PMOS pass FET. The LDO uses the main bandgap as its

reference.

The regulator incorporates a soft-start circuit that ramps the internal reference in order

to provide smooth output waveform with minimal overshooting during power up. When

the regulator is disabled, the output is discharged by an internal pulldown resistor. The

pulldown is also activated when RESETBMCU is low.

Moreover, LDO2 includes current limit protection with option to turn off the LDO when an

overcurrent is detected.

7.3.1 LDO2 features summary

•Input range LDO from 2.8 V to 4.5 V

•Programmable output voltage between 1.8 V and 3.3 V with 2 % accuracy

•Soft-start ramp control during power up and discharge mechanism during power down

•Low quiescent current (~ 1.5 µA) at Low-power mode

•Current limit protection

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

39 / 149

7.3.2 LDO2 block diagram

Discharge

VREF

LDOxEN

LDOxLPWR

LDOx

I2C

interface

LDOxIN

LDOxOUT

CLDOx

aaa-023880

Figure 9. LDO2 block diagram

7.3.3 LDO2 external components

Use a 10 µF X5R/X7R capacitor from output to ground with a voltage rating at least 2

times the nominal output voltage.

7.3.4 LDO2 output voltage setting

LDO2 output voltage is programmed by setting the VLDO2[3:0] bits as shown in

Table 43.

Table 43. LDO2 output voltage setting

Set point VLDO2[3:0] VLDO2 output (V)

0 0000 1.80

1 0001 1.90

2 0010 2.00

3 0011 2.10

4 0100 2.20

5 0101 2.30

6 0110 2.40

7 0111 2.50

8 1000 2.60

9 1001 2.70

10 1010 2.80

11 1011 2.90

12 1100 3.00

13 1101 3.10

14 1110 3.20

15 1111 3.30

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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7.3.5 LDO2 Low-power mode operation

LDO2 can operate in a Low-power mode with reduced quiescent current. The low power

mode can be activated in Standby and Sleep modes by setting the LDO2LPWR bit as

shown in Table 44. Maximum load current is limited to 10 mA when operating in the Low-

power mode.

Table 44. LDO2 control bits

PMIC state LDO2EN LDO2STBY LDO2OMODE LDO2LPWR LDO2 operating mode

Run 0 X X X LDO disabled

Run 1 X X X LDO enabled

Standby 1 0 X X LDO disabled

Standby 1 1 X 0 LDO enabled

Standby 1 1 X 1 LDO enabled in Low-power mode

Sleep 1 X 0 X LDO disabled

Sleep 1 X 1 0 LDO enabled

Sleep 1 X 1 1 LDO enabled in Low-power mode

7.3.6 LDO2 current limit protection

LDO2 has built in current limit protection. When the load current exceeds the current

limit threshold, the regulator goes from a voltage regulation mode to a current regulation

mode limiting the available output current.

By setting the REGSCPEN bit, LDO2 can be automatically disabled in the event of an

over current situation. In the event of an over current, the LDO is disabled by resetting

its VLDO2EN bit, while at the same time an interrupt VLDO2FAULTI is generated to flag

the fault to the system processor. The VLDO2FAULTI interrupt is maskable through the

VLDO2FAULTM mask bit.

If REGSCPEN is not set, the regulator will not be automatically disabled, but instead

enter the current limit mode. By default, the REGSCPEN is not set; therefore, at start-

up none of the regulators will be disabled if an overloaded condition occurs. A fault

interrupt, VLDO2FAULTI is generated in an overload condition regardless of the state of

the REGSCPEN bit.

7.4 VREFDDR reference

VREFDDR is an internal NMOS half supply voltage follower capable of supplying up

to 10 mA. The output voltage is at one half the input voltage. It is typically used as the

reference voltage for DDR memories.

A filtered resistor divider is utilized to create a low frequency pole. This divider then

utilizes a voltage follower to drive the load.

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

41 / 149

Discharge

VINREFDDR

VREFDDR

CREFDDR

aaa-023881

1.0 µF

Figure 10. VREFDDR block diagram

7.5 VSNVS LDO/Switch

VSNVS powers the low-power SNVS/RTC domain on the processor. It derives its power

from either VSYS or a coin cell (only if the COIN_CELL bit is set). When powered by

both, VSYS powers VSNVS if VSYS > VTH threshold and LICELL powers VSNVS when

VSYS < VTL. When powered by VSYS, VSNVS is an LDO capable of supplying 2.0

mA at 3.0 V. When powered by coin cell, VSNVS output tracks the coin cell voltage by

means of a switch. In this case, the VSNVS voltage is simply the coin cell voltage minus

the voltage drop across the switch.

Upon subsequent removal of VSYS, with the coin cell attached and COIN_CELL set,

VSNVS will change configuration from an LDO to a switch.

aaa-023882

LDO/LOAD

switch

Input

sense

selector

I2C interface

VSNVS

VSYS

Coin cell

charger

1.8 to 3.3 V

PF1550

Coin cell

VREF

Figure 11. VSNVS block diagram

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

42 / 149

8 Battery charger description

The PF1550 charger is an integrated 1-cell Li+ charger with a single VBUS power input

and dual path output. All power switches for charging and switching the load between

battery and external power are included on chip. No external MOSFETs, blocking diodes

or current sense resistors are required.

The VBUS input operates from 4.0 V to 6.5 V with up to 22 V overvoltage protection. The

PF1550 internally blocks current from the battery and system back to the inputs when no

input supply is present. Other features include precharge battery conditioning and timer,

fast charge timer, battery overvoltage protection, charge status and fault outputs, battery

thermistor monitor and thermal regulation.

Figure 12 shows a high level internal block diagram of the charger block. The PMIC is

powered from the VSYS node in the PF1550.

VBUSIN

5.0 V 37

1.8 V

VDDIO

SCL

4.2 V

2 SDA

INTB

WDI

2.2 F

25 V

0603

3.3 V

1.0 F

6.3 V

0603

0.1 F

6.3 V

0603

4.7 K

0402

1.0 F

6.3 V

0603

4.7 F

10 V

0603

3.7 V

Li-ion

CC charge

100 mA to

1.0 A

10 K

0402

100 K

0402

100 K

0402

4.7 K

0402

USBPHY

CC_CHARGE

CHARGER

I_PRECHARGE

DPM_THRESHOLD

I_EOC

PHY LDO VOUT

ENABLE

6.5 V LDO 5

OVP VSYS_MIN

LED driver

Linear charger

BATFET control

6CV_CHARGE

V_PRECHARGE_THRESHOLD

WEAK_BATTERY _THRESHOLD

RESTART _THRESHOLD

Battery pack

10 K thermistor

FAULTS

REG_TEMP

CC_ADJ EPAD

THM

CV_ADJ

THM_HOT

THM_WARM

THM_COOL

THM_COLD

VSYS1 VSYS

CV charge

3.5 V to 4.44 V

VSYS2

40CHGB

VBUS_ILIMIT

LED_CURRENT

LED_FREQ

LED_PWM

VFB

ILIM

HIGH VOLTAGE

BLOCKING

LDO MOSFET

aaa-023883

BATTERY

ISOLATION

MOSFET

CC TIMER

PRECHARGE TIMER

EOC TIMER

WATCHDOG

CC_TIMEOUT

PRECHARGE_TIMEOUT

EOC_TIMEOUT

ENABLE

GND

VBATT1

VBATT2

2P7 supply INT_2P7

22 F

10 V

0603

22 F

10 V

0603

0402

LED

I2C INTERFACE

Control

logic

I2C

registers

THERMAL

TIMERS VDPM IBATT

VBATT

Figure 12. Battery charger internal block diagram

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

43 / 149

8.1 Operating modes and behavioral description

VBATT

TSSVBUS_LIN

VBUSIN

INT2P7

VBUS_VALID

BGOK

VSYS

VCORE

VCOREDIG

VBUS_ILIM

USBPHY

(3.3 V)

VDDIO

Charger

detection

0 V

1.8 V

Commanded

by processor

VSYSMIN

4.3 V

SLEEP

0x00 (100 mA) Based on

adaptor type

Processor detection sequence SLEEP

aaa-025039

Linear on

Default mode OTP

selectable (linear on

or charger on)

External

supply

Charger on

Charger

state

INT2P7

0 V

Startup sequence, USB insert, VBATT = 0 V

5.0 V

1.5 V

> 100 ms (min)

Figure 13. Charger low battery (Startup sequence, USB insert, VBATT = 0 V)

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

44 / 149

VBATT

VBUSIN

INT2P7

VBUS_VALID

VSYS

VDDIO

VCORE

VCOREDIG

VBUS_ILIM

USBPHY

(3.3 V)

Charger

detection

0 V

1.8 V

VSYSMIN

4.3 V

SLEEP

0x00 (100 mA) Based on

adaptor type

Processor detection sequence SLEEP

aaa-025040

Linear on

Default mode OTP

selectable (linear on

or charger on)

External

supply

Charger on

Charger

state

3.8 V

Startup sequence, USB insert, VBATT = 3.8 V

5.0 V

2.7 V

1.5 V

3.8 V

> 100 ms (min)

Figure 14. Charger healthy battery (Startup sequence, USB insert, VBATT = 3.8 V)

Table 45. Battery regulation voltage register

BATTERY REGULATION VOLTAGE REGISTER

ADDR: 0x8F

D7 D6 D5 D4 D3 D2 D1 D0

BITS: VSYSMIN CHGCV

POR: 00101011

ACCESS:

The VSYSMIN value is programmable via OTP as per the table below.

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 46. VSYSMIN setting

VSYSMIN[1:0] setting VSYSMIN setting (V)

00 3.5

01 3.7

10 4.3

11 Reserved

The VSYSMIN setting is the "normal" regulation point for VSYS. This parameter sets the

point where the VSYS loop starts taking control and regulates the output. 4.3 V is the

recommended setting to ensure that there is enough headroom before reaching UVDET

(PMIC undervoltage detection, 2.9 V typ.).

Selecting lower settings causes the VSYS loop to start regulating, and reduces charging

current to lower the VSYS threshold, thus reducing the headroom.

Typically, the VSYS output range can go as low as 300 mV below the VSYSMIN setting.

Therefore, the recommended setting for the VSYS output should be between 4.0 V to

4.3 V.

8.2 Charger input source detection

The charger input is compared with several voltage thresholds to determine if it is valid. A

charger input must meet the following three characteristics to be valid:

•VBUS must be above VUVLO (4.2 V max.) to be valid

•VBUS must be below its overvoltage lockout threshold (VOVLO (6.0 V min.))

•VBUS must be above the system voltage by VIN2SYS (50 mV / 175 mV programmable

via OTP)

The VBUS input generates an input interrupt when its status changes. The input status

can be read with VBUS_OK and VBUS_SNS registers. Interrupts can be masked with

VBUS_M register.

Note: Adaptor removal is defined as VBUS < VUVLO.

VBUS_xx

SYS

VVBUS_xx_OVLO

VIN2SYS

VVBUS_xx_UVLO

VBUS_UVLO

VBUS_xx_INVLD

VBUS_xx_OVLO

LIN2SYS

VBUS_INVLD

aaa-025038

Figure 15. Input source detection delay

8.3 Input self-discharge for reliable charger input interrupt

To ensure that a rapid removal and re-insertion of a charge source always results in a

charger input interrupt, the charger input presents loading to the input capacitor to ensure

that when the charge source is removed the input voltage decays below the UVLO

threshold in a reasonable time.

A 2.2 µF input capacitance charged up to the maximum OVLO threshold (VOVLO) decays

down to the minimum UVLO threshold within 300 ms (tINSD). The input self-discharge is

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

46 / 149

implemented by with a 30 kΩ resistor (RINSD) from VBUSIN input to ground. The input

self-discharge resistor is deactivated in the low-power mode to reduce total quiescent

current.

8.4 Charger state diagram

WATCHDOG Suspend

WDT_SNS = 1

CHG_OK = 0

ICHG = 0

WD Timer > tWD

(CHG Timer = Suspend,

only if WDTEN = 1)

WDTCLR=TRUE

(WD Timer = 0 & Resume

CHG Timer = Resume)

From: any prequal state, any fast charge state,

end-of-charge, done or timer fault

Returns to: the same state that it came from

Battery overvoltage

BAT_SNS = 0x09

BAT_OK = 0

ICHG = 0

VBATT > VBATOV

For time > tBATOV

VBATT < VBATOV

(Resume charge timer)

From: any precharge state, any fast charge state,

end-of-charge, done

Returns to: the same state that it came from

From: any precharge state, any fast charge state,

end-of-charge, done

Returns to: the same state that it came from

Battery Thermistor Suspend Mode

CHG_SNS = 0x07

CHG_OK = 0

ICHG = 0

Battery Temperature > THOT

Battery Temperature < TCOLD

Battery Temperature < THOT

AND

Battery Temperature > TCOLD

(Resume charge timer)

NO INPUT POWER or

CHARGER DISABLED

CHG_SNS = 0x08

CHG_OK = 0

ICHG = 0

CHG Timer = 0

WD Timer = 0

INPUT is VALID

(VBUS_VALID = 1)

and MODE PROGRAMMED

FOR CHARGER ENABLED

(CHG Timer = Start)

CHG_OPER[3:0]

PROGRAMMED THE

CHARGER TO BE OFF

INPUT is

INVALID

ANY STATE

except thermal

shutdown

TJ< TSHDN

(CHG Timer = Suspend

WD Timer = Suspend)

Direct

Transition

TJ> TSHDN

(CHG Timer = 0

WD Timer = 0)

Thermal Shutdown

CHG_SNS = 0x0A

CHG_OK = 0

ICHG = 0

CHG Timer > tPRECHG

LOW-BATTERY

PRECHARGE MODE

CHG_SNS = 0x00

CHG_OK = 1

ICHG ≤ IPRECHG.LB

VBATT < VPRECHG.LB

(CHG Timer = 0)

VBATT > VPRECHG.LB

(Soft Start, CHG Timer = 0)

TIMER FAULT

CHG_SNS = 0x06

CHG_OK = 0

ICHG = 0

FAST CHARGE (CC)

CHG_SNS = 0x01

CHG_OK = 1

VBATT ≤ VBATREG

ICHG ≤ IFC and ICHG > IEOC

FAST CHARGE (CV)

CHG_SNS = 0x02

CHG_OK = 1

ICHG ≤ IFC and ICHG > IEOC

VBATT <

95 % of VBATREG

VBATT = 99 % of VBATREG for 32 ms

CHG Timer > tFC

ICHG < IEOC for tSCIDG

(CHG Timer = 0 and Suspend)

END-OF-CHARGE

CHG_SNS = 0x03

CHG_OK = 1

ICHG ≤ IEOC

CHG Timer > tEOC

DONE

CHG_SNS = 0x04

CHG_OK = 0

ICHG = 0

VBATT < (VBATREG - VRESTART)

(No Soft Start,

CHG Timer = Restart)

VBATT < (VBATREG - VRESTART)

(No Soft Start,

CHG Timer = Restart)

aaa-025042

Figure 16. Charger state diagram

8.5 Charging profile

The battery is charged in three modes as shown below. Linear control of the BATFET

has two subset modes (Trickle and Linear constant current mode).

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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•Linear control of BATFET

–Trickle (programmable from 55 mA/100 mA based on battery voltage)

–Linear constant current mode from 100 mA to 1000 mA

•Constant current (CC)

•Constant voltage (CV)

aaa-023884

VBATREG

VRESTART

VLOW_BATT

ICHARGE_CC

IPRECHARGE

IEOC

State Battery current B

Low battery

recovery

Battery

disconnected

Fast charge

constant voltage (CV)

Fast charge

constant current (CC)

Time

End-of-charge

(EOC)

End-of-charge

(EOC)

DONE

(VSYS loaded)

Restart

fast charge

(CV)

VSYS

VBATT (> 0 V)

(0 A)

Figure 17. Charging profile

8.5.1 Precharge state

The precharge state is entered when the main-battery voltage is less than

VPRECHG.LB which is precharge (low battery) charging voltage threshold set by

PRECHGLB_THRS[6:5]. After being in this state for tSCIDG, a CHG_I interrupt is

generated, CHG_OK bit is set and CHG_SNS register is set to 0x00. In the precharge

state, the charge current into the battery is equal or lower than IPRECHG.LB (45 mA typ).

Following events causes the state machine to exit this state:

1. When the main battery voltage rises above VPRECHG.LB, the charger enters the next

state in the charging cycle: “Fast-Charge Constant Current" state.

2. If the battery charger remains in this state for longer than tPRECHG, the charger state

machine transitions to the “Timer Fault” state.

3. If the watchdog timer is not serviced, the charger state machine transitions to the

“Watchdog Suspend” state.

Note: The precharge state works with battery voltages down to 0 V.

The low 0 V operation typically allows this battery charger to revive batteries that have

an “open” internal pack protector. Typically, the pack internal protection circuit isolates

the Lithium-ion cell if the battery pack has detected an overcurrent, undervoltage or

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

48 / 149

overvoltage. When a battery with an “open” internal pack protector is used with this

charger, the low-battery precharge mode forces a small current into the 0 V battery. This

current raises the pack’s terminal voltage above the pack revive threshold, causing the

packs internal pack protection switch to reconnect the Lithium-ion cell.

Note that a normal battery pack typically could stay in the low-battery precharge state for

several minutes. If a battery pack stays in low-battery precharge for longer than tPRECHG,

it may be defective.

8.5.2 Fast charge constant current state

The fast-charge constant current (CC) state occurs when the main-battery voltage is

greater than the precharge threshold and less than the battery regulation threshold

(VPRECHG.LB < VBATT < VCHGCV). In the fast-charge CC state the current into the battery is

less than or equal to IFC (excluding accuracy IFCACC).

Charge current may be less than IFC for any of the following reasons:

•The charger input is in input current limit

•The charger input voltage is low

•The system load is consuming adapter current. When the voltage drop between VBUS

and VSYS is below the VIN2SYS threshold, charging stops and charge current drops

down to 0 A.

Note: The system load always gets priority over the battery charge current.

Note that the system load always gets priority over the battery charge current.

The following events cause the state machine to exit this state:

•When the main battery voltage rises above VBATREG, the charger enters the next state

in the charging cycle: "Fast Charge (CV)".

•If the battery charger remains in this state for longer than tFC, the charger state

machine transitions to the "Timer Fault" state.

•If the watchdog timer is not serviced, the charger state machine transitions to the

"Watchdog Suspend" state.

The battery charger dissipates the most power in the fast-charge constant current state.

This power dissipation causes the internal die temperature to rise. If the die temperature

exceeds the threshold set by REGTEMP[1:0], IFC is reduced. This is covered in thermal

regulation section.

Table 47. Charger current control register

CHARGER CURRENT CONTROL REGISTER

ADDR: 0x8E

D7 D6 D5 D4 D3 D2 D1 D0

BITS: RESERVED PRECHGLB_THRESHOLD CHG_CC

POR: 00000000

ACCESS: —

The fast charge current is programmable via I2C using the bits shown below.

Table 48. Constant current charge settings

CHG_CC[4:0] setting IFC current (mA)

00000 100

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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CHG_CC[4:0] setting IFC current (mA)

00001 150

00010 200

00011 250

00100 300

00101 350

00110 400

00111 450

01000 500

01001 550

01010 600

01011 650

01100 700

01101 750

01110 800

01111 850

10000 900

10001 950

10010 1000

10011 1050 (Reserved)

10100 1100 (Reserved)

10101 1150 (Reserved)

10110 1200 (Reserved)

10111 1250 (Reserved)

11000 1300 (Reserved)

11001 1350 (Reserved)

11010 1400 (Reserved)

11011 1450 (Reserved)

11100 1500 (Reserved)

11101 1550 (Reserved)

11110 1600 (Reserved)

11111 1650 (Reserved)

To insure proper operation, the maximum CC current selected must be one setting below

input current limit (in charger normal mode).

In normal mode, when VSYS < VSYSMINLOOPx (VSYSMINLOOPx = VSYSMINx − 300 mV), digital

logic automatically controls maximum CC current (one setting lower than charger input

current limit ILIM setting). If 100 mA input current limit is selected, the charge current is

forced to 50 mA to allow enough current for VSYS.

The Charger Low-power mode (CLPM) is entered automatically when the 50 mA input

current limit setting, or lower, is selected and when VBATT > 2.8 V.

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8.5.3 Fast charge constant voltage state

The fast-charge constant voltage (CV) state occurs when the battery voltage rises to

VBATREG from the fast-charge CC state.

In the fast-charge CV state, the battery charger maintains VBATREG across the battery

and the charge current is less than or equal to IFC. Charger current decreases

exponentially in this state as the battery becomes fully charged.

The BATFET control circuitry may reduce the charge current for any of the following

reasons:

•The charger input is in input current limit

•The charger input voltage is low

•The system load is consuming adapter current. Note that the system load always gets

priority over the battery charge current.

The following events cause the state machine to exit this state:

•When the charger current is below IEOC for tSCIDG, the charger enters the next state in

the charging cycle: “End-of-Charge”.

•If the battery charger remains in this state for longer than tFC, the charger state

machine transitions to the “Timer Fault” state.

•If the watchdog timer is not serviced, the charger state machine transitions to the

“Watchdog Suspend” state.

Note: During the CC to CV transition, the charge current can be momentarily higher

than IFC. This current is safe and does not result in over charging the battery. After this

transition, the charge current decays and is less than or equal to IFC.

Table 49. Battery regulation voltage register

BATTERY REGULATION VOLTAGE REGISTER

ADDR: 0x8F

D7 D6 D5 D4 D3 D2 D1 D0

BITS: VSYSMIN CHGCV

POR: 00101011

ACCESS:

The CV setting is programmable via I2C using the bits below.

Table 50. CV settings

CHGCV[5:0] Output voltage (V)

000000 3.50

000001 3.50

000010 3.50

000011 3.50

000100 3.50

000101 3.50

000110 3.50

000111 3.50

001000 3.50

001001 3.52

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CHGCV[5:0] Output voltage (V)

001010 3.54

001011 3.56

001100 3.58

001101 3.60

001110 3.62

001111 3.64

010000 3.66

010001 3.68

010010 3.70

010011 3.72

010100 3.74

010101 3.76

010110 3.78

010111 3.80

011000 3.82

011001 3.84

011010 3.86

011011 3.88

011100 3.90

011101 3.92

011110 3.94

011111 3.96

100000 3.98

100001 4.00

100010 4.02

100011 4.04

100100 4.06

100101 4.08

100110 4.10

100111 4.12

101000 4.14

101001 4.16

101010 4.18

101011 [1] 4.20

101100 4.22

101101 4.24

101110 4.26

101111 4.28

110000 4.30

110001 4.32

110010 4.34

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CHGCV[5:0] Output voltage (V)

110011 4.36

110100 4.38

110101 4.40

110110 4.42

110111 4.44

111000 4.44

111001 4.44

111010 4.44

111011 4.44

111100 4.44

111101 4.44

111110 4.44

111111 4.44

[1] Default setting

Table 51. Charger timers register

CHARGER TIMERS REGISTER

ADDR: 0x8A

D7 D6 D5 D4 D3 D2 D1 D0

BITS: TPRECHG RESERVED EOCTIME FCHGTIME

POR: 00001010

ACCESS: —

The fast charge timer is programmable via I2C through the below bits:

Table 52. Fast charge timer settings

FCHGTIME[2:0] setting Fast charge timer duration (Hours)

000 Disable

001 2

010 4

011 6

100 8

101 10

110 12

111 14

Note that, the fast charge timer fault can occur in the fast charge mode, the system

draws current such that the charger state machine is technically in the "fast charge" state

but the battery is not really in "fast charge". This can happen if the current available from

the charger input is not sufficient to provide system load as well as charge the battery.

It is up to the processor to react to the timer fault accordingly. It can decide to re-start

charging (via CHG_OPER), or accept it as an actual timer fault.

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8.5.4 End-of-charge state

The end-of-charge state can only be entered from the fast-charge CV state when the

charger current decreases below IEOC for tSCIDG. After being in the top-off state for tSCIDG

+ tDB(EOC), an interrupt is generated, CHG_OK is set and CHG_SNS = 0x03. In the end-

of-charge state, the battery charger tries to maintain VCHGCV across the battery and

typically the charge current is less than or equal to IEOC.

The BATFET control circuitry may reduce the charge current lower than the battery may

otherwise consume for any of the following reasons:

•The charger input is in input current limit

•The charger input voltage is low

•The system load is consuming adapter current. Note that the system load always gets

priority over the battery charge current.

The following events cause the state machine to exit this state:

•After being in this state for the end-of-charge time (tEOC), the charger enters the next

state in the charging cycle: “DONE”.

•If VBATT < VBATREG – VRESTART, the charger goes back to the “FAST CHARGE (CC)”

state.

•If the watchdog timer is not serviced, the charger state machine transitions to the

“Watchdog Suspend” state.

Table 53. Charger EOC configuration register

CHARGER EOC CONFIGURATION REGISTER

ADDR: 0x8D

D7 D6 D5 D4 D3 D2 D1 D0

BITS: EOC_MODE IEOC EOC_EXIT FRC_

BATT_ISO

CHG_RESTART

POR: 01000001

ACCESS:

The EOC current value is programmable per the below table:

Table 54. EOC current thresholds

IEOC[2:0] setting IEOC current (mA)

000 5

001 10

010 20

011 30

100 50

101 Reserved

110 Reserved

111 Reserved

Table 55. Charger timers register

CHARGER TIMERS REGISTER

ADDR: 0x8A

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CHARGER TIMERS REGISTER

D7 D6 D5 D4 D3 D2 D1 D0

BITS: TPRECHG RESERVED EOCTIME FCHGTIME

POR: 00001010

ACCESS: —

The EOC State timer is programmable per below table:

Table 56. EOC state timer settings

EOCTIME[2:0] setting EOC timer duration (Minutes)

000 0 (16 seconds debounce)

001 10

010 20

011 30

100 40

101 50

110 60

111 70

8.5.5 Done state

The battery charger enters its done state after the charger has been in the end-of-

charge state for tEOC. After being in this state for tSCIDG, a CHG_I interrupt is generated,

CHG_OK is cleared and CHG_SNS = 0x04.

The following events cause the state machine to exit this state:

•If VBATT < VBATREG – VRESTART, the charger goes back to the "FAST CHARGE (CC)"

state

•If the watchdog timer is not serviced, the charger state machine transitions to the

"Watchdog Suspend" state

In the done state, the charge current into the battery (ICHG) is 0 A. In the done state,

the charger presents a very light load to the battery. If the system load presented to the

battery is low (<<100 µA), then a typical system can remain in the done state for many

days.

If left in the done state long enough, the battery voltage decays below the restart

threshold (VRESTART) and the charger state machine transitions back into the fast-

charge CC state. There is no soft start (di/dt limiting) during the done to fast-charge state

transition. In the DONE state, the BATFET is fully closed. The correct way to trigger

restart feature is to pull loading from VSYS, in order to discharge VBATT.

8.6 Battery supplement mode

The Battery supplement mode is a powerful feature of the PF1550 charger, allowing the

device to temporarily suspend charging, and draw supplemental current from the battery

to maintain power to the system when the load demands more current than the VBUS

supply can deliver. This permits users more flexibility when architecting their system. The

battery capacity can be chosen to handle periods of peak loading, which may be currents

higher than supported by the VBUS supply.

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If the system load current exceeds the VBUS input current limit, the VSYS supply current

is no longer be able to support the load demand and the VSYS output voltage decreases.

When VSYS falls below VBATT the PF1550 suspends charging and enters the Battery

supplement mode. In this mode, the battery provides current to support the VSYS load

demand.

If the load demand on VSYS now decreases, the VSYS output voltage recovers,

and begins to rise. When VSYS rises above VBATT, the PF1550 exits the Battery

supplement mode and resumes charging the battery in the CC charging phase.

When VBATT decreases lower than the restart threshold, the part enters CC state from

DONE. Then if the loading on VSYS decreases and VSYS > VBATT, charger starts to

charge from the CC state.

8.7 Power path features

8.7.1 VSYS regulation

In the case of a low battery, the LDO path regulates VSYS to either 3.5 V, 3.7 V or 4.3 V.

This allows the system to power up with a low battery while the battery gets charged. See

Table 46.

8.7.2 Input current limit

The default settings of the VBUSIN and CHG_OPER control bits are such that when a

charge source is applied to VBUSIN, the PF1550 turns its linear regulator on in LINEAR-

ON or CHARGE-ON (via OTP), and limits the charge current to 100 mA (via OTP).

See Section 12 "Register map" for the default values for specific registers/bits.

The input current limit works by monitoring the current being drawn from the input and

comparing it to the programmed current limit. The current limit should be set based on

the current-handling capability of the input adaptor. Generally, this limit is chosen to

optimally fulfill the system-power requirements while achieving a satisfactory charging

time for the batteries. If the adaptor current exceeds its output capability, the charger

responds by reducing the charger current, thereby keeping the current drawn from the

adaptor within its capability.

There is a precision current sense circuitry that monitors the input current whenever

internal INT_2P7 is asserted. The input current limit logic signal is used to reduce

quiescent current when the charger is not plugged in by turning off the current sense

amplifier. The input current limit should include current consumed by the charger block.

There is a low-power mode for the linear regulator where it consumes less than 2.5 mA

bias current at 25 °C. This is useful for the 10 mA to 50 mA input current limit settings.

The input current limit also includes a second control which is voltage based. When

it drops below the desired input, it generates an interrupt to decrease the fast-charge

current. This is further covered in input voltage regulation mode.

Table 57. VBUS input current limit register

VBUS INPUT CURRENT LIMIT REGISTER

ADDR: 0x94

D7 D6 D5 D4 D3 D2 D1 D0

BITS: VBUS_LIN_ILIM RESERVED

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VBUS INPUT CURRENT LIMIT REGISTER

POR: 01101000

ACCESS: R/W R/W R/W R/W R/W —

The table below shows valid input current limit settings.

Table 58. Input current limit settings

VBUS_LIN_ILIM[4:0] setting VBUS input current limit (mA)

00000 10

00001 15

00010 20

00011 25

00100 30

00101 35

00110 40

00111 45

01000 50

01001 100

01010 150

01011 200

01100 300

01101 400

01110 500

01111 600

10000 700

10001 800

10010 900

10011 1000

10100 1500

10101 to 11101 Reserved

11110 Reserved

11111 Reserved

8.7.3 Battery thermistor

Thermistor is not supported when there is no valid charger inserted. A bank of

comparators monitors the thermistor to provide battery temperature information for

the battery charger. The comparator thresholds are based on the recommended NTC

NCP15XH103F03RC (10 K) from Murata or equivalent. Each comparator has 3 #

hysteresis. There are I2C selections for the THOT and TCOLD temperature threshold.

8.7.4 BATFET soft start

When the battery is first plugged into the PF1550, BATFET features an internal soft-start

that prevent high inrush currents into the capacitors at the VSYS node.

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Note: This feature must be tested during lab validation for functionality. It is not required

to cover this in production as there are no critical pass/fail criteria for this feature.

8.8 Thermal

8.8.1 Thermal regulation

Thermal regulation maximizes the battery charge current while regulating the PF1550

junction temperature. The target charge current reduction is achieved with a digital

control loop. As shown in figure below, when the die temperature exceeds the value

programmed by REGTEMP[1:0], a thermal limiting circuit reduces the battery charger’s

target current.

Current (%)

80 °C

Junction temperature (°C)

95 °C

110 °C

125 °C

IFC = 100%

IFC = 50%

IFC = 25%

IFC = 12.5%

100 %

50 %

25 %

12.5 %

100 mA

aaa-025043

Figure 18. Thermal regulation

Table 59. Thermal regulation

REGTEMP[1:0] 50 % CC Thermal

regulation set

point (TJREG0)

25 % CC Thermal

regulation set

point (TJREG1)

12.5 % CC

Thermal

regulation set

point (TJREG2)

100 mA CC

Thermal

regulation set

point (TJREG3)

00 80 °C 95 °C 110 °C 125 °C

01 95 °C 110 °C N/A 125 °C

10 110 °C N/A N/A 125 °C

11 N/A N/A N/A 125 °C

As shown in figure below, a hysteresis mechanism is implemented.

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Current (%)

80 °C

Junction temperature (°C)

95 °C

110 °C 125 °C

75 °C

90 °C

105 °C 120 °C

IFC = 100%

IFC = 50%

IFC = 25%

IFC = 12.5%

100 %

50 %

25 %

12.5 %

100 mA

aaa-025044

Figure 19. Thermal regulation (Current versus Temp, example with REGTEMP[1:0] = 00 and

hysteresis

When thermal regulation changes state, a THM_I interrupt is generated. This is to allow

the system’s microprocessor time to read the status of the thermal regulation loop via the

TREG_SNS status bit.

This diagram below shows an example of the thermal regulation over time. The green

arrows represent when the CHG_I interrupt is generated.

Current (%)

80 °C

Time (s)

75 °C

25 °C

IFC = 100%

IFC = 50%

aaa-025045

Figure 20. Thermal regulation (Current, Temp versus Time, example with REGTEMP[1:0] =

00 and hysteresis

The thermal regulation does not affect the CHG_OK bit (only information contained within

CHG_SNS affects CHG_OK).

8.8.2 Thermal foldback

The thermal foldback function reduces max. charging current which goes into the battery

when the charger junction temperature (TJREGx) reaches a pre-defined temperature set

by REGTEMP[1:0]. Note that the thermal foldback loop being active is not considered to

be an abnormal condition.

After the temperature reaches TJREG0, the charging current will be reduced to 50 % of the

final CC charging current value.

After the charger temperature rises above TJREG0, if the charger temperature falls back

below TJREG0 − 5 °C, charging current reverts back to 100 % of the final CC charging

current value.

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If the charger temperature rises and reaches TJREG1 but below 125 °C, charging current

is reduced to 25 % of the final CC charging current value.

After the charger temperature rises above TJREG1, if the charger temperature falls back

below TJREG1 − 5 °C, charging current reverts back to 50 % of the final CC charging

current value.

If the charger temperature rises and reaches TJREG2 but below 125 °C, charging current

is reduced to 12.5 % of the final CC charging current value.

After the charger temperature rises above TJREG2, if the charger temperature falls back

below TJREG2 − 5 °C, charging current reverts back to 25 % of the final CC charging

current value.

If the charger temperature reaches 125 °C, charging current is reduced to 100 mA.

After the charger temperature rises above 125 °C, if the charger temperature falls back

below 120 °C, charging current reverses back to 12.5 % of the final CC charging current

value.

The thermal foldback function is not available for LPM.

At charger junction temperature above TJREGx, if the charger current is already set to

100 mA, the thermal foldback function keeps the current 100 mA. The final charging

current min. out of the fold back function is clamped at 100 mA.

Table 60. Temperature regulation control register

TEMPERATURE REGULATION CONTROL REGISTER

ADDR: 0x92

D7 D6 D5 D4 D3 D2 D1 D0

BITS: TEMP_FB_EN RESERVED THM_HOT THM_COLD REGTEMP THM_CONFIG

POR: 00000101

ACCESS: —

The table below shows the different thermal regulation set point:

Table 61. Thermal regulation settings

REGTEMP[1:0] setting Thermal regulation set point (°C)

00 80

01 95

10 110

11 Reserved

8.8.3 Input voltage regulation mode

An input-voltage regulation loop allows the charger to be well behaved when it is

attached to a poor quality power source. The loop improves performance with relatively

high resistance charge sources that exist when long cables are used or devices are

charged with non-compliant USB hub configurations. Additionally, this input-voltage

regulation loop improves performance with current limited adapters. If the input current

limit is programmed above the current limit threshold of given adapter, the input voltage

loop allows regulation at the current limit of the adapter. Finally, the input-voltage

regulation loop allows the charger to perform well with adapters that have poor transient

load response times.

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The input-voltage regulation loop automatically reduces the input current limit in order to

keep the input voltage at VVBUS_DPM_REG. Once VBUS drops to the 4.5 V threshold (this

threshold itself is selectable via the VBUS_DPM_REG[2:0] bits), the charging current

is scaled back and this brings back the VBUS voltage higher. The Dynamic Power

Management (DPM) loop then regulates the charging current (indirectly by reducing

input current limit) dynamically to maintain VBUS at the DPM threshold. An interrupt is

generated after the debounce time to notify the processor of the DPM event.

In the figure below, VBUS starts to drop as the charging current increases.

aaa-023886

4.5 V

4.3 V

VUVLO (falling)

Charge

current

VBUS

voltage

VBUS_DPM

interrupt

INTB

tINTDEB

VBUS_DPM

threshold (falling)

VBUS_DPM_STOP

threshold

Figure 21. Response to input voltage droop during charging

The next figure below describes a more stringent event.

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4.5 V

4.3 V

Charge

current

CC_Charge

current incremented

1 LSB

VBUS

voltage

VBUS_DPM

threshold (falling)

VBUS_DPM_STOP

threshold

2.0 µs

10 ms

200 mV

100 mA

aaa-025041

Figure 22. DPM function

There is a second comparator in the DPM loop which is set 200 mV below the

VBUS_DPM_REG threshold. As seen in the second figure above, if the VBUS voltage

continues to drop and hits the threshold of the second comparator, the charging current

is immediately brought to the 100 mA setting to recover from the input voltage droop. At

this point, the VBUS voltage should recover (assuming current drawn from VSYS is not

causing the VBUS collapse).

Now, the charging current is stepped up slowly (every 10 ms) to arrive at the maximum

value that allows regulation of VBUS to or slightly above the DPM threshold. At every

incrementing step, the digital logic monitors if the VBUS voltage is above the 4.5 V

comparator. The incrementing continues only if it is.

Table 62. VBUS linear dynamic input voltage register

VBUS LINEAR DYNAMIC INPUT VOLTAGE REGISTER

ADDR: 0x95

D7 D6 D5 D4 D3 D2 D1 D0

BITS: RESERVED VIN_DPM_STOP PRECHGDBATT_THRESHOLD VBUS_DPM_REG_VOLTAGE

POR: 00000000

ACCESS: —

The input DPM voltage regulation set point is selected by writing to the VBUS_REG

Table 63. Input voltage regulation thresholds

VBUS_REG[2:0] setting VBUS DPM REG voltage setting (V)

000 3.9

001 4.0

010 4.1

011 4.2

100 4.3

101 4.4

110 4.5

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VBUS_REG[2:0] setting VBUS DPM REG voltage setting (V)

111 4.6

8.8.4 JEITA thermal control

The PF1550 includes a temperature control function that conforms to the

recommendations specified in the Japan Electronics and Information Technology

Industries Association (JEITA) guidelines for improving the safety when charging of

lithium-ion batteries.

The JEITA specification establishes five temperature zones, COLD, COOL, NORMAL,

WARM, and HOT, with four temperature thresholds partitioning the zones. Battery

temperature is monitored using a NTC thermistor, in close proximity of the cell, and the

charger is carefully controlled as shown in the following table:

Table 64. JEITA thermal control

Zone JEITA control function

COLD Charging inhibited

COOL Charger CC current and CV voltage adjusted

NORMAL No JEITA control

WARM Charger CC current and CV voltage adjusted

HOT Charging inhibited

JEITA Thermal Control is enabled by selecting bits THM_CNFG[1:0] in the Temperature

Regulation and Control Register 0x92.

Table 65. Temperature regulation control register

TEMPERATURE REGULATION CONTROL REGISTER

ADDR: 0x92

D7 D6 D5 D4 D3 D2 D1 D0

BITS: TEMP_FB_EN RESERVED THM_HOT THM_COLD REGTEMP THM_CONFIG

POR: 00000101

ACCESS: —

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COOL

CV voltage

reduced NORMAL

CV charge voltage WARM

CV voltage

reduced

HOT

Charge

inhibited

COLD

Charge

inhibited

0 °C

Cold

threshold

REG 0x92: D[4]

15 °C

Cool

threshold

REG 0x9A: D[1]

45 °C

Warm

threshold

REG 0x9A: D[0]

60 °C

Hot

threshold

REG 0x92: D[5]

CV charge

adjustment

CV charge voltage

200 mV

60 mV

–60 mV

4.20 V

4.14 V

CV charge

adjustment

–60 mV

4.14 V

Battery temp (°C)

CV charge voltage (V)

OFF

100 mV

160 mV

t1t3t4

t3t4

REG 0x9A: D[3:2]

aaa-023888

0 °C

Cold

threshold

REG 0x92: D[4]

15 °C

Cool

threshold

REG 0x9A: D[1]

45 °C

Warm

threshold

REG 0x9A: D[0]

60 °C

Hot

threshold

REG 0x92: D[5]

CC charge

adjustment

CC charge current

100 %

25 %

–75 %

500 mA

125 mA

CC charge

adjustment

–75 %

125 mA

Battery temp (°C)

CC charge current (mA)

OFF

50 %

75 %

REG_0x9A: D[5:4]

COOL

CC current

reduced NORMAL

CC charge current WARM

CC current

reduced

HOT

Charge

inhibited

COLD

Charge

inhibited

Figure 23. CC charge current and CV charge voltage adjustment

When the THM_CNFG[1:0] is set to 0x02, the charging current and CV voltage are

adjusted based on CC_ADJ[1:0] and CV_ADJ[1:0] respectively whenever TCOOL and

TWARM thresholds are crossed.

When the THM_CNFG[1:0] is set to 0x03, and when the battery temperature rises

above warm temp or goes below TCOOL, only the charging current is changed based on

CC_ADJ[1:0]. CV voltage is not changed.

This feature can be disable if THM_CNFG[1:0] is set to 0x01.

During THM_CNFG[1:0] =0x01, JEITA compliance can still be achieved but through

software.

The PF1550 assists in this implementation by providing an interrupt at the TCOOL and

TWARM threshold when THM_CNFG[1:0] = 0x01.

The charger parameters must not be locked by OTP to use this software function.

If the thermistor functionality is not needed, THM_CNFG[1:0] can be set 0x00.

Table 66. JEITA temperature control register

JEITA TEMPERATURE CONTROL REGISTER

ADDR: 0x9A

D7 D6 D5 D4 D3 D2 D1 D0

BITS: RESERVED CC_ADJ CV_ADJ THM_COOL THM_WARM

POR: 00000000

ACCESS:

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CV_ADJ[1:0] has four settings subtraction off of CHGCV[5:0] settings, refer to register

map and TBBOTP:

Table 67. CV voltage adjustment settings

CV_ADJ[1:0] CV voltage adjustment (mV)

00 60

01 100

10 160

11 200

CC_ADJ[1:0] has four settings subtraction off of CHG_CC settings, see register map and

TBBOTP:

Table 68. CC current adjustment settings

CC_ADJ[1:0] CC current adjustment (%)

00 25 %

01 50 %

10 75 %

11 100 %

THM_HOT[0] THM_HOT setting (#)

0 60

1 55

THM_COLD[0] THM_COLD setting (#)

0 0

1 -10

8.9 Fault states

8.9.1 Timer fault state

The battery charger provides both a charge timer and a watchdog timer to ensure safe

charging.

The charge timer prevents the battery from charging indefinitely. The time that the

charger is allowed to remain in its each of its pre-qualification states is tPRECHG.

The time that the charger is allowed to remain in the fast-charge CC and CV states is tFC

which is programmable with FCHGTIME.

Finally, the time that the charger is in the end-of-charge state is tEOC which is

programmable with EOCTIME bits. Upon entering the timer fault state, a CHG_I interrupt

is generated without a delay, CHG_OK is cleared and CHG_SNS = 0x06.

In the timer fault state, the charger is off. The charger can exit the timer fault state by

programming the charger to be off and then programming it to be on again through the

CHG_OPER bits. Alternatively, the charger input can be removed and re-inserted to exit

the timer fault state.

VSYS should continue to regulate while in the Timer fault state.

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8.9.2 Watchdog timer state

The battery charger provides both a charge timer and a watchdog timer to ensure safe

charging. The watchdog timer protects the battery from charging indefinitely in the event

that the host hangs or otherwise cannot communicate correctly.

The watchdog timer is disabled by default with WDTEN = 0. To use the watchdog timer

feature, enable the feature by setting WDTEN. While enabled, the system controller must

reset the watchdog timer within the timer period (tWD) for the charger to operate normally.

Reset the watchdog timer by programming WDTCLR = 0x01. As long as WDTEN = 1, the

timer continues to run and the processor continues to clear the register before the timer

expires.

The system processor clears the WDTEN bit to stop the timer.

If the watchdog timer expires while the charger is in precharge mode, fast charge CC

or CV, end-of-charge, done, or timer fault, the charging stops, a CHG_I interrupt is

generated without a delay, CHG_OK is cleared, and CHG_SNS = 0x0B and indicates

that the charger is off because the watchdog timer has expired.

Once the watchdog timer has expired, the charger is restarted by programming

WDTCLR=0x01. The VSYS node is supported by the battery and/or the adapter through

the Linear regulator while the watchdog timer is expired.

8.9.3 Thermal shutdown state

The thermal shutdown state occurs when the battery charger is in any state and the

junction temperature (TJ) exceeds the device’s thermal shutdown threshold (TSHDN),

typical 140 °C.

When TJ is close to TSHDN the charger folds back the charging current to 0 A, so the

charger is effectively off. Upon entering this state, CHG_I interrupt is generated without

a delay, CHG_OK is cleared. In the thermal shutdown state, the charger is off and timers

are suspended.

CHG_SNS = 0x0A and CHG_OK = 0 in the thermal shutdown state. The charger

exits the temperature suspend state and returns to the state it came from once the die

temperature has cooled. The timers resume once the charger exits this state. VSYS

continues to regulate while in the thermal shutdown state.

8.9.4 Battery overvoltage state

A battery overvoltage fault occurs in any state when the battery voltage exceeds to

VBATOV threshold.

In this state, BAT_SNS = 0x09 and BAT_OK = 0. A BATT_I interrupt is generated in

this state. In the event of a battery overvoltage state, the BATFET is opened and VSYS

is regulated using the linear path. Once the battery overvoltage condition clears, the

charger exits the battery overvoltage state and returns to the state it came from.

8.9.5 Charger fault priority

Some of the charger fault states occurs at the same time. For example, battery

overvoltage and thermal shutdown occurs at the same time. In this section, which failure

states take priority is discussed.

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In any given state, non-recoverable faults such as battery overcurrent timer fault take the

highest priority. Recoverable faults such as a thermistor suspend, or battery overvoltage

take lower priority.

8.9.6 Battery overcurrent limit

The VBATT to VSYS detector (BATFET) generates an overcurrent (OVRC) and provides

the signal to the PMIC on/off controller.

This feature protects the battery and the system from potential damage due to excessive

battery discharge current. Excessive battery discharge current may occur for several

reasons such as exposure to moisture, a software problem, a device failure, or

mechanical failure that causes a short-circuit.

The battery overcurrent protection feature is enabled with BATFET_OC[1:0] bit.

Disabling this feature reduces the main battery current consumption. When the battery

current to system exceeds the programmed overcurrent threshold for at least tBOVCRI,

a BAT2SOC_I interrupt is generated and BATTOC_SNS bit reports an overcurrent

condition.

If the overcurrent persists for tBOVCR, the VBATT to VSYS MOSFET is disabled or kept

alive depending on the BOVRC_DISBATFET OTP bit. Typically, when the system’s

processor detects this overcurrent interrupt, it executes a housekeeping routine that tries

to mitigate the overcurrent situation. There is an OTP option (via BOVRC_DISBATFET

bit) to either disable the BATFET after completion of housekeeping routine or remain on.

Battery

overcurrent

Battery

overcurrent

interrupt

VSYS VSYS shuts down

tBOVCRI = 3.0 ms

aaa-023885

tBOVCR = 16 ms

Figure 24. Response to battery overcurrent

The table below shows the different overcurrent threshold settings:

Table 69. Battery overcurrent thresholds

BATFET_OC[1:0] setting VBATT to VSYS overcurrent threshold (A)

00 Disabled

01 2.2

10 2.8

11 3.2

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8.10 LED indicator

CHGB is a 6.0 mA LED current sink with programmable blink timing. Blink period and

on-time are programmable with 2-bits. The LED has indicator depending on the charger

state as shown in the LED modes table. Blink frequency is programmable for 0.5 Hz, 1.0

Hz, 8.0 Hz or 256 Hz.. Blink duration is programmable from 0/32 duty cycle to 32/32 duty

cycle in 1/32 increments.

The LED_CFG bit allows the LED’s to operate in two modes as shown in the table

below. With LED_CFG=0 the LED’s behave as follows: charging (on), fault (flashing),

and charge complete (off). When LED_CFG = 1, the LED’s have the following behavior,

charging (flashing), fault (on), and charge complete (off). The LED’s are activated

automatically when charging is started and remain under control of the state machine.

Software can take control over the charge LED’s by setting the LEDOVRD = 1. When

LEDOVRD = 1 the LEDs are totally controlled by software, therefore the state machine

no longer has control. With LEDOVRD = 0 software cannot force the LED’s on but can

still set the current.

The charging LED drivers include ramp up and ramp down patterns implemented in

hardware. The ramp itself is generated by increasing or decreasing the PWM duty cycle

with a 1/32 step every 1/64 seconds. The ramp time is therefore a function of the initial

set PWM cycle and the final PWM cycle. As an example, starting from 0/32 and going to

32/32 takes 500 ms whereas going to from 8/32 to 16/32 takes 125 ms.

Note that the ramp function is executed upon every change in PWM cycle setting.

If a PWM change is programmed via I2C when LED_RAMP = 0, then the change is

immediate rather than spread out over a PWM sweep. In addition, programmable blink

rates are provided. Blinking is obtained by lowering the PWM repetition rate of each of

the drivers through LED_FREQ[1:0] while the on period is determined by the duty cycle

setting. To avoid high frequency spur coupling in the application, the switching edges of

the output drivers are softened.

Table 70. LED modes

Condition LED_CFG = 1 LED_CFG = 0 (default) Current (mA)

Charger off Off Off 6

Charging Flashing 1.0 Hz

50 % duty cycle

On steady

100 % duty cycle

Charging fault On steady

100 % duty cycle

Flashing 1.0 Hz

50 % duty cycle

Charge complete Off Off 6

Table 71. LED enable conditions

LED_EN CHGB LEDOVRD

0 (default) Auto 0

1 On 1

0 Off 1

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Table 72. LED frequency setting

LED_FREQ[1:0] Frequency Units

00 (default) 1 Hz

01 0.5 Hz

10 256 Hz

11 8 Hz

9 Control and interface signals

The PF1550 PMIC is fully programmable via the I2C interface. Additional communication

is provided by direct logic interfacing including interrupt and reset pins as well as pins for

power buttons.

9.1 PWRON

PWRON is an input signal to the IC that acts as an enable signal for the voltage

regulators in the PF1550.

The PWRON pin can be configured as either a level sensitive input (OTP_PWRON_CFG

= 0), or as an edge sensitive input (OTP_PWRON_CFG = 1).

As a level sensitive input, an active high signal turns on the part and an active low signal

turns off the part, or puts it into Sleep mode.

As an edge sensitive input, such as when connected to a mechanical switch, a falling

edge will turn on the part and if the switch is held low for greater than or equal to 4.0

seconds, the part turns off or enters Sleep mode.

Table 73. PWRON pin OTP configuration options

OTP_PWRON_CFG Mode

0 PWRON pin HIGH = ON

PWRON pin LOW = OFF or Sleep mode

1 PWRON pin pulled LOW momentarily = ON

PWRON pin LOW for 4.0 seconds = OFF or Sleep mode

Table 74. PWRON pin logic level

Pin name Parameter Load condition Min. Max. Unit

VIL — 0.0 0.4 VPWRON

VIH — 1.4 3.6 V

When OTP_PWRON_CFG = 1, PWRON pin pulled low momentarily takes the system

from REGS_DISABLE/SLEEP to RUN mode. There is no effect if PWRON is pulled low

momentarily while in RUN or STANDBY modes. Only an interrupt is generated.

PWRON pin low for 4.0 seconds with PWRONRSTEN bit = 1: Enters REGS_DISABLE or

Sleep mode.

See Section 10 "PF1550 state machine" for detailed description.

In this configuration, the PWRON input can be a mechanical switch de-bounced through

a programmable de-bouncer, PWRONDBNC[1:0], to avoid a response to a very short key

press. The interrupt is generated for both the falling and the rising edge of the PWRON

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pin. By default, a 31.25 ms interrupt debounce is applied to both falling and rising

edges. The falling edge debounce timing can be extended with PWRONDBNC[1:0]. The

interrupt is cleared by software, or when cycling through the REGS_DISABLE mode.

Table 75. PWRONDBNC settings

Bits State Turn on

debounce (ms)

Falling edge INT

debounce (ms)

Rising edge INT

debounce (ms)

00 31.25 31.25 31.25

01 31.25 31.25 31.25

10 125 125 31.25

PWRONDBNC[1:0]

11 750 750 31.25

9.2 STANDBY

STANDBY is an input signal to the IC. When it is asserted the part enters standby mode

and when deasserted, the part exits standby mode. STANDBY can be configured as

active high or active low using the STANDBYINV bit.

Table 76. Standby pin polarity control

STANDBY (pin) STANDBYINV (I2C bit) STANDBY control

0 0 Not in Standby mode

0 1 In Standby mode

1 0 In Standby mode

1 1 Not in Standby mode

Table 77. STANDBY pin logic level

Pin name Parameter Load condition Min. Max. Unit

VIL — 0 0.2 * VSNVS VSTANDBY

VIH — 0.8 * VSNVS 3.6 V

Since STANDBY pin activity is driven asynchronously to the system, a finite time

is required for the internal logic to qualify and respond to the pin level changes. A

programmable delay is provided to hold off the system response to a Standby event. This

allows the processor and peripherals some time after a standby instruction has been

received to terminate processes to facilitate seamless entering into Standby mode. When

enabled (STANDBYDLY = 01, 10, or 11), STANDBYDLY delays the Standby initiated

response for the entire IC, until the STBYDLY counter expires. An allowance should be

made for three additional 32 kHz cycles required to synchronize the Standby event.

9.3 RESETBMCU

RESETBMCU is an open-drain, active low output configurable via OTP for two modes of

operation.

In its default mode, it is deasserted at the end of the start-up sequence. In this mode, the

signal can be used to bring the processor out of reset (POR), or as an indicator that all

supplies have been enabled; it is only asserted during a turn off event.

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When configured for its fault mode, RESETBMCU is deasserted after the startup

sequence is completed only if no faults occurred during start up. At any time, if a fault

occurs and persists for 1.8 ms typically, RESETBMCU is asserted low.

The PF1550 is turned off if the fault persists for more than 100 ms typically. The PWRON

signal restarts the part, though if the fault persists, the sequence described above is

repeated. To enter the fault mode, set bit OTP_PWRGD_EN to 1.

The time from the last regulator in the start-up sequence to when RESETBMCU is

deasserted is programmable between 2.0 ms and 1024 ms via OTP_POR_DLY[2:0] bits.

9.4 INTB

INTB is an open-drain, active low output. It is asserted when any interrupt occurs,

provided that the interrupt is unmasked. INTB is deasserted after the fault interrupt is

cleared by software, which requires writing a “1” to the interrupt bit.

Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result,

when a masked interrupt bit goes high, the INTB pin does not go low. A masked interrupt

can still be read from the interrupt status register. This gives the processor the option of

polling for status from the IC.

The IC powers up with all interrupts masked, so the processor must initially poll the

device to determine if any interrupts are active. Alternatively, the processor can unmask

the interrupt bits of interest. If a masked interrupt bit was already high, the INTB pin goes

low after unmasking. The sense registers contain status and input sense bits so the

system processor can poll the current state of interrupt sources. They are read only, and

not latched or clearable.

9.5 WDI

WDI is an input signal to the IC. It is typically connected to the watchdog output of the

processor. When the WDI pin is pulled low, the PMIC enters the “REGS_DISABLE”

mode where all the regulators are turned off. The WDI acts as a hard reset input from the

processor.

During PMIC startup (REGS_DISABLE to RUN mode), the WDI pin is masked till

RESETBMCU is deasserted.

Table 78. WDI pin logic level

Pin name Parameter Load condition Min. Max. Unit

VIL — 0 0.2 * VDDIO VWDI

VIH — 0.8 * VDDIO 3.6 V

9.6 ONKEY

ONKEY is an input pin to the IC and is typically connected to a push-button switch. The

ONKEY pin is pulled high when the switch is depressed, and is pulled low when the

switch is pressed.

Pressing the switch generates interrupts which the processor uses to initiate PMIC

state transitions. Pressing the ONKEY for longer than the delay programmed

by OTP_TGRESET[1:0] (ranges from 4.0 s to 16 s), forces the PMIC into the

REGS_DISABLE state.

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Table 79. ONKEY pin logic level

Pin name Parameter Load condition Min. Max. Unit

VIL — 0 0.2 * VBATT VONKEY

VIH — 0.8 * VBATT 3.6 V

Table 80. ONKEYDBNC settings

Bits State Turn On

Debounce (ms)

Falling Edge INT

Debounce (ms)

Rising Edge INT

Debounce (ms)

00 31.25 31.25 31.25

01 31.25 31.25 31.25

10 125 125 31.25

ONKEYDBNC[1:0]

11 750 750 31.25

The ONKEY input can be a mechanical switch debounced through a programmable

debouncer, ONKEYDBNC[1:0], to avoid a response to a very short (unintentional) key

press. The interrupt is generated during the rising edge of the ONKEY pin.

The falling edge debounce timing can be extended with ONKEYDBNC[1:0] as

defined Table 80. The interrupt is cleared by software, or when cycling through the

REGS_DISABLE mode.

See Section 12 "Register map" for detailed description of the ONKEY interrupt registers.

9.7 Control interface I2C block description

The PF1550 contains an I2C interface port which allows access by a processor, or

any I2C master, to the register set. Via these registers, the resources of the IC can be

controlled. The registers also provide status information about how the IC is operating.

The SCL and SDA lines should be routed away from noisy signals and planes to

minimize noise pick up. To prevent reflections in the SCL and SDA traces from creating

false pulses, the rise and fall times of the SCL and SDA signals must be greater than

20 ns. This can be accomplished by reducing the drive strength of the I2C master via

software.

9.7.1 I2C device ID

I2C interface protocol requires a device ID for addressing the target IC on a multi-device

bus. The PF1550 I2C device address is 0x08.

9.7.2 I2C operation

The I2C mode of the interface is implemented generally following the fast mode definition

which supports up to 400 kbits/s operation (exceptions to the standard are noted to be

7-bit only addressing and no support for general call addressing). Timing diagrams,

electrical specifications, and further details can be found in the I2C specification, which is

available for download at:

http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf

I2C read operations are also performed in byte increments separated by an ACK. Read

operations also begin with the MSB and each byte is sent out unless a STOP command

or NACK is received prior to completion.

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The following examples show how to write and read data to and from the IC. The host

initiates and terminates all communication. The host sends a master command packet

after driving the start condition. The device responds to the host if the master command

packet contains the corresponding slave address. In the following examples, the device

is shown always responding with an ACK to transmissions from the host. If at any time

a NACK is received, the host should terminate the current transaction and retry the

transaction.

SDA

I2C write example

I2C read example

S 0

device address register address master driven data

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

START condition STOP

condition

host can also drive

another START

instead of STOP

PAA DATA (byte 0)A

R/W

SDA S 0

device address device addressregister address PMIC driven data

acknowledge

from slave

acknowledge

from slave

no acknowledge

from slave

START condition

START condition STOP

condition

host can also drive

another START

instead of STOP

PNAAA

R/W

acknowledge

from slave

R/W

aaa-026501

Figure 25. I2C sequence

10 PF1550 state machine

The PMIC part of the PF1550 can operate in a number of states as shown in Figure 26.

The states can be split into two categories:

1. “System On” that includes the RUN, STANDBY and SLEEP modes

2. “System Off” that includes the REGS_DISABLE, CORE_OFF and SHIP modes

STANDBY RUN

SLEEP/LPSR

System running, VCOREDIG ON

REGS_DISABLE

(VSNVS from VSYS

or LICELL)

(MBATT ON,

VCOREDIG ON)

SHIP

(MBATT OFF,

VCOREDIG OFF,

VSNVS OFF)

CORE_OFF

VSNVS_ONLY

(VSNVS from VSYS

or LICELL)

(MBATT ON,

VCOREDIG OFF)

aaa-023889

Figure 26. PMIC state machine

In the “System On” modes, some or all of the PMIC regulators are powered and in

general the system processor is powered.

In the “System Off” modes, all (or all regulators except VSNVS) are powered off. In

general the system processor is powered off during these states. In the REGS_DISABLE

and CORE_OFF modes, the VSNVS supply remains enabled keeping the system RTC

running.

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The only way to transition from “System Off” to “System On” and vice versa is through

the REGS_DISABLE mode. From the REGS_DISABLE mode, the only exit into a

“System On” state is into the “Run” mode. Transition from the REGS_DISABLE mode to

the Run mode requires a Turn On event. See Section 10.3 "Turn on events".

Transition from any of the “System On” modes to the REGS_DISABLE state is allowed.

This transition is referred to as a Turn Off event. See Section 10.4 "Turn off events".

10.1 System ON states

10.1.1 Run state

In this state, the PMIC regulators are enabled and the system is powered up.

RESETBMCU is de-asserted in this state.

This mode can be entered in several ways:

1. From REGS_DISABLE through a Turn On Event: During this transition, the PMIC

regulators are powered up as per their programmed start-up sequence. After all the

regulators are powered, the RESETBMCU pin is de-asserted.

2. From STANDBY by using the STANDBY pin

3. From SLEEP mode by using the PWRON pin: Typically, some of the regulators are

turned off in the SLEEP mode compared to the RUN mode. In the SLEEP mode,

some of the buck regulator output voltages are set lower than those in the RUN

mode. While transitioning from the SLEEP to the RUN mode, regulators that were

turned off in the SLEEP mode are turned back on in the RUN mode following the

same sequence as the programmed OTP sequence. Output voltage transitions during

transition from the SLEEP to the RUN mode also occurs at the same OTP sequence

time slot. RESETBMCU is de-asserted through this state transition.

10.1.2 STANDBY state

This state is entered by controlling the logic level of the STANDBY pin. It can be entered

only from the RUN mode.

The STANDBY pin polarity is programmable through the STANDBYINV I2C bit. By

default, STANDBYINV = 0 and a logic high on the STANDBY pin moves the state

machine from the RUN state to the STANDBY state. When STANDBYINV = 1, a logic

low moves the state machine from the RUN state to the STANDBY state.

Regulator output voltage may be changed, or regulator outputs could be disabled while

entering the STANDBY state and vice versa.

For details on the power-down sequence, see Section 10.7 "Regulator power-down

sequencer". While exiting STANDBY state into the RUN mode, regulator output voltage

changes and regulator enables follow the power-up sequence.

It is possible to exit STANDBY state and enter the SLEEP state. SLEEP state is

generally a lower power system state compared to the STANDBY state. Exiting

STANDBY into the SLEEP state follows the power-down sequence.

RESETBMCU is de-asserted in the STANDBY state.

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10.1.3 SLEEP state

This state is entered from either the RUN state or the STANDBY state by controlling

the PWRON pin. The exact condition required for this transition depends on the OTP

configuration of the PWRON pin. For details see Section 9.1 "PWRON".

The power-down sequence is followed while entering this state and the power-up

sequence is followed while exiting this state into the RUN state.

RESETBMCU is de-asserted in the SLEEP state.

10.2 System OFF states

RESETBMCU is asserted (low) in all the System Off states.

10.2.1 REGS_DISABLE

This state can be considered the ‘home state’ for the state machine. In this state, the

state machine waits for appropriate commands to proceed to other states.

REGS_DISABLE can be entered from one of the “System On” state through a turn off

event.

REGS_DISABLE can be entered from the CORE_OFF and SHIP mode by a charger

attach event.

In the REGS_DISABLE state, the PMIC core circuitry is active. VSNVS is a best-of-

supply output of VSYS and LICELL.

10.2.2 CORE_OFF

This state is entered in two ways:

1. From the REGS_DISABLE mode by pressing and holding the ON_KEY button low >

Tgreset

2. From the REGS_DISABLE mode if the GOTO_CORE_OFF bit is set

This state cannot be entered if a charger is plugged in.

In this state, the internal core of the PMIC is turned off to reduce quiescent current.

VSNVS is the only regulator that is supplied to external loads.

10.2.3 SHIP

In this mode, the MBATT switch between VSYS and VBATT is opened. All the PMIC

supplies including VSNVS are turned off.

The SHIP mode is entered if the GOTO_SHIP bit is set in the REGS_DISABLE state.

The only way to exit from this mode is by a charger attach event. The state machine exits

to the REGS_DISABLE state when this happens. A battery re-attach can also be used to

exit SHIP mode.

10.3 Turn on events

A turn on event takes the PMIC from the REGS_DISABLE state to the RUN state

(transition H in Figure 26).

The turn on events are:

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1. PWRON logic high with PWRON_CFG = 0

2. PWRON H -> L with PWRON_CFG = 1

VSYS > UVDETrising and TJ < TSHDN_fall are preconditions for a turn on event to occur.

The turn on is said to be complete after the RESETBMCU pin is deasserted. The WDI pin

is masked till the RESETBMCU pin is deasserted.

10.4 Turn off events

A turn off event takes the PMIC state machine from one of the “System On” states (RUN,

STANDBY or SLEEP) to the REGS_DISABLE state. The power-down sequence is

followed during all of the turn off events.

The turn off events are:

1. Thermal Shutdown (TJ > TSHDN_rise)

2. PWRON logic low with OTP_PWRON_CFG = 0

3. PWRON low > 4.0 s with OTP_PWRON_CFG = 1 && PWRONRSTEN = 1

4. WDI = 0. This occurs when the processor watchdog expires and pulls the WDI pin low

to create a hard reset.

5. ON_KEY pressed low > Tgreset && ON_KEY_RST_EN = 1. This facilitates creating a

hard reset when pressing the ON_KEY button without processor intervention.

6. GOTO_SHIP = 1. This is used to initiate the device to go into the SHIP mode. When

GOTO_SHIP bit is set to 1, the state machine proceeds from one of the “System On”

states to the REGS_DISABLE mode to the SHIP mode.

10.5 State diagram and transition conditions

Table 81. State transition table

Transiti

Description PWRON_CFG = 0 (Level sensitive) PWRON_CFG = 1 (Edge sensitive)

A Standby to Run (STANDBY pin = 0 && STANDBYINV bit = 0)

(STANDBY pin = 1 && STANDBYINV bit = 1)

(STANDBY pin = 0 && STANDBYINV bit = 0)

(STANDBY pin = 1 && STANDBYINV bit = 1)

B Run to Standby (STANDBY pin = 1 && STANDBYINV bit = 0)

(STANDBY pin = 0 && STANDBYINV bit = 1)

(STANDBY pin = 1 && STANDBYINV bit = 0)

(STANDBY pin = 0 && STANDBYINV bit = 1)

C Standby to Sleep (PWRON = 0) && (Any SWxOMODE = 1 || Any

LDOxOMODE = 1)

(PWRON High to Low and PWRON = 0 > 4s) &&

(PWRONRSTEN = 1) && (Any SWxOMODE = 1 || Any

LDOxOMODE = 1)

E Sleep to Run PWRON = 1 PWRON High to Low to High [1]

F Run to Sleep (PWRON = 0) && (Any SWxOMODE = 1 || Any

LDOxOMODE = 1)

(PWRON High to Low and PWRON = 0 > 4s) &&

(PWRONRSTEN = 1) && (Any SWxOMODE = 1 || Any

LDOxOMODE = 1)

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Transiti

Description PWRON_CFG = 0 (Level sensitive) PWRON_CFG = 1 (Edge sensitive)

G Run/Standby/Sleep to

REGS_DISABLE

(Thermal shutdown)

(GOTO_SHIP = 1)

(PWRON = 0 && All SWxOMODE = 0 && All

LDOxOMODE = 0)

(WDI = 0) [2]

(ONKEY High to Low and ONKEY = 0 > Tgreset &&

ONKEY_RST_EN = 1)

(VSYS < UVDET_Fall) [3][4]

(Thermal shutdown)

(GOTO_SHIP = 1)

(PWRON High to Low and PWRON = 0 > 4s &&

PWRONRSTEN = 1 && All SWxOMODE = 0 && All

LDOxOMODE = 0)

(PWRON High to Low and PWRON = 0 > 4s when in

Sleep state)

(WDI = 0) [2]

(ONKEY High to Low and ONKEY = 0 > Tgreset and

ONKEY_RST_EN = 1)

(VSYS < UVDET_Fall) [3]

H REGS_DISABLE to Run

(Only if VSYS > UVDET

and TJ < TSHDN_fall)

(PWRON = 1 ) (PWRON High to Low )

(If entered REGS_DISABLE via long press on PWRON

&& RESTARTEN = 1 && PWRON stays Low > 1.0 s)

(Charger attach)

[5] [6]

I REGS_DISABLE to

CORE_OFF

(Only if VBUS_INVALID =

(GOTO_CORE_OFF = 1 && ONKEY = 1)

(ONKEY High to Low and ONKEY = 0 > Tgreset &&

ONKEY_RST_EN = 1) [7][8]

(GOTO_CORE_OFF = 1 && ONKEY = 1)

(ONKEY High to Low and ONKEY = 0 > Tgreset &&

ONKEY_RST_EN = 1) [7][9]

J REGS_DISABLE to SHIP GOTO_SHIP = 1 && VBUS_INVALID = 1 GOTO_SHIP = 1 && VBUS_INVALID = 1

K CORE_OFF to REGS_

DISABLE

(ONKEY High to Low and ONKEY = 0 > 1000 ms)

(Charger attach)

(ONKEY High to Low and ONKEY = 0 > 1000 ms)

(Charger attach)

L SHIP to REGS_DISABLE (Charger attach)

(Battery re-attach)

(Charger attach)

(Battery re-attach)

[1] This low period is < 4.0 s. If it is longer than 4.0 s, it transitions to G

[2] PWRON pin is pulled low by processor after WDI = 0.

[3] Follows regulator power-down sequence for this transition

[4] REGS_DISABLE is a transitionary state when GOTO_SHIP = 1. The state machine does not stay at G when GOTO_SHIP = 1

[5] WDI pin is masked till RESETBMCU is deasserted.

[6] Debounce on PWRON programmable via PWRONDBNC[1:0]

[7] PWRON pin is pulled low by processor after ONKEY = 0 > Tgreset.

[8] GOTO_CORE_OFF is set by user when system is ON. For other products, a secondary processor is used to set this bit while in REGS_DISABLE

[9] GOTO_CORE_OFF must be set by user when system is ON

10.6 Regulator power-up sequencer

Start-up sequence of all the switching and linear regulators in the PF1550 is

programmable. VSNVS's sequence is not programmable but is always the first regulator

to power up when the PF1550 is powered up via a cold start (from no input to valid input).

When SYS is first applied to the PF1550 (either by applying a battery, or by plugging in a

charger), VSNVS comes up first.

The switching and linear regulators power up based on their programmed OTP sequence

using the respective OTP_XX_SEQ[2:0] when transitioning from REGS_DISABLE to the

RUN state.

RESETBMCU is pulled low from VCOREDIG POR till the end of the power-up

sequencer.

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Data sheet: advance information Rev. 4.0 — 28 September 2018

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RESETBMCU is pulled high 2.0 ms to 1024 ms after the last regulator powers up. This

delay is OTP programmable through the OTP_POR_DLY[2:0] bits.

When transitioning from STANDBY mode to RUN mode, the power-up sequencer is

activated only if any of the regulators turn back on during this transition.

The power-up sequencer ends as soon as the last regulator powers up, rather than

waiting for a fixed time.

The power-up sequencer is always activated when transitioning from Sleep to Run

modes. The sequencer ends as soon as the last regulator powers up, rather than waiting

for a fixed time.

The PWRUP_I interrupt is set to indicate completion of transition from STANDBY to RUN

and SLEEP to RUN.

The PWRUP_I interrupt is set while transitioning from STANDBY to RUN even if the

sequencers were not used. This is used to indicate that the transition is complete.

10.7 Regulator power-down sequencer

The power-down sequencer performs the functional opposite to the power-up

sequencer. Each regulator has an associated register setting (SW1_PWRDN_SEQ[2:0],

SW2_PWRDN_SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_SEQ[2:0],

LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0], VREFDDR_PWRDN_SEQ[2:0])

that sets its power-down sequence.

The default setting of the above registers is equal to the corresponding

power-up sequence setting. For example, SW1_PWRDN_SEQ[2:0] =

OTP_SW1_PWRUP_SEQ[2:0].

When the power-down sequencer is activated, regulators are turned off one by one in

the descending order of the XXX_PWRDN_SEQ[2:0] setting. This way, by default power-

down is a mirror of the power-up sequence.

In one of the "System On" states, the processor can change the values of the

XXX_PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by OTP (or TBB). If

all XXX_PWRDN_SEQ[2:0] = 0x00, the power-down sequencer is bypassed and all the

regulators are turned off at once. During transition from Run to Standby, the power-down

sequencer is activated if any of the regulators are turned off during this transition.

If regulators are not turned off during this transition, the power-down sequencer is

bypassed and the transition happens at once (any associated DVS transitions still take

time).

During transition from Run to Sleep, the power-down sequencer is always activated.

However, if all XXX_PWRDN_SEQ[2:0] = 0, the transition happens immediately.

The PWRDN_I interrupt is set during transition from Run to Sleep and Run to Standby

even if regulators are not turned off during these transitions.

11 Device start up

11.1 Startup timing diagram

The startup timing of the regulators is programmable through OTP, Figure 27 shows the

startup timing of the regulators as determined by their OTP A4 sequence.

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aaa-028499

VSYS

battery

remove

battery

attach

UVDET

tR1

VSNVS

PWRON

Time Slot 0

Time Slot 1

LDO1, 3

LDO2

SW3

Time Slot 2

SW2

VREFDDR

Time Slot 3

SW1

RESETBMCU

tD1

tR2

tD2

tR3

tD3

tR3

tD3

tR3

tD3

tD5

tR3

tD3

tR3

tD3

tR4

tD4

Time Slot 4

tD5

Figure 27. A4 startup and power down sequence

Table 82. A4 startup and power down sequence timing

Parameter Description [1] Min. Typ. Max. Unit

tD1 Turn-on delay of VSNVS — 0.6 — ms

tR1 Rise time of VSNVS — 0.1 — ms

tD2 User determined delay — — — ms

tR2 Rise time of PWRON — [2] — ms

tD3 Power up delay between regulators

•OTP_SEQ_CLK_SPEED = 0

•OTP_SEQ_CLK_SPEED = 1

[3]

—

0.5

2.0

—

tR3 Rise time of regulators [4] — 0.2 — ms

tD4 Turn-on delay of RESETBMCU — 2.0 — ms

tR4 Rise time of RESETBMCU — 0.2 — ms

tD5 Power down delay between

regulators

— 2.0 — ms

[1] All regulators avoid drop-out mode at startup

[2] Depends on the external signal driving PWRON

[3] A4 configuration

[4] Rise time is a function of slew rate of regulators and nominal voltage selected.

11.2 Device start up configuration

Table 83. PF1550 start up configuration

Pre-programmed OTP configuration

Registers A1 A2 A3 A4 A5 A6 A7 A8

Default I2C address 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08

OTP_VSNVS_VOLT[2:0] 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V

OTP_SW1_VOLT[5:0] 1.1 V 1.0V 1.3875 V 1.1 V 1.3875 V 1.275 V 1.3875 V 1.3875 V

OTP_SW1_PWRUP_SEQ[2:0] 1 5 3 4 3 3 3 3

OTP_SW2_VOLT[5:0] 1.1 V 1.2V 1.35 V 1.2 V 1.5 V 1.35 V 1.2 V 1.35 V

OTP_SW2_PWRUP_SEQ[2:0] 2 5 3 3 3 3 3 3

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Pre-programmed OTP configuration

Registers A1 A2 A3 A4 A5 A6 A7 A8

OTP_SW3_VOLT[5:0] 1.8 V 1.8V 3.3 V 1.8 V 3.3 V 3.3 V 1.8 V 3.3 V

OTP_SW3_PWRUP_SEQ[2:0] 3 1 3 2 3 3 3 3

OTP_LDO1_VOLT[4:0] 1.0 V 1.8 V 1.8 V 3.3 V 1.8 V 1.8 V 3.3 V 1.8 V

OTP_LDO1_PWRUP_SEQ[2:0] 4 1 3 1 3 3 3 3

OTP_LDO2_VOLT[3:0] 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V

OTP_LDO2_PWRUP_SEQ[2:0] 4 1 2 2 2 2 2 2

OTP_LDO3_VOLT[4:0] 1.0 V 1.8 V 3.3 V 1.8 V 3.3 V 3.3 V 3.3 V 3.3 V

OTP_LDO3_PWRUP_SEQ[2:0] 5 1 3 1 3 3 3 3

OTP_VREFDDR_PWRUP_SEQ[2:0] 5 5 3 3 3 3 3 3

OTP_SW1_DVS_SEL Non-DVS mode DVS mode

OTP_SW2_DVS_SEL DVS mode Non-DVS mode DVS mode Non-DVS mode

OTP_LDO1_LS_EN LDO Mode

OTP_LDO3_LS_EN LS Mode LDO Mode

OTP_SW1_RDIS_ENB Enabled

OTP_SW2_RDIS_ENB Enabled

OTP_SW3_RDIS_ENB Enabled

OTP_SW1_DVSSPEED 12.5 mV step each 4.0 µs

OTP_SW2_DVSSPEED 12.5 mV step

each 2.0 µs

12.5 mV step each 4.0 µs

OTP_SWx_EN_AND_STBY_EN SW1,SW2,SW3 Enabled in RUN and STANDBY

OTP_LDOx_EN_AND_STBY_EN LDO1,LDO2,LDO3,VREFDDR Enabled in RUN and STANDBY

OTP_PWRON_CFG Level Sensitive Edge Sensitive

OTP_SEQ_CLK_SPEED 0.5 ms Time Slots 2 ms Time Slots

OTP_TGRESET[1:0] 4 secs Global Reset Timer

OTP_POR_DLY[2:0] 2 ms RESETBMCU Power-Up Delay

OTP_UVDET[1:0] Rising 3.0 V; Falling 2.9 V

OTP_I2C_DEGLITCH_EN I2C Deglitch Filter Disabled

OTP_CHGR_OPER[1:0] Charger = ON,

Linear = ON

Charger = OFF,

Linear = ON

Charger = ON,

Linear = ON

Charger = ON,

Linear = ON

Charger = ON,

Linear = ON

Charger = OFF,

Linear = ON

Charger = ON,

Linear = ON

Charger = ON,

Linear = ON

OTP_CHGR_TPRECHG Pre-charge timer = 30 minutes

OTP_CHGR_EOCTIME[2:0] End-Of-Charge Debounce = 16 secs

OTP_CHGR_FCHGTIME[2:0] Fast-Charge Timer Disabled

OTP_CHGR_EOC_MODE Linear ON in the DONE state

OTP_CHGR_CHG_RESTART[1:0] 100 mV below CHGCV

OTP_CHGR_CHG_CC[4:0] CC = 100 mA CC = 500 mA CC = 100 mA

OTP_CHGR_VSYSMIN[1:0] VSYSMIN = 4.3 V VSYSMIN = 3.7 V VSYSMIN = 4.3 V

OTP_CHGR_CHGCV[5:0] CV = 4.2 V

OTP_CHGR_VBUS_LIN_ILIM[4:0] VBUS ILIM

= 500 mA

VBUS ILIM = 1500 mA

OTP_CHGR_VBUS_DPM_REG[2:0] 3.9V 3.9 V 3.9 V 4.5 V 3.9 V 3.9 V 3.9 V 3.9 V

OTP_CHGR_USBPHYLDO USBPHY

LDO Disabled

USBPHY LDO Enabled

OTP_CHGR_USBPHY USBPHY = 3.3 V

OTP_CHGR_ACTDISPHY USBPHY Active

Discharge

Disabled

USBPHY Active Discharge Enabled

12 Register map

12.1 Specific PMIC Registers (Offset is 0x00)

The following pages contain description of the various registers in the PF1550.

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Table 84. Register DEVICE_ID - ADDR 0x00

Name Bit R/W Default Description

DEVICE_ID 2 to 0 R 100 Loaded from fuses

000 — Devices with "00" at the end of the part number, such as

"PF1500"

001 — Future use

010 — Future use

011 — Future use

100 — Devices with "50" at the end of the part number, such as

"PF1550"

101 — Future use

110 — Future use

111 — Future use

FAMILY 7 to 3 R 01111 Identifies PMIC

01111 — 0b0_1111 for "15" used to denote the "PF1550"

Table 85. Register OTP_FLAVOR - ADDR 0x01

Name Bit R/W Default Description

UNUSED 7 to 0 R 0x00 Blown by ATE to indicate flavor of OTP used

0x00 — OTP not burned

0x01 — A1

0x02 — A2

0x03 — A3

continues...

Table 86. Register SILICON_REV - ADDR 0x02

Name Bit R/W Default Description

METAL_LAYER_REV 2 to 0 R 001 Unused

FULL_LAYER_REV 5 to 3 R 010 Unused

FAB_FIN 7 to 6 R 00 Unused

Table 87. Register INT_CATEGORY - ADDR 0x06

Name Bit R/W Default Description

CHG_INT 0 R 0 This bit is set high if any of the charger interrupt status bits are set

0 — No charger interrupt bit is set, cleared, or did not occur

1 — "OR" function of all charger interrupt status bit

SW1_INT 1 R 0 This bit is set high if any of the Buck 1 interrupt status bits are set

0 — SW1 interrupts cleared or did not occur

1 — Any of the SW1 interrupt status bits are set

SW2_INT 2 R 0 This bit is set high if any of the Buck 2 interrupt status bits are set

0 — SW2 interrupts cleared or did not occur

1 — Any of the SW2 interrupt status bits are set

SW3_INT 3 R 0 This bit is set high if any of the Buck 3 interrupt status bits are set

0 — SW3 interrupts cleared or did not occur

1 — any of the SW3 interrupt status bits are set

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Name Bit R/W Default Description

LDO_INT 4 R 0 This bit is set high if any of the LDO interrupt status bits are set.

This includes LDO1, LDO2 and LDO3.

0 — LDO interrupts cleared or did not occur

1 — Any of the LDO interrupt status bits are set

ONKEY_INT 5 R 0 This bit is set high if any of the interrupts associated with ONKEY

push button are set.

0 — ONKEY related interrupts cleared or did not occur

1 — Any of the ONKEY interrupt status bits are set

TEMP_INT 6 R 0 This bit is set if any of the interrupts associated with the die

temperature monitor are set

0 — PMIC junction temperature related interrupts cleared or did

not occur

1 — any of the PMIC junction temperature interrupts status bits

are set

MISC_INT 7 R 0 This bit is set if interrupts not covered by the above mentioned

categories occur

0 — Other interrupts (not covered by categories above) cleared,

or did not occur

1 — Status bit of other interrupts (not covered by categories

above) is set

Table 88. Register SW_INT_STAT0 - ADDR 0x08

Name Bit R/W Default Description

SW1_LS_I 0 RW1C[1] 0 SW1 low-side current limit interrupt status. This bit is set if the

current limit fault persists for longer than the debounce time.

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

SW2_LS_I 1 RW1C 0 SW2 low-side current limit interrupt status. This bit is set if the

current limit fault persists for longer than the debounce time.

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

SW3_LS_I 2 RW1C 0 SW3 low-side current limit interrupt status. This bit is set if the

current limit fault persists for longer than the debounce time.

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

UNUSED 7 to 3 — — Unused

[1] Read or Write 1 to clear the bit

Table 89. Register SW_INT_MASK0 - ADDR 0x09

Name Bit R/W Default Description

SW1_LS_M 0 RW 1 SW1 low-side current limit interrupt mask

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is NOT pulled low if corresponding

interrupt status bit is set.

SW2_LS_M 1 RW 1 SW2 low-side current limit interrupt mask

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is NOT pulled low if corresponding

interrupt status bit is set.

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Name Bit R/W Default Description

SW3_LS_M 2 RW 1 SW3 low-side current limit interrupt mask

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is NOT pulled low if corresponding

interrupt status bit is set.

UNUSED 7 to 3 — — Unused

Table 90. Register SW_INT_SENSE0 - ADDR 0x0A

Name Bit R/W Default Description

SW1_LS_S 0 R 0 SW1 low-side current limit interrupt sense. Sense is high as long

as fault persists (post-debounce).

0 — Fault removed

1 — Fault exists

SW2_LS_S 1 R 0 SW2 low-side current limit interrupt sense. Sense is high as long

as fault persists (post-debounce).

0 — Fault removed

1 — Fault exists

SW3_LS_S 2 R 0 SW3 low-side current limit interrupt sense. Sense is high as long

as fault persists (post-debounce)

0 — Fault removed

1 — Fault exists

UNUSED 7 to 3 — — Unused

Table 91. Register SW_INT_STAT1 - ADDR 0x0B

Name Bit R/W Default Description

SW1_HS_I 0 RW1C [1] 0 SW1 high-side current limit interrupt

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

SW2_HS_I 1 RW1C 0 SW2 high-side current limit interrupt

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

SW3_HS_I 2 RW1C 0 SW3 high-side current limit interrupt

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

UNUSED 7 to 3 — — Unused

[1] Read or Write 1 to clear the bit

Table 92. Register SW_INT_MASK1 - ADDR 0x0C

Name Bit R/W Default Description

SW1_HS_M 0 RW 1 SW1 high-side current limit interrupt mask

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is NOT pulled low if corresponding

interrupt status bit is set.

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Name Bit R/W Default Description

SW2_HS_M 1 RW 1 SW2 high-side current limit interrupt mask

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is NOT pulled low if corresponding

interrupt status bit is set.

SW3_HS_M 2 RW 1 SW3 high-side current limit interrupt mask

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is NOT pulled low if corresponding

interrupt status bit is set.

UNUSED 7 to 3 — — Unused

Table 93. Register SW_INT_SENSE1 - ADDR 0x0D

Name Bit R/W Default Description

SW1_HS_S 0 R 0 SW1 high-side current limit interrupt sense. This bit should not

toggle within a switching cycle (at buck switching frequency), but

report the sense status within the switching cycle.

0 — Fault removed

1 — Fault exists

SW2_HS_S 1 R 0 SW2 high-side current limit interrupt sense. This bit should not

toggle within a switching cycle (at buck switching frequency), but

report the sense status within the switching cycle.

0 — Fault removed

1 — Fault exists

SW3_HS_S 2 R 0 SW3 high-side current limit interrupt sense. This bit should not

toggle within a switching cycle (at buck switching frequency), but

report the sense status within the switching cycle.

0 — Fault removed

1 — Fault exists

UNUSED 7 to 3 — — Unused

Table 94. Register SW_INT_STAT2 - ADDR 0x0E

Name Bit R/W Default Description

SW1_DVS_DONE_I 0 RW1C[1] 0 Interrupt to indicate SW1 DVS complete. This interrupt should

occur every time regulator output voltage is changed (either via

I2C within a given state, or if there is change in voltage when

transitioning states, Run to Standby, for example).

0 — DVS not complete and/or bit cleared

1 — DVS complete

SW2_DVS_DONE_I 1 RW1C 0 Interrupt to indicate SW2 DVS complete. This interrupt should

occur every time regulator output voltage is changed (either via

I2C within a given state, or if there is change in voltage when

transitioning states, Run to Standby, for example).

0 — DVS not complete and/or bit cleared

1 — DVS complete

UNUSED 7 to 2 — — Unused

[1] Read or Write 1 to clear the bit

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Table 95. Register SW_INT_MASK2 - ADDR 0x0F

Name Bit R/W Default Description

SW1_DVS_DONE_M 0 RW 1 Mask for interrupt that indicates SW1 DVS complete

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

SW2_DVS_DONE_M 1 RW 1 Mask for interrupt that indicates SW2 DVS complete

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

UNUSED 7 to 2 — — Unused

Table 96. Register SW_INT_SENSE2 - ADDR 0x10

Name Bit R/W Default Description

SW1_DVS_S 0 R 0 Indicates DVS in progress for SW1

0 — DVS not in progress

1 — DVS in progress

SW2_DVS_S 1 R 0 Indicates DVS in progress for SW2

0 — DVS not in progress

1 — DVS in progress

UNUSED 7 to 2 — — Unused

Table 97. Register LDO_INT_STAT0 - ADDR 0x18

Name Bit R/W Default Description

LDO1_FAULTI 0 RW1C[1] 0 LDO1 current limit interrupt

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

LDO2_FAULTI 1 RW1C 0 LDO2 current limit interrupt

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

LDO3_FAULTI 2 RW1C 0 LDO3 current limit interrupt

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

UNUSED 7 to 3 — — Unused

[1] Read or Write 1 to clear the bit

Table 98. Register LDO_INT_MASK0 - ADDR 0x19

Name Bit R/W Default Description

LDO1_FAULTM 0 RW 1 LDO1 current limit fault interrupt mask

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

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Name Bit R/W Default Description

LDO2_FAULTM 1 RW 1 LDO2 current limit fault interrupt mask

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

LDO3_FAULTM 2 RW 1 LDO3 current limit fault interrupt mask

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

UNUSED 7 to 3 — — Unused

Table 99. Register LDO_INT_SENSE0 - ADDR 0x1A

Name Bit R/W Default Description

LDO1_FAULTS 0 R 0 LDO1 fault interrupt sense

0 — Fault removed

1 — Fault exists

LDO2_FAULTS 1 R 0 LDO2 fault interrupt sense

0 — Fault removed

1 — Fault exists

LDO3_FAULTS 2 R 0 LDO3 fault interrupt sense

0 — Fault removed

1 — Fault exists

UNUSED 7 to 3 — — Unused

Table 100. Register TEMP_INT_STAT0 - ADDR 0x20

Name Bit R/W Default Description

THERM110I 0 RW1C[1] 0 Die temperature crosses 110 °C interrupt. Bidirectional interrupt.

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

UNUSED 1 — — Unused

THERM125I 2 RW1C 0 Die temperature crosses 125 °C interrupt. Bidirectional interrupt.

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

UNUSED 7 to 3 — — Unused

[1] Read or Write 1 to clear the bit

Table 101. Register TEMP_INT_MASK0 - ADDR 0x21

Name Bit R/W Default Description

THERM110M 0 RW 1 Die temperature crosses 110 °C interrupt mask

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is NOT pulled low if corresponding

interrupt status bit is set.

UNUSED 1 — — Unused

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Name Bit R/W Default Description

THERM125M 2 RW 1 Die temperature crosses 125 °C interrupt mask

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

UNUSED 7 to 3 — — Unused

Table 102. Register TEMP_INT_SENSE0 - ADDR 0x22

Name Bit R/W Default Description

THERM110S 0 R 0 110 °C interrupt sense

0 — Die temperature below 110 °C

1 — Die temperature above 110 °C

UNUSED 1 — — Unused

THERM125S 2 R 0 125 °C interrupt sense

0 — Die temperature below 125 °C

1 — Die temperature above 125 °C

UNUSED 7 to 3 — — Unused

Table 103. Register ONKEY_INT_STAT0 - ADDR 0x24

Name Bit R/W Default Description

ONKEY_PUSHI 0 RW1C [1] 0 Interrupt to indicate a push of the ONKEY button. Goes high after

debounce.

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared. Interrupt occurs

whenever ONKEY button is pushed low for longer than the falling

edge debounce setting.

Interrupt also occurs whenever ONKEY button is released high

for longer than the rising edge debounce setting, provided it went

past the falling edge debounce time. In other words, this interrupt

occurs whenever a change in status of the ONKEY_PUSHS

sense bit occurs.

ONKEY_1SI 1 RW1C 0 Interrupt after ONKEY pressed for > 1 s

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

ONKEY_2SI 2 RW1C 0 Interrupt after ONKEY pressed for > 2 s

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

ONKEY_3SI 3 RW1C 0 Interrupt after ONKEY pressed for > 3 s

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

ONKEY_4SI 4 RW1C 0 Interrupt after ONKEY pressed for > 4 s

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

ONKEY_8SI 5 RW1C 0 Interrupt after ONKEY pressed for > 8 s

0 — Interrupt cleared or did not occur

1 — Interrupt occurred and/or not cleared

UNUSED 7 to 6 — — Unused

[1] Read or Write 1 to clear the bit

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Table 104. Register ONKEY_INT_MASK0 - ADDR 0x25

Name Bit R/W Default Description

ONKEY_PUSHM 0 RW 1 Interrupt mask for ONKEY_PUSH_I

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

ONKEY_1SM 1 RW 1 Interrupt mask for ONKEY_1SI

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

ONKEY_2SM 2 RW 1 Interrupt mask for ONKEY_2SI

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is NOT pulled low if corresponding

interrupt status bit is set.

ONKEY_3SM 3 RW 1 Interrupt mask for ONKEY_3SI

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

ONKEY_4SM 4 RW 1 Interrupt mask for ONKEY_4SI

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

ONKEY_8SM 5 RW 1 Interrupt mask for ONKEY_8SI

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

UNUSED 7 to 6 — — Unused

Table 105. Register ONKEY_INT_SENSE0 - ADDR 0x26

Name Bit R/W Default Description

ONKEY_PUSHS 0 R 0 Push interrupt sense

0 — ONKEY not pushed low. This bit follows debounced version

of the ONKEY button being released.

1 — ONKEY pushed low. This follows the ONKEY button after the

debounce circuit (debounce is programmable).

ONKEY_1SS 1 R 0 1 s interrupt sense or cleared after ONKEY button is released

0 — ONKEY not pushed low for >1 s or cleared after ONKEY

button is released.

1 — ONKEY pushed and being held low > 1 s. This bit is cleared

when ONKEY_PUSHS goes back to 0 when the push-button is

released.

ONKEY_2SS 2 R 0 2 s interrupt sense or cleared after ONKEY button is released

0 — ONKEY not pushed low for >1 s or cleared after ONKEY

button is released.

1 — ONKEY pushed and being held low > 1 s. This bit is cleared

when ONKEY_PUSHS goes back to 0 when the push-button is

released.

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Name Bit R/W Default Description

ONKEY_3SS 3 R 0 3 s interrupt sense or cleared after ONKEY button is released

0 — ONKEY not pushed low for >1 s or cleared after ONKEY

button is released

1 — ONKEY pushed and being held low > 1 s. This bit is cleared

when ONKEY_PUSHS goes back to 0 when the push-button is

released.

ONKEY_4SS 4 R 0 4 s interrupt sense or cleared after ONKEY button is released

0 — ONKEY not pushed low for >1 s or cleared after ONKEY

button is released.

1 — ONKEY pushed and being held low > 1 s. This bit is cleared

when ONKEY_PUSHS goes back to 0 when the push-button is

released.

ONKEY_8SS 5 R 0 8 s interrupt sense or cleared after ONKEY button is released

0 — ONKEY not pushed low for >1 s or cleared after ONKEY

button is released.

1 — ONKEY pushed and being held low > 1 s. This bit is cleared

when ONKEY_PUSHS goes back to 0 when the push-button is

released.

UNUSED 7 to 6 — — Unused

Table 106. Register MISC_INT_STAT0 - ADDR 0x28

Name Bit R/W Default Description

PWRUP_I 0 RW1C[1] 0 Interrupt to indicate completion of transition from STANDBY to

RUN and from SLEEP to RUN

0 — Interrupt cleared or has not occurred

1 — Interrupt has occurred

PWRDN_I 1 RW1C 0 Interrupt to indicate completion of transition from RUN to

STANDBY and from RUN to SLEEP

0 — Interrupt cleared or has not occurred

1 — Interrupt has occurred

PWRON_I 2 RW1C 0 Power on button event interrupt

0 — Interrupt cleared or has not occurred

1 — Interrupt has occurred

LOW_SYS_WARN_I 3 RW1C 0 LOW_SYS_WARN threshold crossed interrupt

0 — Interrupt cleared or has not occurred

1 — Interrupt has occurred

SYS_OVLO_I 4 RW1C 0 SYS_OVLO threshold crossed interrupt

0 — Interrupt cleared or has not occurred

1 — Interrupt has occurred

UNUSED 7 to 5 — — Unused

[1] Read or Write 1 to clear the bit

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Table 107. Register MISC_INT_MASK0- ADDR 0x29

Name Bit R/W Default Description

PWRUP_M 0 RW[1] 1 Mask for Interrupt to indicate completion on transition from

STANDBY to RUN and from SLEEP to RUN

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

PWRDN_M 1 RW 1 Mask for Interrupt to indicate completion on transition from RUN

to STANDBY and from RUN to SLEEP

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

PWRON_M 2 RW 1 Power on button event interrupt mask

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

LOW_SYS_WARN_M 3 RW 1 LOW_SYS_WARN threshold crossed interrupt mask

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

SYS_OVLO_M 4 RW 1 SYS_OVLO threshold crossed interrupt mask

0 — Mask removed. INTB pin is pulled low if corresponding

interrupt status bit is set.

1 — Mask enabled. INTB pin is not pulled low if corresponding

interrupt status bit is set.

UNUSED 7 to 5 — — Unused

[1] Asynchronous Set, Read and Write

Table 108. Register MISC_INT_SENSE0 - ADDR 0x2A

Name Bit R/W Default Description

PWRUP_S 0 R 0 Sense for interrupt to indicate completion on transition from

STANDBY to RUN and from SLEEP to RUN

0 — Transition not in progress

1 — Transition in progress

PWRDN_S 1 R 0 Interrupt to indicate completion on transition from RUN to

STANDBY and from RUN to SLEEP

0 — Transition not in progress

1 — Transition in progress

PWRON_S 2 R 0 Power on button event interrupt sense

0 — PWRON low

1 — PWRON high

LOW_SYS_WARN_S 3 R 0 LOW_SYS_WARN threshold crossed interrupt sense

0 — SYS > LOW_SYS_WARN

1 — SYS < LOW_SYS_WARN

SYS_OVLO_S 4 R 0 SYS_OVLO threshold crossed interrupt sense

0 — SYS < SYS_OVLO

1 — SYS > SYS_OVLO

UNUSED 7 to 5 — — Unused

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Table 109. Register COINCELL_CONTROL - ADDR 0x30

Name Bit R/W Default Description

VCOIN 3 to 0 RW 0000 Coin cell charger charging voltage

0000 — 1.8 V

0111 — 3.3 V (goes up in 100 mV step per LSB)

COINCHEN 4 RW 0 Coin cell charger enable

0 — Charger disabled

1 — Charger enabled

UNUSED 7 to 5 — — Unused

Table 110. Register SW1_VOLT - ADDR 0x32

Name Bit R/W Default Description

SW1_VOLT 5 to 0 RW1S[1] — SW1 voltage setting register (Run mode)

000000 — See Table 31 for voltage settings

111111 — See Table 31 for voltage settings

Reset condition — POR

UNUSED 7 to 5 — — Unused

[1] Load from OTP fuse, Read and Write

Table 111. Register SW1_STBY_VOLT - ADDR 0x33

Name Bit R/W Default Description

SW1_STBY_VOLT 5 to 0 RW1S[1] — SW1 output voltage setting register (Standby mode). The default

value here should be identical to SW1_VOLT[5:0] register.

000000 — See Table 31 for voltage settings

111111 — See Table 31 for voltage settings

UNUSED 7 to 6 — — Unused

[1] Load from OTP fuse, Read and Write

Table 112. Register SW1_SLP_VOLT - ADDR 0x34

Name Bit R/W Default Description

SW1_SLP_VOLT 5 to 0 RW1S[1] — SW1 output voltage setting register (Sleep mode). The default

value here should be identical to SW1_VOLT[5:0] register.

000000 — See Table 31 for voltage settings

111111 — See Table 31 for voltage settings

UNUSED 7 to 6 — — Unused

[1] Load from OTP fuse, Read and Write

Table 113. Register SW1_CTRL - ADDR 0x35

Name Bit R/W Default Description

SW1_EN 0 RW1S[1] 0 Enables buck regulator. Loaded from OTP based on the

sequence settings. User can turn regulator off by clearing this bit.

0 — Regulator disabled in Run mode

1 — Regulator enabled in Run mode

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Name Bit R/W Default Description

SW1_STBY_EN 1 RW1S 0 Enables buck regulator in Standby mode. User can turn regulator

off by clearing this bit. The default value of this bit should be

equal to the SW1_EN bit (based on OTP).

0 — Regulator disabled in Standby mode

1 — Regulator enabled in Standby mode

SW1_OMODE 2 RW[2] 0 Enables buck regulator in Sleep mode. User can turn regulator off

by clearing this bit.

0 — Regulator disabled in Sleep mode

1 — Regulator enabled in Sleep mode

SW1_LPWR 3 RW 0 Enables the buck to enter Low-power mode during Standby and

Sleep

0 — Regulator not in Low-power mode

1 — Regulator in Low-power mode during Standby or Sleep

modes

SW1_DVSSPEED 4 RW1S 0 Controls slew rate of DVS transitions. Loaded from OTP and

changeable by user after boot up. Not used when OTP_SW1_

DVS_SEL = 1.

0 — DVS rate at 12.5 mV/2 μs

1 — DVS rate at 12.5 mV/4 μs

SW1_FPWM_IN_DVS 5 RW 0 Enables CCM operation during DVS down

0 — does not force FPWM during DVS

1 — forces regulator to track the DVS reference while it is falling

rather than relying on the load current to pull the voltage low

SW1_FPWM 6 RW 0 Forces buck to go into CCM mode

0 — Not in FPWM mode

1 — Forced in PWM mode irrespective of load current

SW1_RDIS_ENB 7 RW1S 0 Controls discharge resistor on output when regulator disabled

0 — Enables discharge resistor on output when regulator

disabled. Resistor connected at FB pin when regulator disabled to

force capacitor discharge.

1 — Disables discharge resistor on output when regulator

disabled. Resistor not connected at FB pin when regulator

disabled. Relies on leakage/residue load to discharge output

capacitor.

[1] Load from OTP fuse, Read and Write

[2] Asynchronous Set, Read and Write

Table 114. Register SW1_SLP_VOLT - ADDR 0x36

Name Bit R/W Default Description

SW1_ILIM 1 to 0 RW1S[1] 00 Sets current limit of SW1 regulator

00 — Typical current limit of 1.0 A

01 — Typical current limit of 1.2 A

10 — Typical current limit of 1.5 A

11 — Typical current limit of 2.0 A

UNUSED 3 to 2 — — Unused

SW1_TMODE_SEL 4 RW 0 0 — TON control

1 — TOFF control

UNUSED 7 to 5 — — Unused

[1] Load from OTP fuse, Read and Write

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Table 115. Register SW2_VOLT - ADDR 0x38

Name Bit R/W Default Description

SW2_VOLT 5 to 0 RW1S[1] — SW2 voltage setting register (Run mode)

000000 —See Table 31 for voltage settings

111111 — See Table 31 for voltage settings

UNUSED 7 to 6 — — Unused

[1] Load from OTP fuse, Read and Write

Table 116. Register SW2_STBY_VOLT - ADDR 0x39

Name Bit R/W Default Description

SW2_STBY_VOLT 5 to 0 RW1S[1] — SW2 output voltage setting register (Standby mode). The default

value here should be identical to SW2_VOLT[5:0] register.

000000 — See Table 31 for voltage settings

111111 — See Table 31 for voltage settings

UNUSED 7 to 6 — — Unused

[1] Load from OTP fuse, Read and Write

Table 117. Register SW2_SLP_VOLT - ADDR 0x3A

Name Bit R/W Default Description

SW2_SLP_VOLT 5 to 0 RW1S[1] — SW2 output voltage setting register (Sleep mode). The default

value here should be identical to SW2_VOLT[5:0] register.

000000 — See Table 31 for voltage settings

111111 — See Table 31 for voltage settings

UNUSED 7 to 6 — — Unused

[1] Load from OTP fuse, Read and Write

Table 118. Register SW2_CTRL - ADDR 0x3B

Name Bit R/W Default Description

SW2_EN 0 RW1S[1] 0 Enables buck regulator. Loaded from OTP based on the

sequence settings. User can turn regulator off by clearing this bit.

0 — Regulator disabled in Run mode

1 — Regulator enabled in Run mode

SW2_STBY_EN 1 RW1S 0 Enables buck regulator in Standby mode. User can turn regulator

off by clearing this bit. The default value of this bit should be

equal to the SW1_EN bit (based on OTP).

0 — Regulator disabled in Standby mode

1 — Regulator enabled in Standby mode

SW2_OMODE 2 RW 0 Enables buck regulator in Sleep mode. User can turn regulator off

by clearing this bit.

0 — Regulator disabled in Sleep mode

1 — Regulator enabled in Sleep mode

SW2_LPWR 3 RW 0 Enables the buck to enter Low-power mode during Standby and

Sleep modes

0 — Regulator not in Low-power mode

1 — Regulator in Low-power mode during Standby or Sleep

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Name Bit R/W Default Description

SW2_DVSSPEED 4 RW1S 0 Controls slew rate of DVS transitions. Loaded from OTP and

changeable by user after boot up. Not used when OTP_SW2_

DVS_SEL = 1.

0 — DVS rate at 12.5 mV/2 μs

1 — DVS rate at 12.5 mV/4 μs

SW2_FPWM_IN_DVS 5 RW 0 Enables CCM operation during DVS down

0 — does not force FPWM during DVS

1 — forces regulator to track the DVS reference while it is falling

rather than relying on the load current to pull the voltage low

SW2_FPWM 6 RW 0 Forces buck to go into CCM mode

0 — Not in FPWM mode

1 — Forced in PWM mode irrespective of load current.

SW2_RDIS_ENB 7 RW1S 0 Controls discharge resistor on output when regulator disabled

0 — Enables discharge resistor on output when regulator

disabled. Resistor connected at FB pin when regulator disabled to

force capacitor discharge.

1 — Disables discharge resistor on output when regulator

disabled. Resistor not connected at FB pin when regulator

disabled. Relies on leakage/residue load to discharge output

capacitor.

[1] Load from OTP fuse, Read and Write

Table 119. Register SW2_CTRL1 - ADDR 0x3C

Name Bit R/W Default Description

SW2_ILIM 1 to 0 RW1S 00 Sets current limit of SW2 regulator

00 — Typical current limit of 1.0 A

01 — Typical current limit of 1.2 A

10 — Typical current limit of 1.5 A

11 — Typical current limit of 2.0 A

UNUSED 3 to 2 — — Unused

SW2_TMODE_SEL 4 RW 0 0 — TON control

1 — TOFF control

UNUSED 7 to 5 — — Unused

Table 120. Register SW3_VOLT - ADDR 0x3E

Name Bit R/W Default Description

SW3_VOLT 3 to 0 RW1S — SW3 voltage setting register (Run mode). Loaded from fuses.

Read only because DVS is not supported in this regulator.

0000 — See Table 37 for voltage settings

1111 — See Table 37 for voltage settings

UNUSED 7 to 4 — — Unused

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Table 121. Register SW3_STBY_VOLT - ADDR 0x3F

Name Bit R/W Default Description

SW3_STBY_VOLT 3 to 0 RW1S — SW3 voltage setting register (Standby mode). Loaded from fuses.

Read only because DVS is not supported in this regulator.

0000 — See Table 37 for voltage settings

1111 —See Table 37 for voltage settings

UNUSED 7 to 4 — — Unused

Table 122. Register SW3_SLP_VOLT - ADDR 0x40

Name Bit R/W Default Description

SW3_SLP_VOLT 3 to 0 RW1S — SW3 voltage setting register (Sleep mode). Loaded from fuses.

Read only because DVS is not supported in this regulator.

0000 — See Table 37 for voltage settings

1111 — See Table 37 for voltage settings

UNUSED 7 to 4 — — Unused

Table 123. Register SW3_CTRL - ADDR 0x41

Name Bit R/W Default Description

SW3_EN 0 RW1S 0 Enables buck regulator. Loaded from OTP based on the

sequence settings. User can turn regulator off by clearing this bit.

0 — Regulator disabled in Run mode

1 — Regulator enabled in Run mode

SW3_STBY_EN 1 RW1S 0 Enables buck regulator in Standby mode. User can turn regulator

off by clearing this bit. The default value of this bit should be

equal to the SW1_EN bit (based on OTP).

0 — Regulator disabled in Standby mode

1 — Regulator enabled in Standby mode

SW3_OMODE 2 RW 0 Enables buck regulator in Sleep mode. User can turn regulator off

by clearing this bit.

0 — Regulator disabled in Sleep mode

1 — Regulator enabled in Sleep mode

SW3_LPWR 3 RW 0 Enables the buck to enter Low-power mode during Standby and

Sleep modes

0 — Regulator not in Low-power mode

1 — Regulator in Low-power mode while in Standby or Sleep

UNUSED 4 — — Unused

UNUSED 5 — — Unused

SW3_FPWM 6 RW 0 Forces buck to go into CCM mode

0 — Not in FPWM mode

1 — Forced in PWM mode irrespective of load current

SW3_RDIS_ENB 7 RW1S 0 Controls discharge resistor on output when regulator disabled

0 — Enables discharge resistor on output when regulator

disabled. Resistor connected at FB pin when regulator disabled to

force capacitor discharge.

1 — Disables discharge resistor on output when regulator

disabled. Resistor not connected at FB pin when regulator

disabled. Relies on leakage/residue load to discharge output

capacitor.

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Table 124. Register SW3_CTRL1 - ADDR 0x42

Name Bit R/W Default Description

SW3_ILIM 1 to 0 RW1S 00 Sets current limit of SW3 regulator

00 — Typical current limit of 1.0 A

01 — Typical current limit of 1.2 A

10 — Typical current limit of 1.5 A

11 — Typical current limit of 2.0 A

UNUSED 3 to 2 — — Unused

SW3_TMODE_SEL 4 RW 0 0 — TON control

1 — TOFF control

UNUSED 7 to 5 — — Unused

Table 125. Register VSNVS_CTRL - ADDR 0x48

Name Bit R/W Default Description

VSNVS_VOLT 2 to 0 RW1S 000 Not used in PF1550. Placeholder for future products.

CLKPULSE 3 RW 0 Optional bit used for evaluation. Refer to IP block

FORCEBOS 4 RW 0 Optional bit for evaluation

0 — BOS circuit activated only when VSYS < UVDET

1 — Forces best of supply circuit irrespective of UVDET

LIBGDIS 5 RW 0 Use to reduce quiescent current in coin cell mode

0 — VSNVS local bandgap enabled in coin cell mode

1 — VSNVS local bandgap disabled in coin cell mode to save

quiescent current

UNUSED 7 to 6 — — Unused

Table 126. Register VREFDDR_CTRL - ADDR 0x4A

Name Bit R/W Default Description

VREFDDR_EN 0 RW1S 0 0 — Disables VREFDDR regulator

1 — Enables VREFDDR regulator. This is set by the OTP

sequence.

VREFDDR_STBY_EN 1 RW1S 0 The default value for this should be same as VREFDDREN

0 — Disables VREFDDR regulator in Standby mode

1 — Enables VREFDDR regulator in Standby mode if

VREFDDREN = 1

VREFDDR_OMODE 2 RW 0 0 — Keeps VREFDDR off in Off mode

1 — Enables VREFDDR in Sleep mode if VREFDDREN = 1

VREFDDR_LPWR 3 RW 0 0 — Disables VREFDDR Low-power mode

1 — Enables VREFDDR Low-power mode

UNUSED 7 to 4 — — Unused

Table 127. Register LDO1_VOLT - ADDR 0x4C

Name Bit R/W Default Description

LDO1_VOLT 4 to 0 RW1S — LDO1 output voltage setting register. Loaded from OTP.

00000 — See Table 41 for voltage settings

11111 — See Table 41 for voltage settings

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Name Bit R/W Default Description

UNUSED 7 to 5 — — Unused

Table 128. Register LDO1_CTRL - ADDR 0x4D

Name Bit R/W Default Description

VLDO1_EN 0 RW1S 0 Enables LDO regulator. Loaded from OTP based on the

sequence settings. User can turn regulator off by clearing this bit.

0 — Disables regulator

1 — Enables regulator

VLDO1_STBY_EN 1 RW1S 0 Enables LDO in Standby mode. Default value of this bit should be

same as VLDO1_EN.

0 — Disables regulator

1 — Enables regulator

VLDO1_OMODE 2 RW 0 Enables LDO in Sleep mode

0 — Disables regulator

1 — Enables regulator

VLDO1_LPWR 3 RW 0 Forces LDO to Low-power mode in Sleep and Standby modes

0 — Not in Low-power mode during Standby and Sleep

1 — Regulator in Low-power mode during Standby and Sleep

LDO1_LS_EN 4 RW1S 0 This is loaded from OTP_LDOy_LS_EN and changeable from 0

to 1 on power up. Changing from 1 to 0 is not allowed.

0 — Sets LDOy in LDO mode

1 — Sets LDOy to a load switch (fully on) mode

UNUSED 7 to 5 — — Unused

Table 129. Register LDO2_VOLT - ADDR 0x4F

Name Bit R/W Default Description

LDO2_VOLT 3 to 0 RW1S — LDO2 output voltage setting register. Loaded from OTP.

0000 — See Table 43 for voltage settings

1111 — See Table 43 for voltage settings

UNUSED 7 to 4 — — Unused

Table 130. Register LDO2_CTRL - ADDR 0x50

Name Bit R/W Default Description

VLDO2_EN 0 RW1S 0 Enables LDO regulator. Loaded from OTP based on the

sequence settings. User can turn regulator off by clearing this bit.

0 — Disables regulator

1 — Enables regulator

VLDO2_STBY_EN 1 RW1S 0 Enables LDO in Standby mode. Default value of this bit should be

same as VLDO1_EN.

0 — Disables regulator

1 — Enables regulator

VLDO2_OMODE 2 RW 0 Enables LDO in Sleep mode

0 — Disables regulator

1 — Enables regulator

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Name Bit R/W Default Description

VLDO2_LPWR 3 RW 0 Forces LDO to Low-power mode in Sleep and Standby modes

0 — Not in Low-power mode during Standby and Sleep

1 — Regulator in Low-power mode during Standby and Sleep

UNUSED 7 to 4 — — Unused

Table 131. Register LDO3_VOLT - ADDR 0x52

Name Bit R/W Default Description

LDO3_VOLT 4 to 0 RW1S — LDO3 output voltage setting register. Loaded from OTP.

00000 — See Table 41 for voltage settings

11111 — See Table 41 for voltage settings

UNUSED 7 to 5 — — Unused

Table 132. Register LDO3_CTRL - ADDR 0x53

Name Bit R/W Default Description

VLDO3_EN 0 RW1S 0 Enables LDO regulator. Loaded from OTP based on the

sequence settings. User can turn regulator off by clearing this bit.

0 — Disables regulator

1 — Enables regulator

VLDO3_STBY_EN 1 RW1S 0 Enables LDO in Standby mode. Default value of this bit should be

same as VLDO1_EN.

0 — Disables regulator

1 — Enables regulator

VLDO3_OMODE 2 RW 0 Enables LDO in Sleep mode

0 — Disables regulator

1 — Enables regulator

VLDO3_LPWR 3 RW 0 Forces LDO to Low-power mode in Sleep and Standby modes

0 — Not in Low-power mode during Standby and Sleep

1 — Regulator in Low-power mode during Standby and Sleep

LDO3_LS_EN 4 RW1S 0 This is loaded from OTP_LDOy_LS_EN and changeable from 0

to 1 on power up. Changing from 1 to 0 is not allowed.

0 — sets LDOy in LDO mode

1 — sets LDOy to a load switch (fully on) mode

UNUSED 7 to 5 — — Unused

Table 133. Register PWRCTRL0 - ADDR 0x58

Name Bit R/W Default Description

STANDBYDLY 1 to 0 RW 01 Controls delay of Standby pin after synchronization

0 — No additional delay

1 — 32 kHz cycle additional delay

2 — 32 kHz cycle additional delay

3 — 32 kHz cycle additional delay

STANDBYINV 2 RW 0 Controls polarity of STANDBY pin

0 — Standby pin input active high

1 — Standby pin input active low

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Name Bit R/W Default Description

POR_DLY 5 to 3 RW1S 000 Controls delay of RESETBMCU pin after power up (loaded from

OTP)

000 — RESETBMCU goes high 2 ms after last regulator

010 — RESETBMCU goes high 4 ms after last regulator

011 — RESETBMCU goes high 8 ms after last regulator

100 — RESETBMCU goes high 16 ms after last regulator

101 — RESETBMCU goes high 128 ms after last regulator

110 — RESETBMCU goes high 256 ms after last regulator

111 — RESETBMCU goes high 1024 ms after last regulator

TGRESET 7 to 6 RW1S 00 Controls duration for which ONKEY has to be pushed low for a

global reset (part goes to REGS_DISABLE)

00 — 4 s

01 — 8 s

10 — 12 s

11 — 16 s

Table 134. Register PWRCTRL1 - ADDR 0x59

Name Bit R/W Default Description

PWRONDBNC 1 to 0 RW 00 Controls debounce of PWRON when in push-button mode

(PWRON_CFG = 1)

00 — 31.25 ms falling edge; 31.25 ms rising edge

01 — 31.25 ms falling edge; 31.25 ms rising edge

10 — 125 ms falling edge; 31.25 ms rising edge

11 — 750 ms falling edge; 31.25 ms rising edge

ONKEYDBNC 3 to 2 RW 00 Controls debounce of ONKEY push button

00 — 31.25 ms falling edge; 31.25 ms rising edge

01 — 31.25 ms falling edge; 31.25 ms rising edge

10 — 125 ms falling edge; 31.25 ms rising edge

11 — 750 ms falling edge; 31.25 ms rising edge

PWRONRSTEN 4 RW 0 Enables going to REGS_DISABLE or Sleep mode when

PWRON_CFG = 1. See Section 10 "PF1550 state machine" for

details.

0 — Long press on PWRON button does not take state to

REGS_DISABLE or Sleep

1 — Long press on PWRON button takes state to

REGS_DISABLE or Sleep

RESTARTEN 5 RW 0 Enables restart of system when PWRON push button is held low

for 5 s

0 — No impact

1 — When going to REGS_DISABLE via a long press of PWRON

button, holding it low for 1 more second takes state back to RUN

(Equally, a 5 second push restarts the system)

REGSCPEN 6 RW 0 Shuts down LDO if it enters a current limit fault. Controls LDO1,

LDO2 and LDO3.

0 — LDO does not shut down in the event of a current limit fault.

Continues to current limit

1 — LDO is turned off when it encounters a current limit fault

ONKEY_RST_EN 7 RW 1 Enables turning off of system via ONKEY. See Section 10

"PF1550 state machine" for details.

0 — ONKEY cannot be used to turn off or restart system

1 — ONKEY can be used to turn off or restart system

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 135. Register PWRCTRL2 - ADDR 0x5A

Name Bit R/W Default Description

UVDET 1 to 0 RW1S 00 Sets UVDET threshold

00 — Rising 2.65 V; Falling 2.55 V

01 — Rising 2.8 V; Falling 2.7 V

10 — Rising 3.0 V; Falling 2.9 V

11 — Rising 3.1 V; Falling 3.0 V

LOW_SYS_WARN 3 to 2 RW 00 Sets LOW_SYS_WARN threshold

00 — Rising 3.3 V; Falling 3.1 V

01 — Rising 3.5 V; Falling 3.3 V

10 — Rising 3.7 V; Falling 3.5 V

11 — Rising 3.9 V; Falling 3.7 V

UNUSED 7 to 4 — — Unused

Table 136. Register PWRCTRL3 - ADDR 0x5B

Name Bit R/W Default Description

GOTO_SHIP 0 RW 0 Set this bit to go to SHIP mode from any state. See Section 10

"PF1550 state machine" for details.

0 — No impact

1 — PF1550 gracefully enters SHIP mode

GOTO_CORE_OFF 1 RW 0 Set this bit to go to CORE_OFF mode once in REGS_DISABLE

state

0 — No impact

1 — PF1550 gracefully enters CORE_OFF mode when in

REGS_DISABLE state

UNUSED 7 to 2 — — Unused

Table 137. Register SW1_PWRDN_SEQ - ADDR 0x5F

Name Bit R/W Default Description

SW1_PWRDN_SEQ 2 to 0 RW1S 000 This contains same value as power-up sequence value by

default. Power-up sequence is in mirror registers.

xxx = The power-down sequencer performs the functional

opposite to the power-up sequencer. Each regulator has an

associated register setting (SW1_PWRDN_SEQ[2:0], SW2_

PWRDN_SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_

SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0].

VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down

sequence. The default setting of the above registers is equal

to the corresponding power-up sequence setting. For example,

SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0].

When the power-down sequencer is activated, regulators are

turned off one by one in the descending order of the XXX_

PWRDN_SEQ[2:0] setting. This way, by default, power-down

is a mirror of the power-up sequence. In one of the "System

On" states, the processor can change the values of the XXX_

PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by

OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the power-

down sequencer is bypassed and all the regulators are turned off

at once.

UNUSED 7 to 3 — — Unused

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Table 138. Register SW2_PWRDN_SEQ - ADDR 0x60

Name Bit R/W Default Description

SW2_PWRDN_SEQ 2 to 0 RW1S 000 This contains same value as power-up sequence value by

default. Power-up sequence is in mirror registers.

xxx = The power-down sequencer performs the functional

opposite to the power-up sequencer. Each regulator has an

associated register setting (SW1_PWRDN_SEQ[2:0], SW2_

PWRDN_SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_

SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0].

VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down

sequence. The default setting of the above registers is equal

to the corresponding power-up sequence setting. For example,

SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0].

When the power-down sequencer is activated, regulators are

turned off one by one in the descending order of the XXX_

PWRDN_SEQ[2:0] setting. This way, by default, power-down

is a mirror of the power-up sequence. In one of the "System

On" states, the processor can change the values of the XXX_

PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by

OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the power-

down sequencer is bypassed and all the regulators are turned off

at once.

UNUSED 7 to 3 — — Unused

Table 139. Register SW2_PWRDN_SEQ - ADDR 0x61

Name Bit R/W Default Description

SW3_PWRDN_SEQ 2 to 0 RW1S 000 This contains same value as power-up sequence value by

default. Power-up sequence is in mirror registers.

xxx = The power-down sequencer performs the functional

opposite to the power-up sequencer. Each regulator has an

associated register setting (SW1_PWRDN_SEQ[2:0], SW2_

PWRDN_SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_

SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0].

VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down

sequence. The default setting of the above registers is equal

to the corresponding power-up sequence setting. For example,

SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0].

When the power-down sequencer is activated, regulators are

turned off one by one in the descending order of the XXX_

PWRDN_SEQ[2:0] setting. This way, by default, power-down

is a mirror of the power-up sequence. In one of the "System

On" states, the processor can change the values of the XXX_

PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by

OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the power-

down sequencer is bypassed and all the regulators are turned off

at once.

UNUSED 7 to 3 — — Unused

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 140. Register LDO1_PWRDN_SEQ - ADDR 0x62

Name Bit R/W Default Description

LDO1_PWRDN_SEQ 2 to 0 RW1S 000 This contains same value as power-up sequence value by

default. Power-up sequence is in mirror registers.

xxx = The power-down sequencer performs the functional

opposite to the power-up sequencer. Each regulator has an

associated register setting (SW1_PWRDN_SEQ[2:0], SW2_

PWRDN_SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_

SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0].

VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down

sequence. The default setting of the above registers is equal

to the corresponding power-up sequence setting. For example,

SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0].

When the power-down sequencer is activated, regulators are

turned off one by one in the descending order of the XXX_

PWRDN_SEQ[2:0] setting. This way, by default, power-down

is a mirror of the power-up sequence. In one of the "System

On" states, the processor can change the values of the XXX_

PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by

OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the power-

down sequencer is bypassed and all the regulators are turned off

at once.

UNUSED 7 to 3 — — Unused

Table 141. Register LDO2_PWRDN_SEQ - ADDR 0x63

Name Bit R/W Default Description

LDO2_PWRDN_SEQ 2 to 0 RW1S 000 This contains same value as power-up sequence value by

default. Power-up sequence is in mirror registers.

xxx = The power-down sequencer performs the functional

opposite to the power-up sequencer. Each regulator has an

associated register setting (SW1_PWRDN_SEQ[2:0], SW2_

PWRDN_SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_

SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0].

VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down

sequence. The default setting of the above registers is equal

to the corresponding power-up sequence setting. For example,

SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0].

When the power-down sequencer is activated, regulators are

turned off one by one in the descending order of the XXX_

PWRDN_SEQ[2:0] setting. This way, by default, power-down

is a mirror of the power-up sequence. In one of the "System

On" states, the processor can change the values of the XXX_

PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by

OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the power-

down sequencer is bypassed and all the regulators are turned off

at once.

UNUSED 7 to 3 — — Unused

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 142. Register LDO3_PWRDN_SEQ - ADDR 0x64

Name Bit R/W Default Description

LDO3_PWRDN_SEQ 2 to 0 RW1S 000 This contains same value as power-up sequence value by

default. Power-up sequence is in mirror registers.

xxx = The power-down sequencer performs the functional

opposite to the power-up sequencer. Each regulator has an

associated register setting (SW1_PWRDN_SEQ[2:0], SW2_

PWRDN_SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_

SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0].

VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down

sequence. The default setting of the above registers is equal

to the corresponding power-up sequence setting. For example,

SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0].

When the power-down sequencer is activated, regulators are

turned off one by one in the descending order of the XXX_

PWRDN_SEQ[2:0] setting. This way, by default, power-down

is a mirror of the power-up sequence. In one of the "System

On" states, the processor can change the values of the XXX_

PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by

OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the power-

down sequencer is bypassed and all the regulators are turned off

at once.

UNUSED 7 to 3 — — Unused

Table 143. Register VREFDDR_PWRDN_SEQ - ADDR 0x65

Name Bit R/W Default Description

VREFDDR_PWRDN_S

2 to 0 RW1S 000 This contains same value as power-up sequence value by

default. Power-up sequence is in mirror registers.

xxx = The power-down sequencer performs the functional

opposite to the power-up sequencer. Each regulator has an

associated register setting (SW1_PWRDN_SEQ[2:0], SW2_

PWRDN_SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_

SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0].

VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down

sequence. The default setting of the above registers is equal

to the corresponding power-up sequence setting. For example,

SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0].

When the power-down sequencer is activated, regulators are

turned off one by one in the descending order of the XXX_

PWRDN_SEQ[2:0] setting. This way, by default, power-down

is a mirror of the power-up sequence. In one of the "System

On" states, the processor can change the values of the XXX_

PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by

OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the power-

down sequencer is bypassed and all the regulators are turned off

at once.

UNUSED 7 to 3 — — Unused

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 144. Register STATE_INFO - ADDR 0x67

Name Bit R/W Default Description

STATE 5 to 0 R 000000 Indicates machine state

000000 — Wait status

001100 — RUN state

001101 — STANDBY state

001110 — SLEEP/LPSR state

101011 — REGS_DISABLE state

Other bits are reserved

UNUSED 7 to 6 — — Unused

Table 145. Register I2C_ADDR - ADDR 0x68

Name Bit R/W Default Description

I2C_SLAVE_ADDR_L

SBS

2 to 0 R 000 Loaded from fuses. But read only in functional space.

000 — Slave Address: 0x08

001 — Slave Address: 0x09

010 — Slave Address: 0x0A

011 — Slave Address: 0x0B

100 — Slave Address: 0x0C

101 — Slave Address: 0x0D

110 — Slave Address: 0x0E

111 — Slave Address: 0x0F

USE_DEFAULT_ADD R 7 RW 0 DEFAULT ADDR

Table 146. Register RC_16MHZ - ADDR 0x6B

Name Bit R/W Default Description

REQ_16MHZ 0 RW 0 Enables 16 MHz clock

0 — 16 MHz clock enable controlled by state machine

1 — 16 MHz clock always enabled

REQ_ACORE_ON 1 RW 0 Controls Analog core enable

0 — Analog core enable controlled by state machine

1 — Analog core always on

REQ_ACORE_HIPWR 2 RW 0 Controls Low-power mode of the analog core

0 — Analog core Low-power mode controlled by state machine

1 — Analog core never in Low-power mode

UNUSED 7 to 3 — — Unused

Table 147. Register KEY1 - ADDR 0x6B

Name Bit R/W Default Description

KEY1 7 to 0 RW 0x00 Unused

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12.2 Specific Charger Registers (Offset is 0x80)

Table 148. Register CHG_INT - ADDR 0x00

Name Bit R/W Default Description

SUP_I 0 RW1S[1] 0 Supplement mode interrupt

0 — The SUP_OK bit interrupt has not occurred or been cleared

1 — The SUP_OK bit interrupt has occurred

Reset condition — VCOREDIG_RSTB

BAT2SOC_I 1 RW1S 0 VBATT to VSYS overcurrent interrupt

0 — The BAT2SOC_OK interrupt has not occurred or been

cleared

1— The BAT2SOC _OK bit interrupt has occurred

Reset condition — VCOREDIG_RSTB

BAT_I 2 RW1S 0 Battery interrupt

0 — The BAT_OK interrupt has not occurred or been cleared

1 — The BAT_OK interrupt has occurred

Reset condition — VCOREDIG_RSTB

CHG_I 3 RW1S 0 Charger interrupt

0 — The CHG_OK interrupt has not occurred or been cleared

1 — The CHG_OK interrupt has occurred

Reset condition — VCOREDIG_RSTB

RSVD4 4 RW1S 0 Unused

VBUS_I 5 RW1S 0 VBUS interrupt

0 — The VBUS_OK interrupt has not occurred or been cleared

1 — The VBUS_OK interrupt has occurred

Reset condition — VCOREDIG_RSTB

VBUS_DPM_I 6 RW1S 0 VBUS_DPM interrupt

0 — The VBUS_DPM _OK interrupt has not occurred or been

cleared

1 — The VBUS_DPM _OK interrupt has occurred

Reset condition — VCOREDIG_RSTB

THM_I 7 RW1S 0 THM interrupt. Occurs when Warm/Cool thresholds are crossed

or when thermal foldback is active. After the interrupt has

occurred, THM_OK bit can be read to know the source of the

interrupt.

If THM_OK = 0, warm/cool thresholds are crossed

If THM_OK = 1, thermal foldback is active

0 — THM interrupt has not occurred or has been cleared

1 — THM interrupt has occurred

Reset condition — VCOREDIG_RSTB

[1] Load from OTP fuse, Read and Write

Table 149. Register CHG_INT_MASK - ADDR 0x02

Name Bit R/W Default Description

SUP_M 0 RW 1 Supplement mode interrupt mask

0 — Unmasked

1 — Masked

Reset condition — VCOREDIG_RSTB

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Power management integrated circuit (PMIC) for low power application processors

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Name Bit R/W Default Description

BAT2SOC_M 1 RW 1 VBATT to VSYS overcurrent interrupt mask

0 — Unmasked

1 — Masked

Reset condition — VCOREDIG_RSTB

BAT_M 2 RW 1 Battery interrupt mask

0 — Unmasked

1 — Masked

Reset condition — VCOREDIG_RSTB

CHG_M 3 RW 1 Charger interrupt mask

0 — Unmasked

1 — Masked

Reset condition — VCOREDIG_RSTB

RSVD4 4 RW 1 Unused

VBUS_M 5 RW 1 VBUS interrupt mask

0 — Unmasked

1 — Masked

Reset condition — VCOREDIG_RSTB

VBUS_DPM_M 6 RW 1 VBUS_DPM interrupt mask

0 — Unmasked

1 — Masked

Reset condition — VCOREDIG_RSTB

THM_M 7 RW 1 THM interrupt mask

0 — Unmasked

1 — Masked

Reset condition — VCOREDIG_RSTB

Table 150. Register CHG_INT_OK - ADDR 0x04

Name Bit R/W Default Description

SUP_OK 0 R 0 Supplement mode indicator

0 — Supplement mode not detected

1 — Supplement mode detected

Reset condition — VCOREDIG_RSTB

BAT2SOC_OK 1 R 0 Single-bit battery overcurrent indicator

0 — Battery to VSYS has not hit overcurrent limit

1 — Battery to VSYS has hit overcurrent limit (BATT_SNS Bit 5 =

0b1)

Reset condition — VCOREDIG_RSTB

BAT_OK 2 R 1 Single-bit battery status indicator. See BATT_SNS for more

information.

0 — The battery has an issue or the charger has been

suspended, for example, BAT_SNS = 0x06 or 0x07 or 0x09

1 — The battery is okay, for example, BAT_SNS ≠ 0x06 or 0x07

or 0x09

Reset condition — VCOREDIG_RSTB

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Name Bit R/W Default Description

CHG_OK 3 R 0 Single-bit charger status indicator. See CHG_SNS for more

information.

Reset condition — VCOREDIG_RSTB

0 — The charger is not charging, has suspended charging or

Thermal Reg = 1, for example, CHG_SNS ≠ 0x00 or 0x01 or 0x02

or 0x03

1 — The charger is okay, for example, CHG_SNS = 0x00 or 0x01

or 0x02 or 0x03

Reset condition — VCOREDIG_RSTB

RSVD4 4 R 0 Unused

VBUS_OK 5 R 0 Single-bit VBUS_LIN input status indicator. See VBUS_LIN_SNS

for more information.

0 — The VBUS_LIN input is invalid. For example, VBUS_VALID

= 0.

1 — The VBUS_LIN input is valid. For example, VBUS_VALID =

Reset condition — VCOREDIG_RSTB

VBUS_DPM_OK 6 R 0 VBUS_DPM status indicator. This register provides status of input

Dynamic Power Management threshold.

0 — Not in VBUS_DPM mode

1 — VBUS_DPM mode

Reset condition — VCOREDIG_RSTB

THM_OK 7 R 1 Thermistor status indicator. This register provides information on

whether battery temperature is within or outside the thermistor

cool/warm thresholds.

0 — Thermistor outside cool and warm thresholds

1 — Thermistor between cool and warm thresholds

Reset condition — VCOREDIG_RSTB

Table 151. Register VBUS_SNS - ADDR 0x06

Name Bit R/W Default Description

RSVD0 1 to 0 R 00 Unused

VBUS_UVLO_SNS 2 R 1 0 — VBUS_ LIN > VBUS_LIN_UVLO

1 — VBUS_ LIN < VBUS_LIN_UVLO or when VBUS is detached

VBUS_IN2SYS_SNS 3 R 1 0 — VBUS_ LIN > VBATT + VIN2SYS

1 — VBUS_ LIN < VBATT + VIN2SYS

VBUS_OVLO_SNS 4 R 0 0 — VBUS_ LIN < VBUS_LIN_OVLO

1 — VBUS_ LIN > VBUS_LIN_OVLO

VBUS_VALID 5 R 0 0 — VBUS is not valid

1 — VBUS is valid, VBUS_LIN > VBUS_LIN_UVLO, VBUS_LIN >

VBATT + VIN2SYS, VBUS_LIN < VBUS_LIN_OVLO

Reset condition — VCOREDIG_RSTB

RSVD6 6 R 0 Unused

VBUS_DPM_SNS 7 R 0 VBUS_LIN DPM sense details

0 — VBUS _LIN DPM threshold has not been triggered

1 — VBUS_LIN DPM threshold has been triggered

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Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 152. Register CHG_SNS - ADDR 0x07

Name Bit R/W Default Description

CHG_SNS 3 to 0 R 1000 Charger sense

0 — Charger is in precharge mode, CHG_OK = 1, VBATT <

VPRECHG.LB, TJ < TSHDN

1 — Charger is in fast-charge constant current mode, CHG_OK =

1, VBATT < VBATREG, TJ < TSHDN

2 — Charger is in fast-charge constant voltage mode, CHG_OK =

1, VBATT = VBATREG, TJ < TSHDN

3 — Charger is in end-of-charge mode, CHG_OK = 1, VBATT ≥

VBATREG, IBAT = IEOC, TJ < TSHDN

4 — Charger is in done mode, CHG_OK = 0, VBATT >

VBATREG-VRESTART, TJ < TSHDN

5 — Reserved

6 — Charger is in timer fault mode, CHG_OK = 0, VBATT <

VBATOV, if BAT_SNS = 0b001 then VBATT < VBATPC, TJ <

TSHDN

7 — Charger is in thermistor suspend mode, CHG_OK =

0, VBATT < VBATOV, if BAT_SNS = 0b001 then VBATT <

VPRECHG.LB, TJ < TSHDN

8 — Charger is off, input invalid and/or charger is disabled,

CHG_OK = 0

9 — Battery overvoltage condition

10 — Charger is off and TJ > TSHDN, CHG_OK = 0

000011 — Reserved

12 — Charger block is in Linear only mode, not charging,

CHG_OK = 0

13 — Reserved

14 — Reserved

15 — Reserved

Reset condition — VCOREDIG_RSTB

RSVD4 4 R 0 Unused

WDT_SNS 5 R 0 Watchdog sense bit

0 — Watchdog timer has not expired

1 — Charger is off because the watchdog timer expired,

CHG_OK = 0

Reset condition — VCOREDIG_RSTB

THM_SNS 6 R 0 Cool/Warm sense bit

0 — Thermistor temperature is between cool and warm

thresholds

1 — Thermistor temperature is < Cool, or > Warm threshold

Reset condition — VCOREDIG_RSTB

TREG_SNS 7 R 0 Temperature regulation sense

0 — The junction temperature is less than the threshold set by

REGTEMP and the full charge current limit is available

1 — The junction temperature is greater than the threshold set by

REGTEMP and the charge current limit may be folding back to

reduce power dissipation

Reset condition — VCOREDIG_RSTB

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 153. Register BATT_SNS - ADDR 0x08

Name Bit R/W Default Description

BATT_SNS 2 to 0 R 000 0 — 0x00 = No valid VBUS input

1 — 0x01 = VBATT < VPRECHG.LB

2 — 0x02 = the battery cannot charge beyond the precharge

threshold and charging has suspended and is in timer fault mode.

This condition is also reported in the CHG_SNS as 0x06.

3 — Reserved

4 — 0x04 = VPRECHG.LB < VBATT

5 — 0x05 = the battery voltage is greater than the battery

overvoltage flag threshold (VBATOV). Note that this flag is only be

generated when there is a valid input.

6 — 0x06 = battery not detected with a valid input and after

system wake-up

7 — Reserved

Reset condition — VCOREDIG_RSTB

RSVD3 4 to 3 RW 00 Unused

BATTOC_SNS 5 R 0 VBATT to VSYS overcurrent fault

0 — No fault

1 — VBATT to VSYS in high current fault

Reset condition — VCOREDIG_RSTB

RSVD6 7 to 6 RW 00 Unused

Table 154. Register CHG_OPER- ADDR 0x09

Name Bit R/W Default Description

CHG_OPER 1 to 0 RW1S[1] 01 Charger operation configuration

0 — charger = off, linear = off. The BATFET switch is on to allow

the battery to support the system.

1 — charger = off, linear = on. When there is a valid VBUS input

and no battery, the linear regulator regulates the VSYS voltage to

VSYSMIN[1:0].

2 — charger = on, linear = on. When there is a valid input, the

battery is charging. VSYS is the larger of VSYSMIN and VBATT +

IBAT * RBATFET.

3 — Reserved

Reset condition — VCOREDIG_RSTB

UNUSED 2 RW 0 Unused

WDTEN 3 RW 0 Enable watchdog timer bit. While enabled, the system controller

must reset the watchdog timer within the timer period (tWD) for

the charger to operate normally. Reset the watchdog timer by

programming WDTCLR = 0x01.

0 — Watchdog timer disabled

1 — Watchdog timer enabled

Reset condition — VCOREDIG_RSTB

DISBATFET 4 RW 0 VBATT to VSYS FET disable control

0 — VBATT to VSYS FET is controlled by internal state machine

1 — VBATT to VSYS FET is forced off

Reset condition — VCOREDIG_RSTB

UNUSED 7 to 5 RW 000 Unused

[1] Load from OTP fuse, Read and Write

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 155. Register CHG_TMR - ADDR 0x0A

Name Bit R/W Default Description

FCHGTIME 2 to 0 RW1S 010 Fast-charge timer duration (tFC)

0 — Disable

1 — 2 hrs

2 — 4 hrs

3 — 6 hrs

4 — 8 hrs

5 — 10 hrs

6 — 12 hrs

7 — 14 hrs

Reset condition — VCOREDIG_RSTB

EOCTIME 5 to 3 RW1S 001 End-of-charge timer setting

0 — 0 min (16 secs debounce)

1 — 10 min

2 — 20 min

3 — 30 min

4 — 40 min

5 — 50 min

6 — 60 min

7 — 70 min

Reset condition — VCOREDIG_RSTB

RSVD6 6 R 0 Unused

TPRECHG 7 RW1S 0 Precharge timer value. Used for low battery.

0 — Precharge timer value = 30 min

1 — Precharge timer value = 45 min

Reset condition — VCOREDIG_RSTB

Table 156. Register CHG_EOC_CNFG - ADDR 0x0D

Name Bit R/W Default Description

CHG_RESTART 1 to 0 RW1S 01 Charger restart threshold

00 — 0x00 = 100 mV below the value programmed by

CHG_CV_PRM

01 — 0x01 = 150 mV below the value programmed by

CHG_CV_PRM

02 — 0x02 = 200 mV below the value programmed by

CHG_CV_PRM

03 — 0x03 = disabled

Reset condition — VCOREDIG_RSTB

FORCE_BATT_ISO 2 RW1S 0 Unused

EOC_EXIT 3 RW1S 0 Unused

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Name Bit R/W Default Description

IEOC 6 to 4 RW 100 End-of-charge current threshold. End-of-charge occurs during

fast-charge constant voltage mode and end-of-charge current

measured as battery decays to the value programmed in this

0 — 5 mA

1 — 10 mA

2 — 20 mA

3 — 30 mA

4 — 50 mA

5 — Reserved

6 — Reserved

7 — Reserved

Reset condition — VCOREDIG_RSTB

EOC_MODE 7 RW1S 0 Unused

Table 157. Register CHG_CURR_CNFG - ADDR 0x0E

Name Bit R/W Default Description

CHG_CC 4 to 0 RW1S 00000 Fast charge current selection. When the charger is enabled, the

charge current limit is set by these bits. These bits range from

100 mA to 1.0 A.

0 — 100 mA

1 — 150 mA

2 — 200 mA

3 — 250 mA

4 — 300 mA

5 — 350 mA

6 — 400 mA

7 — 450 mA

8 — 500 mA

9 — 550 mA

10 — 600 mA

11 — 650 mA

12 — 700 mA

13 — 750 mA

14 — 800 mA

15 — 850 mA

16 — 900 mA

17 — 950 mA

18 — 1000 mA

19 — 1050 mA (Reserved)

20 — 1100 mA (Reserved)

21 — 1150 mA (Reserved)

22 — 1200 mA (Reserved)

23 — 1250 mA (Reserved)

24 — 1300 mA (Reserved)

25 — 1350 mA (Reserved)

26 — 1400 mA (Reserved)

27 — 1450 mA (Reserved)

28 — 1500 mA (Reserved)

29 — 1550 mA (Reserved)

30 — 1600 mA (Reserved)

31 — 1650 mA (Reserved)

Reset condition — VCOREDIG_RSTB

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Name Bit R/W Default Description

PRECHGLB_THRS 6 to 5 RW1S 00 Precharge (low battery) charging voltage threshold setting

0 — 2.8 V

1 — 2.7 V (Reserved)

2 — 2.9 V (Reserved)

3 — 3.0 V (Reserved)

Reset condition — VCOREDIG_RSTB

RSVD7 7 RW 0 Reserved

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 158. Register BATT_REG - ADDR 0x0F

Name Bit R/W Default Description

CHGCV 5 to 0 RW1S 101011 Battery termination voltage setting

0 — 3.50 V

1 — 3.50 V

2 — 3.50 V

3 — 3.50 V

4 — 3.50 V

5 — 3.50 V

6 — 3.50 V

7 — 3.50 V

8 — 3.50 V

9 — 3.52 V

10 — 3.54 V

11 — 3.56 V

12 — 3.58 V

13 — 3.60 V

14 — 3.62 V

15 — 3.64 V

16 — 3.66 V

17 — 3.68 V

18 — 3.70 V

19 — 3.72 V

20 — 3.74 V

21 — 3.76 V

22 — 3.78 V

23 — 3.80 V

24 — 3.82 V

25 — 3.84 V

26 — 3.86 V

27 — 3.88 V

28 — 3.90 V

29 — 3.92 V

30 — 3.94 V

31 — 3.96 V

32 — 3.98 V

33 — 4.00 V

34 — 4.02 V

35 — 4.04 V

36 — 4.06 V

37 — 4.08 V

38 — 4.10 V

39 — 4.12 V

40 — 4.14 V

41 — 4.16 V

42 — 4.18 V

43 — 4.20 V

44 — 4.22 V

45 — 4.24 V

46 — 4.26 V

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Name Bit R/W Default Description

47 — 4.28 V

48 — 4.30 V

49 — 4.32 V

50 — 4.34 V

51 — 4.36 V

52 — 4.38 V

53 — 4.40 V

54 — 4.42 V

55 — 4.44 V

56 — 4.44 V

57 — 4.44 V

58 — 4.44 V

59 — 4.44 V

60 — 4.44 V

61 — 4.44 V

62 — 4.44 V

63 — 4.44 V

Reset condition — VCOREDIG_RSTB

VSYSMIN 7 to 6 RW1S 00 Minimum system regulation voltage (VSYSMIN)

0 — 3.5 V

1 — 3.7 V

2 — 4.3 V

3 — Reserved

Reset condition — VCOREDIG_RSTB

Table 159. Register BATFET_CNFG - ADDR 0x11

Name Bit R/W Default Description

WDTCLR 1 to 0 RW 00 Watchdog timer clear bits. Writing "01" to these bits clears the

watchdog timer when the watchdog timer is enabled.

0 — The watchdog timer is not cleared

1 — The watchdog timer is cleared

2 — The watchdog timer is not cleared

3 — The watchdog timer is not cleared

Reset condition — VCOREDIG_RSTB

WD_BATFET_OFF 2 RW 0 Watchdog timer BATFET control

0 — Not used in PF1550. See WDFLT_BFET_EN bit in

Fault_BATFET_CNFG register.

1 — Not used in PF1550. See WDFLT_BFET_EN bit in

Fault_BATFET_CNFG register.

Reset condition — VCOREDIG_RSTB

BOVRC_DISBATFET 3 RW1S 0 Disable BATFET in case of battery overcurrent limit

0 — Charger controls BATFET switch; BATFET will be turned off

in case of battery overcurrent occurs for 16 ms (default)

1 — BATFET will not be turned off when battery overcurrent

occurs. Charger operation remains undisturbed by overcurrent

event.

Reset condition — VCOREDIG_RSTB

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Name Bit R/W Default Description

BATFET_OC 5 to 4 RW1S 11 VBATT to VSYS FET overcurrent threshold, 2 bits adjustment

0 — Disabled

1 — 2.2 A typ

2 — 2.8 A typ

3 — 3.2 A typ

Reset condition — VCOREDIG_RSTB

WD_TIME 6 RW 0 Sets watchdog timer value

0 — 80 s

0 — 32 s

Reset condition — VCOREDIG_RSTB

BOVRC_NOVBUS 7 RW 0 Enables/disables battery overcurrent protection when no VBUS is

present

0 — Disables battery overcurrent protection when no VBUS is

present

1 — Enables battery overcurrent protection when no VBUS is

present

Reset condition — VCOREDIG_RSTB

Table 160. Register THM_REG_CNFG - ADDR 0x12

Name Bit R/W Default Description

THM_CNFG 1 to 0 RW1S 01 Thermistor configuration. 2 bits adjustment.

0 — Thermistor not in control of charger. TCOOL and TWARM

interrupts are still generated. Thermistor Suspend mode is not

entered in this setting. CC and CV values are not altered when

TCOOL/cold, TWARM/hot thresholds are crossed.

1 — Thermistor control in charger. Charging will be stopped when

battery temperature > THOT or < TCOLD.

2 — JEITA 1 settings - Thermistor control in charger. Charging

current and battery regulation voltage will be reduced at battery

temperature > TWARM and < TCOOL.

3 — JEITA 2 settings - Thermistor control in charger. Charging

current will be reduced at battery temperature > TWARM and <

TCOOL. Charger voltage is not changed.

Reset condition — VCOREDIG_RSTB

REGTEMP 3 to 2 RW1S 01 Junction temperature thermal regulation loop set point. 2-bit

adjustments. The charger's target current limit starts to fold

back and the TREG_SNS bit is set if the junction temperature is

greater than the REGTEMP set point.

0 — 80 °C

1 — 95 °C

2 — 110 °C

3 — 125 °C (Reserved)

Reset condition — VCOREDIG_RSTB

THM_COLD 4 RW1S 0 Thermistor cold temperature selection

0 — 0 °C

1 — –10 °C

Reset condition — VCOREDIG_RSTB

THM_HOT 5 RW1S 0 Thermistor hot temperature selection

0 — 60 °C

1 — 55 °C

Reset condition — VCOREDIG_RSTB

RSVD6 6 RW 0 Unused

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Name Bit R/W Default Description

TEMP_FB_EN 7 RW1S 0 Enable/disable thermal foldback current function

0 — Thermal foldback disabled

1 — Thermal foldback enabled

Reset condition — VCOREDIG_RSTB

Table 161. Register VBUS_INLIM_CNFG - ADDR 0x14

Name Bit R/W Default Description

RSVD0 2 to 0 RW 000 Unused

VBUS_LIN_ILIM 7 to 3 RW1S 01101 Maximum input current limit selection. 5 bit adjustment from 10

mA to 1500 mA.

0 — 10 mA

1 — 15 mA

2 — 20 mA

3 — 25 mA

4 — 30 mA

5 — 35 mA

6 — 40 mA

7 — 45 mA

8 — 50 mA

9 — 100 mA

10 — 150 mA

11 — 200 mA

12 — 300 mA

13 — 400 mA

14 — 500 mA

15 — 600 mA

16 — 700 mA

17 — 800 mA

18 — 900 mA

19 — 1000 mA

20 — 1500 mA

21 — Reserved

22 — Reserved

23 — Reserved

24 — Reserved

25 — Reserved

26 — Reserved

27 — Reserved

28 — Reserved

29 — Reserved

30 — Reserved

31 — Reserved

Reset condition — CHGPOK_RSTB

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 162. Register VBUS_LIN_DPM - ADDR 0x15

Name Bit R/W Default Description

VBUS_DPM_REG 2 to 0 RW1S 000 VBUS regulation voltage (DPM mode)

0 — 3.90 V

1 — 4.00 V

2 — 4.10 V

3 — 4.20 V

4 — 4.30 V

5 — 4.40 V

6 — 4.50 V

7 — 4.60 V

Reset condition — VCOREDIG_RSTB

PRECHGDBATT_T

HRSH

4 to 3 RW1S 00 Precharge threshold

0 — Reserved

1 — Reserved

2 — Reserved

3 — Reserved

VIN_DPM_STOP 5 RW1S 0 Dynamic input power management panic stop threshold

0 — 200 mV

1 — 250 mV

Reset condition — VCOREDIG_RSTB

RSVD6 6 R 0 Unused

FET_SCALE 7 RW1S 0 Enables/disables BATFET scaling

0 — Reserved

1 — Reserved

Reset condition — VCOREDIG_RSTB

Table 163. Register USB_PHY_LDO_CNFG - ADDR 0x16

Name Bit R/W Default Description

ACTDISPHY 0 RW1S 1 Active discharger enable bit for USBPHY

0 — No active discharge

1 — Active discharge when regulator disabled

Reset condition — VCOREDIG_RSTB

USBPHY 1 RW1S 0 USBPHY voltage setting register

0 — 3.3 V

1 — 4.9 V

Reset condition — VCOREDIG_RSTB

USBPHYLDO 2 RW1S 0 USBPHY LDO enable

0 — Disabled

0 — Enabled

Reset condition — VCOREDIG_RSTB

RSVD3 3 RW 0 Unused

RSVD4 5 to 4 RW 00 Unused

RSVD6 7 to 6 RW 00 Unused

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 164. Register DBNC_DELAY_TIME - ADDR 0x18

Name Bit R/W Default Description

VBUS_OV_TDB 1 to 0 RW1S 00 VBUS overvoltage debounce delay

0 — 10 µs (Reserved)

1 — 100 µs

2 — 1 ms

3 — 10 ms

Reset condition — VCOREDIG_RSTB

USB_PHY_TDB 3 to 2 RW1S 00 USBPHY debounce timer - not used in PF1550

0 — 0 ms

1 — 16 ms

2 — 32 ms

3 — Not used

Reset condition — VCOREDIG_RSTB

SYS_WKUP_DLY 5 to 4 RW1S 00 System wake-up time

0 — 8.0 ms

1 — 16 ms

2 — 32 ms

3 — 100 ms

Reset condition — VCOREDIG_RSTB

RSVD6 7 to 6 RW 00 Unused

Table 165. Register CHG_INT_CNFG - ADDR 0x19

Name Bit R/W Default Description

CHG_INT_GEN 0 RW1S 0 Determines if an interrupt is generated at every mode transition in

charger

0 — Interrupt is not generated at every mode transition except

transition from Fast Charge to CV

1 — Interrupt is generated at every mode transition (Fast Charge,

CV, EOC, DONE, No Charger)

Reset condition — VCOREDIG_RSTB

EOC_INT 1 RW1S 0 Interrupt bit generated at end-of-charge

0 — No interrupt bit is generated when end-of- charge current is

triggered

1 — Interrupt bit is generated when end-of-charge current is

triggered

Reset condition — VCOREDIG_RSTB

RSVD2 7 to 2 RW 000000 Unused

Table 166. Register THM_ADJ_SETTING - ADDR 0x1A

Name Bit R/W Default Description

THM_WARM 0 RW1S 0 Thermistor warm threshold setting

0 — 45 °C

1 — 50 °C

Reset condition — VCOREDIG_RSTB

THM_COOL 1 RW1S 0 Thermistor cool threshold setting

0 — 15 °C

1 — 10 °C

Reset condition — VCOREDIG_RSTB

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Name Bit R/W Default Description

CV_ADJ 3 to 2 RW1S 00 JEITA Thermistor battery termination voltage subtraction setting

0 — 60 mV

1 — 100 mV

2 — 160 mV

3 — 200 mv

Reset condition — VCOREDIG_RSTB

CC_ADJ 5 to 4 RW1S 00 JEITA Thermistor battery charging current setting (percentage of

I_FC)

0 — 25 %

1 — 50 %

2 — 75 %

3 — 100 %

Reset condition — VCOREDIG_RSTB

RSVD6 7 to 6 RW 00 Unused

Table 167. Register VBUS2SYS_CNFG - ADDR 0x1B

Name Bit R/W Default Description

VBUS2SYS_TDB 1 to 0 RW1S 00 VBUS to VSYS comparator debounce time

0 — Reserved

1 — 100 µs

2 — 1 ms

3 — 10 ms

Reset condition — VCOREDIG_RSTB

VBUS2SYS_THRSH 2 RW1S 0 VBUS to VSYS comparator threshold setting

0 — 50 mV

1 — 175 mV

Reset condition — VCOREDIG_RSTB

RSVD3 7 to 3 RW 00000 Unused

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 168. Register LED_PWM - ADDR 0x1C

Name Bit R/W Default Description

LED_PWM 5 to 0 RW 000000 LED PWM duty cycle setting

0 — 0/32 (Off)

1 — 1/32

2 — 2/32

3 — 3/32

4 — 4/32

5 — 5/32

6 — 6/32

7 — 7/32

8 — 8/32

9 — 9/32

10 — 10/32

11 — 11/32

12 — 12/32

13 — 13/32

14 — 14/32

15 — 15/32

16 — 16/32

17 — 17/32

18 — 18/32

19 — 19/32

20 — 20/32

21 — 21/32

22 — 22/32

23 — 23/32

24 — 24/32

25 — 25/32

26 — 26/32

27 — 27/32

28 — 28/32

29 — 29/32

30 — 30/32

31 — 31/32

32 and higher — 32/32

Reset condition — VCOREDIG_RSTB

LED_RAMP 6 RW 0 Enable PWM ramp enable

0 — Ramp disable

1 — Ramp enable

Reset condition — VCOREDIG_RSTB

LED_EN 7 RW 0 LED driver enable

0 — Disabled

1 — Enabled

Reset condition — VCOREDIG_RSTB

Table 169. Register FAULT_BATFET_CNFG - ADDR 0x1D

Name Bit R/W Default Description

OVFLT_BFET_EN 0 RW1S 0 BATFET control during battery overvoltage

0 — BATFET is opened during battery overvoltage

1 — BATFET remains closed

Reset condition — VCOREDIG_RSTB

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Name Bit R/W Default Description

WDFLT_BFET_EN 1 RW1S 0 BATFET control during watchdog fault

0 — BATFET is opened during watchdog fault

1 — BATFET remains closed

Reset condition — VCOREDIG_RSTB

THMSUS_BFET_EN 2 RW1S 0 BATFET control during thermistor fault (< Cold or > Hot)

0 — BATFET is opened during battery thermistor fault

1 — BATFET remains closed

Reset condition — VCOREDIG_RSTB

TSHDN_BFET_EN 3 RW1S 0 BATFET control during thermal shutdown

0 — BATFET is opened during thermal shutdown

1 — BATFET remains closed

Reset condition — VCOREDIG_RSTB

TMRFLT_BFET_EN 4 RW1S 0 BATFET control during charger timer fault

0 — BATFET is opened during charger timer fault

1 — BATFET remains closed

Reset condition — POR

RSVD5 5 RW1S 0 Unused

CTRL_CHGR_BET A_

SEL

7 to 6 RW1S 00 Reserved

Table 170. Register LED_CNFG - ADDR 0x1E

Name Bit R/W Default Description

LED_FREQ 1 to 0 RW 00 LED driver PWM frequency setting

0 — 1.0 Hz

1 — 0.5 Hz

2 — 256 Hz

3 — 8.0 Hz

Reset condition — VCOREDIG_RSTB

LED_CURRENT 3 to 2 RW1S 00 LED driver current amplitude setting

0 — Reserved

1 — 6.0 mA

2 — Reserved

3 — Reserved

Reset condition — VCOREDIG_RSTB

LED_CFG 4 RW1S 0 Controls LED on/blinking mode

0 — LED on during charging; flashing during charger fault; off in

DONE state

1 — LED flashing during charging; on during charger fault; off in

DONE state

Reset condition — VCOREDIG_RSTB

LEDOVRD 5 RW 0 Enable software control of LED

0 — LED controlled by state machine

1 — LED controlled via software

Reset condition — VCOREDIG_RSTB

RSVD4 7 to 6 RW 00 Unused

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Table 171. Register LED_CNFG - ADDR 0x1F

Name Bit R/W Default Description

CHGR_KEY2 7 to 0 RW 0x00 Reserved

12.3 Register PMIC bitmap

VCOREDIG_PORB [1]

PS_END_RSTB [2]

REGS_DISABLE_TOG_RSTB [3]

[1] Bits reset by invalid VCOREDIG

[2] Bits reset by PORB or RESETBMCU

[3] Bits reset by pulse to REGS_DISABLE mode

Table 172. Register PMIC bitmap

BITS[7:0]Addre

76543210

Name FAMILY[3:7] DEVICE_ID[2:0]

Reset01111100

0x00 DEVICE_ID

TypeRRRRRRRR

Name — — OTP_FLAVOR[5:0]

Reset00000000

0x01 OTP_FLAVOR

Type — — R R R R R R

Name FAB_FIN[7:6] FULL_LAYER_REV[5:3] METAL_LAYER_REV[2:0]

Reset00001000

0x02 SILICON_REV

TypeRRRRRRRR

Name MISC_INT TEMP_INT ONKEY_INT LDO_INT SW3_INT SW2_INT SW1_INT CHG_INT

Reset00000000

0x06 INT_CATEGORY

TypeRRRRRRRR

Name — — — — — SW3_LS_I SW2_LS_I SW1_LS_I

Reset00000000

0x08 SW_INT_STAT0

Type — — — — — RW1C RW1C RW1C

Name — — — — — SW3_LS_M SW2_LS_M SW1_LS_M

Reset00000111

0x09 SW_INT_MASK0

Type — — — — — RW RW RW

Name — — — — — SW3_LS_S SW2_LS_S SW1_LS_S

Reset00000000

0x0A SW_INT_

SENSE0

Type — — — — — R R R

Name — — — — — SW3_HS_I SW2_HS_I SW1_HS_I

Reset00000000

0x0B SW_INT_STAT1

Type — — — — — RW1C RW1C RW1C

Name — — — — — SW3_HS_M SW2_HS_M SW1_HS_M

Reset00000111

0x0C SW_INT_MASK1

Type — — — — — RW RW RW

Name — — — — — SW3_HS_S SW2_HS_S SW1_HS_S

Reset00000000

0x0D SW_INT_

SENSE1

Type — — — — — R R R

Name — — — — — — SW2_DVS_

DONE_I

SW1_DVS_

DONE_I

Reset00000000

0x0E SW_INT_STAT2

Type — — — — — — RW1C RW1C

Name — — — — — — SW2_DVS_

DONE_M

SW1_DVS_

DONE_M

Reset00000011

0x0F SW_INT_MASK2

Type — — — — — — RW RW

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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BITS[7:0]Addre

76543210

Name — — — — — — SW2_DVS_S SW1_DVS_S

Reset00000000

0x10 SW_INT_

SENSE2

Type — — — — — — R R

Name — — — — — LDO3_FAULTI LDO2_FAULTI LDO1_FAULTI

Reset00000000

0x18 LDO_INT_

STAT0

Type — — — — — RW1C RW1C RW1C

Name — — — — — LDO3_FAULTM LDO2_FAULTM LDO1_FAULTM

Reset00000111

0x19 LDO_INT_

MASK0

Type — — — — — RW RW RW

Name — — — — — LDO3_FAULTS LDO2_FAULTS LDO1_FAULTS

Reset00000000

0x1A LDO_INT_

SENSE0

Type — — — — — R R R

Name — — — — — THERM125I — THERM110I

Reset00000000

0x20 TEMP_INT_

STAT0

Type — — — — — RW1C — RW1C

Name — — — — — THERM125M — THERM110M

Reset00001111

0x21 TEMP_INT_

MASK0

Type — — — — — RW — RW

0x22 TEMP_INT_

SENSE0

Name — — — — — THERM125S — THERM110S

Reset00000000

Type — — — — — R — R

Name — — ONKEY_8SI ONKEY_4SI ONKEY_3SI ONKEY_2SI ONKEY_1SI ONKEY_PUSHI

Reset00000000

0x24 ONKEY_INT_

STAT0

Type — — RW1C RW1C RW1C RW1C RW1C RW1C

Name — — ONKEY_8SM ONKEY_4SM ONKEY_3SM ONKEY_2SM ONKEY_1SM ONKEY_PUSHM

Reset00111111

0x25 ONKEY_INT_

MASK0

Type — — RW RW RW RW RW RW

Name — — ONKEY_8SS ONKEY_4SS ONKEY_3SS ONKEY_2SS ONKEY_1SS ONKEY_PUSHS

Reset00000000

0x26 ONKEY_INT_

SENSE0

Type — — R R R R R R

Name — — — SYS_OVLO_I LOW_SYS_

WARN_I

PWRON_I PWRDN_I PWRUP_I

Reset00000000

0x28 MISC_INT_

STAT0

Type — — — RW1C RW1C RW1C RW1C RW1C

Name — — — SYS_OVLO_M LOW_SYS_

WARN_M

PWRON_M PWRDN_M PWRUP_M

Reset00011111

0x29 MISC_INT_

MASK0

Type — — — RW RW RW RW RW

Name — — — SYS_OVLO_S LOW_SYS_

WARN_S

PWRON_S PWRDN_S PWRUP_S

Reset00000000

0x2A MISC_INT_

SENSE0

Type — — — R R R R R

Name COINCHEN VCOIN[3:0]

Reset00000000

0x30 COINCELL_

CONTROL

Type — — — RW RW RW RW RW

Name — — SW1_VOLT[5:0]

Reset00000000

0x32 SW1_VOLT

Type — — RW1S RW1S RW1S RW1S RW1S RW1S

Name — — SW1_STBY_VOLT[5:0]

Reset00000000

0x33 SW1_STBY_

VOLT

Type — — RW1S RW1S RW1S RW1S RW1S RW1S

Name — — SW1_SLP_VOLT[5:0]

Reset00000000

0x34 SW1_SLP_VOLT

Type — — RW1S RW1S RW1S RW1S RW1S RW1S

Name SW1_RDIS_ENB SW1_FPWM SW1_FPWM_

IN_DVS

SW1_

DVSSPEED

SW1_LPWR SW1_OMODE SW1_STBY_EN SW1_EN

Reset00000000

0x35 SW1_CTRL

Type RW1S RW RW RW1S RW RW RW1S RW1S

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

123 / 149

BITS[7:0]Addre

76543210

Name — — — SW1_TMODE_SEL — — SW1_ILIM[1:0]

Reset00000000

0x36 SW1_CTRL1

Type — — — RW — — RW1S RW1S

Name — — SW2_VOLT[5:0]

Reset00000000

0x38 SW2_VOLT

Type — — RW1S RW1S RW1S RW1S RW1S RW1S

Name — — SW2_STBY_VOLT[5:0]

Reset00000000

0x39 SW2_STBY_

VOLT

Type — — RW1S RW1S RW1S RW1S RW1S RW1S

Name — — SW2_SLP_VOLT[5:0]

Reset00000000

0x3A SW2_SLP_VOLT

Type — — RW1S RW1S RW1S RW1S RW1S RW1S

Name SW2_RDIS_ENB SW2_FPWM SW2_FPWM_

IN_DVS

SW2_

DVSSPEED

SW2_LPWR SW2_OMODE SW2_STBY_EN SW2_EN

Reset00000000

0x3B SW2_CTRL

Type RW1S RW RW RW1S RW RW RW1S RW1S

Name — — — SW2_TMODE_SEL — — SW2_ILIM[1:0]

Reset00000000

0x3C SW2_CTRL1

Type — — — RW — — RW1S RW1S

Name — — — — SW3_VOLT[3:0]

Reset00000000

0x3E SW3_VOLT

Type — — — — RW1S RW1S RW1S RW1S

Name — — — — SW3_STBY_VOLT[3:0]

Reset00000000

0x3F SW3_STBY_

VOLT

Type — — — — RW1S RW1S RW1S RW1S

Name — — — — SW3_SLP_VOLT[3:0]

Reset00000000

0x40 SW3_SLP_VOLT

Type — — — — RW1S RW1S RW1S RW1S

Name SW3_RDIS_ENB SW3_FPWM — SW3_

DVSSPEED

SW3_LPWR SW3_OMODE SW3_STBY_EN SW3_EN

Reset00000000

0x41 SW3_CTRL

Type RW1S RW — RW1S RW RW RW1S RW1S

Name — — — SW3_TMODE_SEL — — SW3_ILIM[1:0]

Reset00000000

0x42 SW3_CTRL1

Type — — — RW — — RW1S RW1S

Name — — LIBGDIS FORCEBOS CLKPULSE VSNVS_VOLT[2:0]

Reset00000000

0x48 VSNVS_CTRL

Type — — RW RW RW RW1S RW1S RW1S

Name — — — — VREFDDR_

LPWR

VREFDDR_

OMODE

VREFDDR_

STBY_EN

VREFDDR_EN

Reset00000000

0x4A VREFDDR_

CTRL

Type — — — — RW RW RW1S RW1S

Name — — — LDO1_VOLT[4:0]

Reset00000000

0x4C LDO1_VOLT

Type — — — RW1S RW1S RW1S RW1S RW1S

Name — — — LDO1_LS_EN LDO1_LPWR LDO1_OMODE LDO1_STB Y_EN VLDO1_EN

Reset00000000

0x4D LDO1_CTRL

Type — — — RW1S RW RW RW1S RW1S

Name — — — — LDO2_VOLT[3:0]

Reset00000000

0x4F LDO2_VOLT

Type — — — — RW1S RW1S RW1S RW1S

Name — — — — LDO2_LPWR LDO2_OMODE LDO2_STB Y_EN VLDO2_EN

Reset00000000

0x50 LDO2_CTRL

Type — — — — RW RW RW1S RW1S

Name — — — LDO3_VOLT[4:0]

Reset00000000

0x52 LDO3_VOLT

Type — — — RW1S RW1S RW1S RW1S RW1S

Name — — — LDO3_LS_EN LDO3_LPWR LDO3_OMODE LDO3_STB Y_EN VLDO3_EN

Reset00000000

0x53 LDO3_CTRL

Type — — — RW1S RW RW RW1S RW1S

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

124 / 149

BITS[7:0]Addre

76543210

Name TGRESET[7:6] POR_DLY[5:3] STANDBYINV STANDBYDLY[1:0]

Reset00000001

0x58 PWRCTRL0

Type RW1S RW1S RW1S RW1S RW1S RW RW RW

Name ONKEY_RST_EN REGSCPEN RESTARTEN PWRONRSTEN ONKEYDBNC[3:2] PWRONDBNC[1:0]

Reset10000000

0x59 PWRCTRL1

Type RW RW RW RW RW RW RW RW

Name — — — — LOW_SYS_WARN[3:2] UVDET[1:0]

Reset00000000

015A PWRCTRL2

Type — — — — RW RW RW1S RW1S

Name — GOTO_CORE_

OFF

GOTO_SHIP

Reset00000000

0x5B PWRCTRL3

Type RW RW RW RW RW RW RW RW

Name — — — — — SW1_PWRDN_SEQ[2:0]

Reset00000000

0x5F SW1_PWRDN_

SEQ

Type — — — — — RW1S RW1S RW1S

Name — — — — — SW2_PWRDN_SEQ[2:0]

Reset00000000

0x60 SW2_PWRDN_

SEQ

Type — — — — — RW1S RW1S RW1S

Name — — — — — SW3_PWRDN_SEQ[2:0]

Reset00000000

0x61 SW3_PWRDN_

SEQ

Type — — — — — RW1S RW1S RW1S

Name — — — — — LDO1_PWRDN_SEQ[2:0]

Reset00000000

0x62 LDO1_PWRDN_

SEQ

Type — — — — — RW1S RW1S RW1S

Name — — — — — LDO2_PWRDN_SEQ[2:0]

Reset00000000

0x63 LDO2_PWRDN_

SEQ

Type — — — — — RW1S RW1S RW1S

Name — — — — — LDO3_PWRDN_SEQ[2:0]

Reset00000000

0x64 LDO3_PWRDN_

SEQ

Type — — — — — RW1S RW1S RW1S

Name — — — — — VREFDDR_PWRDN_SEQ[2:0]

Reset00000000

0x65 VREFDDR_

PWRDN_S EQ

Type — — — — — RW1S RW1S RW1S

Name — — STATE[5:0]

Reset00000000

0x67 STATE_INFO

Type — — R R R R R R

Name USE_DEFAULT_

ADDR

— — — — I2C_SLAVE_ADDR_LSBS[2:0]

Reset00000000

0x68 I2C_ADDR

Type RW — — — — R R R

Name————————

Reset00000000

0x69 IO_DRV0

Type RW RW RW RW RW RW RW RW

Name————————

Reset00000000

0x6A IO_DRV1

Type — — — — — — RW RW

Name — — — — — REQ_ACORE_

HIPWR

REQ_ACORE_ON REQ_16MHZ

Reset00000000

0x6B RC_16MHZ

Type — — — — — RW RW RW

Name KEY1[7:0]

Reset00000000

0x6F KEY1

Type RW RW RW RW RW RW RW RW

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

125 / 149

12.4 Register charger bitmap

CHGPOK_RSTB [1]

VCOREDIG_RSTB [2]

[1] Bits reset by invalid VBUSIN

[2] Bits reset by invalid VCOREDIG

Table 173. Register charger bitmap

BITS[7:0]Address Register name

76543210

Name THM_I VBUS_DPM_I VBUS_I RSVD4 CHG_I BAT_I BAT2SOC_I SUP_I

Reset00000000

0x00 CHG_INT

Type RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1C

Name THM_M VBUS_DPM_M VBUS_M RSVD4 CHG_M BAT_M BAT2SOC_M SUP_M

Reset11111111

0x02 CHG_INT_MASK

Type RW RW RW RW RW RW RW RW

Name THM_OK VBUS_DPM_OK VBUS_OK RSVD4 CHG_OK BAT_OK BAT2SOC_OK SUP_OK

Reset10000100

0x04 CHG_INT_OK

TypeRRRRRRRR

Name VBUS_DPM_

SNS

RSVD6 VBUS_VALID_

SNS

VBUS_OVLO_

SNS

VBUS_IN2SYS_

SNS

VBUS_UVLO_

SNS

RSVD0[1:0]

Reset00001100

0x06 VBUS_SNS

TypeRRRRRRRR

Name TREG_SNS THM_SNS WDT_SNS RSVD4 CHG_SNS[3:0]

Reset00001000

0x07 CHG_SNS

TypeRRRRRRRR

Name RSVD6[7:6] BATTOC_SNS RSVD3[4:3] BATT_SNS[2:0]

Reset00000000

0x08 BATT_SNS

Type RW RW R RW RW R R R

Name RSVD5[7:5] DISBATFET WDTEN RSVD2 CHG_OPER[1:0]

Reset00000001

0x09 CHG_OPER

Type RW RW RW RW RW RW RW1S RW1S

Name TPRECHG RSVD6 EOCTIME[5:3]FCHGTIME[2:0]

Reset00001010

0x0A CHG_TMR

Type RW1S R RW1S RW1S RW1S RW1S RW1S RW1S

Name EOC_MODE IEOC[6:4] EOC_EXIT FORCE_BATT_

ISO

CHG_RESTART[1:0]

Reset01000001

0x0D CHG_EOC_CNFG

Type RW1S RW RW RW RW1S RW1S RW1S RW1S

Name RSVD7 PRECHGLB_THRSH[6:5] CHG_CC[4:0]

Reset00000000

0x0E CHG_CURR_CNFG

Type RW RW1S RW1S RW1S RW1S RW1S RW1S RW1S

Name MINVSYS[7:6] CHGCV[5:0]

Reset00101011

0x0F BATT_REG

Type RW1S RW1S RW1S RW1S RW1S RW1S RW1S RW1S

Name BOVRC_

NOVBUS

WD_TIME BATFET_OC[5:4] BOVRC_

DISBATFET

WD_BATFET_

OFF

WDTCLR[1:0]

Reset00110000

0x11 BATFET_CNFG

Type RW RW RW1S RW1S RW1S RW RW RW

Name TEMP_FB_EN RSVD6 THM_HOT THM_COLD REGTEMP[3:2] THM_CNFG[1:0]

Reset00000101

0x12 THM_REG_CNFG

Type RW1S RW RW1S RW1S RW1S RW1S RW1S RW1S

Name VBUS_LIN_ILIM[7:3] RSVD0[2:0]

Reset01101000

0x14 VBUS_INLIM_CNFG

Type RW1S RW1S RW1S RW1S RW1S RW RW RW

Name FET_SCALE RSVD6 VIN_DPM_

STOP

PRECHGDBATT_THRSH[4:3] VBUS_DPM_REG[2:0]

Reset00000000

0x15 VBUS_LIN_DPM

Type RW1S R RW1S RW1S RW1S RW1S RW1S RW1S

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

126 / 149

BITS[7:0]Address Register name

76543210

Name RSVD6[7:6] RSVD4[5:4] RSVD3 USBPHYLDO USBPHY ACTDISPHY

Reset00000001

0x16 USB_PHY_LDO_CNFG

Type RW RW RW RW RW RW1S RW1S RW1S

Name RSVD6[7:6] SYS_WKUP_DLY[5:4] USB_PHY_TDB[3:2] VBUS_OV_TDB[1:0]

Reset00000000

0x18 DBNC_DELAY_TIME

Type RW RW RW1S RW1S RW1S RW1S RW1S RW1S

Name RSVD2[7:2] EOC_INT CHG_INT_GEN

Reset00000000

0x19 CHG_INT_CNFG

Type RW RW RW RW RW RW RW1S RW1S

0x1A THM_ADJ_SETTING Name RSVD6[7:6] CC_ADJ[5:4] CV_ADJ[3:2] THM_COOL THM_WARM

Reset00000000

Type RW RW RW1S RW1S RW1S RW1S RW1S RW1S

Name RSVD3[7:3] VBUS2SYS_

THRSH

VBUS2SYS_TDB[1:0]

Reset00000000

0x1B VBUS2SYS_CNFG

Type RW RW RW RW RW RW1S RW1S RW1S

Name LED_EN LED_RAMP LED_PWM[5:0]

Reset00000000

0x1C LED_PWM

Type RW RW RW RW RW RW RW RW

Name CTRL_CHGR_BETA_SEL[7:6] RSVD5 TMRFLT_BFET_

TSHDN_BFET_

THMSUS_

BFET_EN

WDFLT_

BFEET_EN

OVFLT_BFEET_

Reset00000000

0x1D FAULT_BATFET_CNFG

Type RW1S RW1S RW1S RW1S RW1S RW1S RW1S RW1S

Name RSVD4[7:6] LEDOVRD LED_CFG LED_CURRENT[3:2] LED_FREQ[1:0]

Reset00000000

0x1E LED_CNFG

Type RW RW RW RW1S RW1S RW1S RW RW

Name CHGR_KEY2[7:0]

Reset00000000

0x1F CHGR_KEY2

Type RW RW RW RW RW RW RW RW

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

127 / 149

12.5 Register OTP bitmap

Table 174. Register OTP bitmap

BIT[7:0]Address Register name Value

7 6 5 4 3 2 1 0

0x1C OTP_PMIC_

CFG0

UNUSED UNUSED UNUSED OTP_PWRGD_

OTP_SEQ_

CLK_SPEED

OTP_PWRON_

CFG

A1 (Default) 0x00 0 0 0 0 0 0 0 0

A2 0x04 0 0 0 0 0 1 0 0

A3 0x04 0 0 0 0 0 1 0 0

A4 0x04 0 0 0 0 0 1 0 0

A5 0x04 0 0 0 0 0 1 0 0

A6 0x04 0 0 0 0 0 1 0 0

A7 0x04 0 0 0 0 0 1 0 0

A8 0x04 0 0 0 0 0 1 1 0

0x1D OTP_SW1 OTP_SW1_

DVSSPEED

OTP_SW1_RDIS_

ENB

OTP_SW1_VOLT[5:0]

A1 (Default) 0x80 1 0 0 0 0 0 0 0

A2 0xA0 1 0 1 0 0 0 0 0

A3 0XBF 1 0 1 1 1 1 1 1

A4 0XA8 1 0 1 0 1 0 0 0

A5 0XBF 1 0 1 1 1 1 1 1

A6 0XB6 1 0 1 1 0 1 1 0

A7 0XBF 1 0 1 1 1 1 1 1

A8 0XBF 1 0 1 1 1 1 1 1

0x1E OTP_SW1_SW2 OTP_SW2_VOLT[5:0] OTP_SW1_

DVS_SEL

OTP_SW1_

EN_AND_

STBY_EN

A1 (Default) 0XA3 1 0 1 0 0 0 1 1

A2 0x05 0 0 0 0 0 1 0 1

A3 0x09 0 0 0 0 1 0 0 1

A4 0xC1 1 1 0 0 0 0 0 1

A5 0x0D 0 0 0 0 1 1 0 1

A6 0x09 0 0 0 0 1 0 0 1

A7 0x05 0 0 0 0 0 1 0 1

A8 0x09 0 0 0 0 1 0 0 1

0x1F OTP_SW2_SW3 OTP_SW3_VOLT[3:0] OTP_SW2_

DVS_SEL

OTP_SW2_

EN_AND_

STBY_EN

OTP_SW2_

DVSSPEED

OTP_SW2_

RDIS_ENB

A1 (Default) 0x04 0 0 0 0 0 1 0 0

A2 0x0E 0 0 0 0 1 1 1 0

A3 0xFE 1 1 1 1 1 1 1 0

A4 0x06 0 0 0 0 0 1 1 0

A5 0xFE 1 1 1 1 1 1 1 0

A6 0xFE 1 1 1 1 1 1 1 0

A7 0x0E 0 0 0 0 1 1 1 0

A8 0xFE 1 1 1 1 1 1 1 0

0x20 OTP_SW3__

SWxILIM

OTP_SW3_ILIM[1:0] OTP_SW2_ILIM[1:0] OTP_SW1_ILIM[1:0] OTP_SW3_

EN_AND_

STBY_EN

OTP_SW3_

RDIS_ENB

A1 (Default) 0XFE 1 1 1 1 1 1 1 0

A2 0xFE 1 1 1 1 1 1 1 0

A3 0xFE 1 1 1 1 1 1 1 0

A4 0xFE 1 1 1 1 1 1 1 0

A5 0xFE 1 1 1 1 1 1 1 0

A6 0xFE 1 1 1 1 1 1 1 0

A7 0xFE 1 1 1 1 1 1 1 0

A8 0xFE 1 1 1 1 1 1 1 0

0x21 OTP_VREF_

LDO1

OTP_LDO1_LS_EN OTP_LDO1_VOLT[4:0] OTP_

VREFDDREN_

AND_STBY_EN

UNUSED

A1 (Default) 0x16 0 0 0 1 0 1 1 0

A2 0x42 0 1 0 0 0 0 1 0

A3 0x42 0 1 0 0 0 0 1 0

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

128 / 149

BIT[7:0]Address Register name Value

7 6 5 4 3 2 1 0

A4 0x7E 0 1 1 1 1 1 1 0

A5 0x42 0 1 0 0 0 0 1 0

A6 0x42 0 1 0 0 0 0 1 0

A7 0x7E 0 1 1 1 1 1 1 0

A8 0x42 0 1 0 0 0 0 1 0

0x22 OTP_LDO1_

LDO2

UNUSED OTP_LDO2_EN_

AND_STBY_EN

UNUSED OTP_LDO2_VOLT[3:0] OTP_LDO1_

EN_AND_

STBY_EN

A1 (Default) 0x4F 0 1 0 0 1 1 1 1

A2 0x5F 0 1 0 1 1 1 1 1

A3 0x5F 0 1 0 1 1 1 1 1

A4 0x5F 0 1 0 1 1 1 1 1

A5 0x5F 0 1 0 1 1 1 1 1

A6 0x5F 0 1 0 1 1 1 1 1

A7 0x5F 0 1 0 1 1 1 1 1

A8 0x5F 0 1 0 1 1 1 1 1

0x23 OTP_LDO3 UNUSED OTP_LDO3_

EN_AND_

STBY_EN

OTP_LDO3_

LS_EN

OTP_LDO3_VOLT[4:0]

A1 (Default) 0x65 0 1 1 0 0 1 0 1

A2 0x50 0 1 0 1 0 0 0 0

A3 0x5F 0 1 0 1 1 1 1 1

A4 0x50 0 1 0 1 0 0 0 0

A5 0x5F 0 1 0 1 1 1 1 1

A6 0x5F 0 1 0 1 1 1 1 1

A7 0x5F 0 1 0 1 1 1 1 1

A8 0x5F 0 1 0 1 1 1 1 1

0x24 OTP_PMIC_

CFG1

UNUSED OTP_UVDET[1:0] OTP_POR_DLY[2:0] OTP_TGRESET[1:0]

A1 (Default) 0x40 0 1 0 0 0 0 0 0

A2 0x40 0 1 0 0 0 0 0 0

A3 0x40 0 1 0 0 0 0 0 0

A4 0x40 0 1 0 0 0 0 0 0

A5 0x40 0 1 0 0 0 0 0 0

A6 0x40 0 1 0 0 0 0 0 0

A7 0x40 0 1 0 0 0 0 0 0

A8 0x40 0 1 0 0 0 0 0 0

0x25 OTP_SW1_

SW2_SEQ

UNUSED UNUSED OTP_SW2_PWRUP_SEQ[2:0] OTP_SW1_PWRUP_SEQ[2:0]

A1 (Default) 0x11 0 0 0 1 0 0 0 1

A2 0x2D 0 0 1 0 1 1 0 1

A3 0x1B 0 0 0 1 1 0 1 1

A4 0x1C 0 0 0 1 1 1 0 0

A5 0x1B 0 0 0 1 1 0 1 1

A6 0x1B 0 0 0 1 1 0 1 1

A7 0x1B 0 0 0 1 1 0 1 1

A8 0x1B 0 0 0 1 1 0 1 1

0x26 OTP_SW3_

LDO1_SEQ

UNUSED UNUSED OTP_LDO1_PWRUP_SEQ[2:0] OTP_SW3_PWRUP_SEQ[2:0]

A1 (Default) 0x23 0 0 1 0 0 0 1 1

A2 0x09 0 0 0 0 1 0 0 1

A3 0x1B 0 0 0 1 1 0 1 1

A4 0x0A 0 0 0 0 1 0 1 0

A5 0x1B 0 0 0 1 1 0 1 1

A6 0x1B 0 0 0 1 1 0 1 1

A7 0x1B 0 0 0 1 1 0 1 1

A8 0x1B 0 0 0 1 1 0 1 1

0x27 OTP_LDO2_

LDO3_SEQ

UNUSED UNUSED OTP_LDO3_PWRUP_SEQ[2:0] OTP_LDO2_PWRUP_SEQ[2:0]

A1 (Default) 0x2C 0 0 1 0 1 1 0 0

A2 0x09 0 0 0 0 1 0 0 1

A3 0x1A 0 0 0 1 1 0 1 0

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

129 / 149

BIT[7:0]Address Register name Value

7 6 5 4 3 2 1 0

A4 0x0A 0 0 0 0 1 0 1 0

A5 0x1A 0 0 0 1 1 0 1 0

A6 0x1A 0 0 0 1 1 0 1 0

A7 0x1A 0 0 0 1 1 0 1 0

A8 0x1A 0 0 0 1 1 0 1 0

0x28 OTP_PMIC_

CFG2

OTP_SHIP_

COREOFF_CYA

OTP_I2C_SLV_ADDR[2:0] OTP_I2C_

DEGLITCH_EN[0]

OTP_VREFDDR_PWRUP_SEQ[2:0]

A1 (Default) 0x05 0 0 0 0 0 1 0 1

A2 0x05 0 0 0 0 0 1 0 1

A3 0x03 0 0 0 0 0 0 1 1

A4 0x03 0 0 0 0 0 0 1 1

A5 0x03 0 0 0 0 0 0 1 1

A6 0x03 0 0 0 0 0 0 1 1

A7 0x03 0 0 0 0 0 0 1 1

A8 0x03 0 0 0 0 0 0 1 1

0x29 RSVD UNUSED UNUSED UNUSED UNUSED Reserved (OTP_VSNVS_VOLT[2:0]) Reserved

(OTP_FORCE_

LICELL)

A1 (Default) 0x00 0 0 0 0 0 0 0 0

A2 0x00 0 0 0 0 0 0 0 0

A3 0x00 0 0 0 0 0 0 0 0

A4 0x00 0 0 0 0 0 0 0 0

A5 0x00 0 0 0 0 0 0 0 0

A6 0x00 0 0 0 0 0 0 0 0

A7 0x00 0 0 0 0 0 0 0 0

A8 0x00 0 0 0 0 0 0 0 0

0x2A RSVD OTP_PMIC_SPARE0[7:0]

A1 (Default) 0x00 0 0 0 0 0 0 0 0

A2 0x00 0 0 0 0 0 0 0 0

A3 0x00 0 0 0 0 0 0 0 0

A4 0x00 0 0 0 0 0 0 0 0

A5 0x00 0 0 0 0 0 0 0 0

A6 0x00 0 0 0 0 0 0 0 0

A7 0x00 0 0 0 0 0 0 0 0

A8 0x00 0 0 0 0 0 0 0 0

0x2B OTP_CHG_CFG0 Reserved (OTP_

CHGR_

THM_WARM)

Reserved (OTP_

CHGR_

THM_COOL)

OTP_CHGR_EOCTIME[2:0] OTP_CHGR_

TPRECHG

OTP_CHGR_OPER[1:0]

A1 (Default) 0x02 0 0 0 0 0 0 1 0

A2 0x01 0 0 0 0 0 0 0 1

A3 0x02 0 0 0 0 0 0 1 0

A4 0x02 0 0 0 0 0 0 1 0

A5 0x02 0 0 0 0 0 0 1 0

A6 0x01 0 0 0 0 0 0 0 1

A7 0x02 0 0 0 0 0 0 1 0

A8 0x02 0 0 0 0 0 0 1 0

0x2C OTP_CHG_CFG1 OTP_CHGR_CHG_RESTART[1:0] Reserved (OTP_

CHGR_

FORCE_BATT_

ISO)

Reserved (OTP_

CHGR_

EOC_EXIT)

Reserved (OTP_

CHGR_

EOC_MODE)

OTP_CHGR_FCHGTIME[2:0]

A1 (Default) 0x00 0 0 0 0 0 0 0 0

A2 0x00 0 0 0 0 0 0 0 0

A3 0x00 0 0 0 0 0 0 0 0

A4 0x00 0 0 0 0 0 0 0 0

A5 0x00 0 0 0 0 0 0 0 0

A6 0x00 0 0 0 0 0 0 0 0

A7 0x00 0 0 0 0 0 0 0 0

A8 0x00 0 0 0 0 0 0 0 0

0x2D OTP_CHG_CFG2 OTP_CHGR_VSYSMIN[1:0] OTP_CHGR_CHG_CC[4:0] OTP_CHGR_

TEMPFB_EN

A1 (Default) 0x80 1 0 0 0 0 0 0 0

A2 0x80 1 0 0 0 0 0 0 0

A3 0x80 1 0 0 0 0 0 0 0

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

130 / 149

BIT[7:0]Address Register name Value

7 6 5 4 3 2 1 0

A4 0x90 1 0 0 1 0 0 0 0

A5 0x80 1 0 0 0 0 0 0 0

A6 0x40 0 1 0 0 0 0 0 0

A7 0x80 1 0 0 0 0 0 0 0

A8 0x80 1 0 0 0 0 0 0 0

0x2E OTP_CHG_CFG3 OTP_CHGR_BATFET_OC[1:0] OTP_CHGR_CHGCV[5:0]

A1 (Default) 0x2B 0 0 1 0 1 0 1 1

A2 0x2B 0 0 1 0 1 0 1 1

A3 0x2B 0 0 1 0 1 0 1 1

A4 0x2B 0 0 1 0 1 0 1 1

A5 0x2B 0 0 1 0 1 0 1 1

A6 0x2B 0 0 1 0 1 0 1 1

A7 0x2B 0 0 1 0 1 0 1 1

A8 0x2B 0 0 1 0 1 0 1 1

0x2F OTP_CHG_CFG4 UNUSED OTP_CHGR_THM_CNFG[1:0] OTP_CHGR_REGTEMP[1:0] OTP_CHGR_

THM_COLD

OTP_CHGR_

THM_HOT

OTP_CHGR_

BOVRC_

DISBATFET

A1 (Default) 0x00 0 0 0 0 0 0 0 0

A2 0x00 0 0 0 0 0 0 0 0

A3 0x00 0 0 0 0 0 0 0 0

A4 0x00 0 0 0 0 0 0 0 0

A5 0x00 0 0 0 0 0 0 0 0

A6 0x00 0 0 0 0 0 0 0 0

A7 0x00 0 0 0 0 0 0 0 0

A8 0x00 0 0 0 0 0 0 0 0

0x30 OTP_CHG_CFG5 UNUSED UNUSED OTP_CHGR_

VIN_DPM_STOP

OTP_CHGR_VBUS_LIN_ILIM[4:0]

A1 (Default) 0x0E 0 0 0 0 1 1 1 0

A2 0x14 0 0 0 1 0 1 0 0

A3 0x14 0 0 0 1 0 1 0 0

A4 0x14 0 0 0 1 0 1 0 0

A5 0x14 0 0 0 1 0 1 0 0

A6 0x14 0 0 0 1 0 1 0 0

A7 0x14 0 0 0 1 0 1 0 0

A8 0x14 0 0 0 1 0 1 0 0

0x31 OTP_CHG_CFG6 OTP_CHGR_SYS_WKUP_DLY[1:0] OTP_CHGR_

ACTDISPHY

OTP_CHGR_

USBPHY

OTP_CHGR_

USBPHYLDO

OTP_CHGR_VBUS_DPM_REG[2:0]

A1 (Default) 0x00 0 0 0 0 0 0 0 0

A2 0x28 0 0 1 0 1 0 0 0

A3 0x28 0 0 1 0 1 0 0 0

A4 0x2E 0 0 1 0 1 1 1 0

A5 0x28 0 0 1 0 1 0 0 0

A6 0x28 0 0 1 0 1 0 0 0

A7 0x28 0 0 1 0 1 0 0 0

A8 0x28 0 0 1 0 1 0 0 0

0x32 OTP_CHG_CFG7 OTP_CHGR_CC_ADJ[1:0] OTP_CHGR_

CHG_INT_EN

OTP_CHGR_

EOC_INT

OTP_CHGR_VBUS_OV_TDB[1:0] Reserved

(OTP_CHGR_USB_PHY_

TDB[1:0])

A1 (Default) 0x04 0 0 0 0 0 1 0 0

A2 0x04 0 0 0 0 0 1 0 0

A3 0x04 0 0 0 0 0 1 0 0

A4 0x14 0 0 0 1 0 1 0 0

A5 0x04 0 0 0 0 0 1 0 0

A6 0x04 0 0 0 0 0 1 0 0

A7 0x04 0 0 0 0 0 1 0 0

A8 0x04 0 0 0 0 0 1 0 0

0x33 OTP_CHG_CFG8 UNUSED OTP_CHGR_LED_CURRENT[1:0] OTP_CHGR_VBUS2SYS_TDB[1:0] OTP_CHGR_

VBUS2SYS_

THRSH

OTP_CHGR_CV_ADJ[1:0]

A1 (Default) 0x28 0 0 1 0 1 0 0 0

A2 0x28 0 0 1 0 1 0 0 0

A3 0x28 0 0 1 0 1 0 0 0

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

131 / 149

BIT[7:0]Address Register name Value

7 6 5 4 3 2 1 0

A4 0x28 0 0 1 0 1 0 0 0

A5 0x28 0 0 1 0 1 0 0 0

A6 0x28 0 0 1 0 1 0 0 0

A7 0x28 0 0 1 0 1 0 0 0

A8 0x28 0 0 1 0 1 0 0 0

0x34 OTP_CHG_CFG9 OTP_CHGR_LED_

CNFG

OTP_CHGR_OVFLT_

BFET_EN

OTP_CHGR_

WDFLT_BFET_

OTP_CHGR_

THMSUS_BFET_

OTP_CHGR_

TSHDN_BFET_

OTP_CHGR_

TMRFLT_

BFET_EN

Reserved

(OTP_CHGR_BETA_SEL[1:0])

A1 (Default) 0x00 0 0 0 0 0 0 0 0

A2 0x00 0 0 0 0 0 0 0 0

A3 0x00 0 0 0 0 0 0 0 0

A4 0x00 0 0 0 0 0 0 0 0

A5 0x00 0 0 0 0 0 0 0 0

A6 0x00 0 0 0 0 0 0 0 0

A7 0x00 0 0 0 0 0 0 0 0

A8 0x00 0 0 0 0 0 0 0 0

0x35 OTP_CHG_

CFG10

UNUSED UNUSED UNUSED Reserved (OTP_

CHGR_

FET_SCALE)

Reserved

(OTP_CHGR_PRECHG_

LOWBATT_THRSH[1:0])

OTP_CHGR_PRECHG_

LOWBATT_THRSH[1:0]

A1 (Default) 0x00 0 0 0 0 0 0 0 0

A2 0x00 0 0 0 0 0 0 0 0

A3 0x00 0 0 0 0 0 0 0 0

A4 0x00 0 0 0 0 0 0 0 0

A5 0x00 0 0 0 0 0 0 0 0

A6 0x00 0 0 0 0 0 0 0 0

A7 0x00 0 0 0 0 0 0 0 0

A8 0x00 0 0 0 0 0 0 0 0

0x36 RSVD OTP_CHGR_SPARE0[7:0]

A1 (Default) 0x00 0 0 0 0 0 0 0 0

A2 0x00 0 0 0 0 0 0 0 0

A3 0x00 0 0 0 0 0 0 0 0

A4 0x00 0 0 0 0 0 0 0 0

A5 0x00 0 0 0 0 0 0 0 0

A6 0x00 0 0 0 0 0 0 0 0

A7 0x00 0 0 0 0 0 0 0 0

A8 0x00 0 0 0 0 0 0 0 0

0x37 OTP_CRC_LSB CRC[1]LSB — — — — — — —

A1 (Default) 0xB5 1 0 1 1 0 1 0 1

A2 0xB5 1 0 1 1 0 1 0 1

A3 0xB5 1 0 1 1 0 1 0 1

A4 0xB5 1 0 1 1 0 1 0 1

A5 0xB5 1 0 1 1 0 1 0 1

A6 0xB5 1 0 1 1 0 1 0 1

A7 0xB5 1 0 1 1 0 1 0 1

A8 0xB5 1 0 1 1 0 1 0 1

13 Application details

13.1 Example schematic

Figure 28 shows a typical schematic of the PF1550 with key external components.

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

132 / 149

100 K

4.7 K 0.1 F

6.3 V

1.0 F

6.3 V

1.0 F

6.3 V

1.0 F

6.3 V

1.0 F

6.3 V

0.1 F

6.3 V

4.7 F

6.3 V

4.7 F

6.3 V

4.7 F

6.3 V

2.2 F

25 V

4.7 K

100 K100 K 100 K

PMIC_STBY_REQ

WDOG_B

PMIC_ON_REQ

POR_B

INTB (GPIO)

I2C SDA

i.MX 7ULP

(Interface)

i.MX 7ULP

(USB)

VBATT

I2C SCL

1.0 F

6.3 V

1.0 F

6.3 V

1.0 F

6.3 V

4.7 F

6.3 V

10 F

6.3 V

4.7 F

6.3 V

1.0 F

6.3 V

10 F

6.3 V

10 F

6.3 V

3.7 V

Li-Ion

CC charge

100 mA to

1.0 A

10 K

Battery pack

10 K thermistor

ONKEY

STANDBY

WDI

PWRON

INTB

RESETBMCU

THM

CV charge 3.5 V to 4.44 V

0.75 V to 3.3 V @ 300 mA

1.8 V to 3.3 V @ 400 mA

0.75 V to 3.3 V @ 300 mA

0.47 F

6.3 V

0.5 V to 0.9 V @ 10 mA

VSYS

1.8 V @ 1.0 A

1.0 H

1.0 H 10 F

6.3 V

10 F

6.3 V

1.2 V @ 1.0 A (DVS)

10 F

6.3 V

10 F

6.3 V

10 F

6.3 V

0.6 V to 1.3785 V @ 1.0 A (DVS)

22 F

10 V

22 F

10 V

4.2 V

5.0 V

1.8 V

3.3 V

VSYS

aaa-023890

1.0 H

GND

VBATT1

VBATT2

INT_2P7

SW1FB

VDD_DIG1

VDD_HSIC

VDD_PTC

VDD_PTD

0.9 V

1.8 V

1.2 V

3.3 V

1.8 V

VDD_RTC

VSYS1

VSYS2

VLDO1

VLDO3

VLDO2

VCORE

CHGB

VDIG

VDDOTP

VSNVS

VLDO1IN

VLDO2IN

VLDO3IN

VDDIO

SCL

SDA

VREFDDR

VINREFDDR

1.0 F

6.3 V

SW1LX

SW2FB

SW2LX

SW3FB

SW3LX

SW1IN

VBUSIN

USBPHY

SW2IN

SW3IN

LICELL

4.7 F

10 V

47 Ω

i.MX 7ULP

(Core)

PF1550

LPDDR2

Peripherals

UID

PHY PWR

VBUS

VSYS

D-

D+

GND

ON/OFF

Figure 28. Typical Schematic

13.2 Bill of materials

The table below shows an example bill of materials to be used with the PF1550.

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

133 / 149

Table 175. Bill of materials

Block Function Description Qty

VCORE Analog IC supply CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1

VDIG Digital IC supply CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1

INT2P7 Charger analog supply CAP CER 2.2 µF 6.3 V 20% X5R 0201 1

USBPHY USB PHY output capacitor CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1

VBUSIN VBUSIN bypass capacitor CAP CER 2.2 µF 25 V 20 % X5R 0402 1

VSYS VSYS capacitor 22 µF, 10 V, MLCC, X5R 2

VBATT Bypass capacitor between VBATT and

VSYS [1] 10 µF, 6.3 V, MLCC, X5R 1

VDDIO VDDIO bypass capacitor CAP CER 0.1 uF 6.3 V 20 % X5R 0201 1

THM Thermistor bias resistor 10 kOhm, 0201 1

BUCK1 inductor 1.0 µH, +/−20 %, 120 mOhm typ, 1700 mA 1

BUCK1 input capacitor 4.7 µF, 6.3 V, MLCC, X5R 1

Buck 1

BUCK1 output capacitor 10 µF, 6.3 V, MLCC, X5R 2

BUCK2 inductor 1.0 µH, +/−20 %, 120 mOhm typ, 1700 mA 1

BUCK2 input capacitor 4.7 µF, 6.3 V, MLCC, X5R 1

Buck 2

BUCK2 output capacitor 10 µF, 6.3V, MLCC, X5R 2

BUCK3 inductor 1.0 µH, +/-20 %, 120 mOhm typ, 1700 mA 1

BUCK3 input capacitor 4.7 µF, 6.3 V, MLCC, X5R 1

Buck 3

BUCK3 output capacitor 10 µF, 6.3 V, MLCC, X5R 2

LDO1 input capacitor CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1LDO1

LDO1 output capacitor 4.7 µF, 6.3 V, MLCC, X5R 1

LDO2 input capacitor CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1LDO2

LDO2 output capacitor 10 µF, 6.3 V, MLCC, X5R 1

LDO3 input capacitor CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1LDO3

LDO3 output capacitor 4.7 µF, 6.3 V, MLCC, X5R 1

VREFDDR input capacitor CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1VREFDDR

VREFDDR output capacitor CAP CER 1.0 µF 6.3 V 20 % X5R 0201 1

VSNVS VSNVS output capacitor CAP CER 0.47 µF 6.3 V 20 % X5R 0201 1

LICELL LICELL bypass capacitor CAP CER 0.1 µF 6.3 V 20 % X5R 0201 1

[1] ONLY for < 20mA EOC current threshold settings and to allow a smooth transition from CV to EOC state

13.3 PF1550 layout guidelines

13.3.1 General board recommendations

•It is recommended to use an eight layer board stack-up arranged as follows:

–High current signal

–GND

–Signal

–Power

–Signal

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

134 / 149

–GND

•Allocate TOP and BOTTOM PCB layers for POWER ROUTING (high current signals),

copper-pour the unused area.

•Use internal layers sandwiched between two GND planes for the SIGNAL routing.

13.3.2 Component placement

It is desirable to keep all component related to the power stage as close to the PMIC as

possible, specially decoupling input and output capacitors.

13.3.3 General routing requirements

•Some recommended things to keep in mind for manufacturability:

–Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than

the hole

–Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper

–Minimum allowed spacing between line and hole pad is 3.5 mils

–Minimum allowed spacing between line and line is 3.0 mils

•Care must be taken with SWxFB pins traces. These signals are susceptible to noise

and must be routed far away from power, clock, or high power signals, like the ones on

the SWxIN, SWxLX. They could be also shielded.

•Shield feedback traces of the regulators and keep them as short as possible (trace

them on the bottom so the ground and power planes shield these traces).

•Avoid coupling traces between important signal/low noise supplies (like VCORE, VDIG)

from any switching node (for example, SW1LX, SW2LX, SW3LX).

•Make sure that all components related to a specific block are referenced to the

corresponding ground.

13.3.4 Parallel routing requirements

•I2C signal routing

–CLK is the fastest signal of the system, so it must be given special care.

–To avoid contamination of these delicate signals by nearby high power or high

frequency signals, it is a good practice to shield them with ground planes placed on

adjacent layers. Make sure the ground plane is uniform throughout the whole signal

trace length.

–These signals can be placed on an outer layer of the board to reduce their

capacitance with respect to the ground plane.

–Care must be taken with these signals not to contaminate analog signals, as they are

high frequency signals. Another good practice is to trace them perpendicularly on

different layers, so there is a minimum area of proximity between signals.

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

135 / 149

DON’T

Signal

Ground plane Ground planes

aaa-023891

Figure 29. Recommended shielding for critical signals

13.3.5 Switching regulator layout recommendations

•Per design, the switching regulators in PF1550 are designed to operate with only one

input bulk capacitor. However, it is recommended to add a high frequency filter input

capacitor (CIN_hf), to filter out any noise at the regulator input. This capacitor should

be in the range of 100 nF and should be placed right next to or under the IC, closest to

the IC pins.

•Make high-current ripple traces low-inductance (short, high W/L ratio).

•Make high-current traces wide or copper islands.

COUT

CIN_HF CIN

VIN

SWxIN

SWxLX

SWxFB

Compensation

Driver

controller

aaa-023892

Figure 30. Generic buck regulator architecture

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

136 / 149

SWxFB

SWxLX

SWxIN

Route FB trace on any layer away from noisy nodes

VIN

CIN

COUT

CIN_HF VOUT

Inductor

GND

aaa-023893

Figure 31. Layout example for buck regulators

13.4 Thermal information

13.4.1 Rating data

The thermal rating data of the packages has been simulated with the results listed in

Table 3 .

Junction to Ambient Thermal Resistance Nomenclature: the JEDEC specification

reserves the symbol RθJA or θJA (Theta-JA) strictly for junction-to-ambient thermal

resistance on a 1s test board in natural convection environment. RθJMA or θJMA (Theta-

JMA) is used for both junction-to-ambient on a 2s2p test board in natural convection

and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is

anticipated that the generic name, Theta-JA, continues to be commonly used.

The JEDEC standards can be consulted at http://www.jedec.org/.

13.4.2 Estimation of junction temperature

An estimation of the chip junction temperature TJ can be obtained from the equation: TJ=

TA+ (RθJA x PD) with:

TA = Ambient temperature for the package in °C

RθJA = Junction to ambient thermal resistance in °C/W

PD= Power dissipation in the package in W

The junction to ambient thermal resistance is an industry standard value that provides a

quick and easy estimation of thermal performance. Unfortunately, there are two values

in common usage: the value determined on a single layer board RθJA and the value

obtained on a four layer board RθJMA. Actual application PCBs show a performance close

to the simulated four layer board value although this may be somewhat degraded in case

of significant power dissipated by other components placed close to the device.

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

137 / 149

At a known board temperature, the junction temperature TJ is estimated using the

following equation TJ= TB+ (RθJBx PD) with

TB = Board temperature at the package perimeter in °C

RθJB = Junction to board thermal resistance in °C/W

PD = Power dissipation in the package in W

14 Package outline

The PF1550 uses a 40-pin QFN 5.0 mm x 5.0 mm with exposed pad, case number

98ASA00913D.

This drawing is available for download at http://www.nxp.com.

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

138 / 149

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

139 / 149

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Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

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Figure 32. Package outline SOT1369-4 (QFN)

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

141 / 149

15 Revision history

Table 176. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PF1550 v.4.0 20180928 Advance information — PF1550 v.3.0

Modifications •Added MC32PF1550A0EP, MC32PF1550A8EP, MC34PF1550A0EP and MC34PF1550A8EP parts to

Table 1

•Added OTP configuration for A8 to Table 83

PF1550 v.3.0 20180502 Advance information — PF1550 v.2.0

Modifications •Changed PC parts to MC in Table 1

•Updated programming option for MC32PF1550A7EP and MC34PF1550A7EP (replaced LPDDR3 by

LPDDR2) in Table 1

•Updated SDA and SCL pin description in Table 2

•Updated A7 OTP configuration for OTP_SW3_VOLT[5:0] and OTP_LDO1_VOLT[4:0] registers

(replaced 3.3 V by 1.8 V and 1.8 V by 3.3 V) in Table 83 and modified Table 174 to reflect A7 OTP

option updates

•Updated min. and max. input current values in Table 6

PF1550 v.2.0 20180202 Advance information — PF1550 v.1.0

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

142 / 149

Document ID Release date Data sheet status Change notice Supersedes

Modifications •Updated Figure 10

•Updated Figure 28

•Updated description in Section 7.3.6 "LDO2 current limit protection"

•Changed capacitor value from 4.7 µF to 10 µF in Section 7.3.3 "LDO2 external components"

•Updated Figure 15, Figure 17, Figure 28

•Changed the value of LDO2 output capacitor from 4.7 µF to 10 µF in Table 175

•Updated Figure 3 (changed VUSB to VBUSIN

•Updated Figure 4 (changed VDO3IN to VLDO3IN)

•Corrected typos in Table 5, Table 6, Table 7, Table 8, Table 9, Table 10, Table 11, Table 13,

Table 14, Table 17, and Table 18

•Updated quiescent current ILDO1Q from 4.0 to 4.5 in Table 21 and added new parameter

•Updated and added new parameters to Table 19 and Table 20

•Updated values for ILDO2LIM in Table 22

•Updated quiescent current ILDO3Q from 4.0 to 4.5 in Table 23

•Updated typical and maximum value for REGS_DISABLE and SHIP MODE in Table 26

•Updated Section 6.3.3 "Output voltage setting in SW3"

•Updated Figure 12, Figure 13, and Figure 14

•Changed OTP_SW2_DVS_SEL to DVS mode for A4 configuration in Table 83

•Changed OTP configuration for SW1 to 1.3875 V in Table 83

•Updated Table 174 and Table 175

•Updated IQ_CHARGER_LQM max. value from 2.5 to 3.0 in Table 6

•Updated values for VSWx in Table 19

•Updated ILDO1Q and ILDO3Q values from 22 to 25 in Table 21 and Table 23

•Added part numbers to Table 1

•Updated typical value for tFC in Table 13

•Updated ISWxLIMH values in Table 19 and Table 20

•Updated Figure 16 and Figure 17

•Added Section 9.7

•Added OTP configuration for A5 to Table 83

•Updated Table 1

•Added A6 and A7 OTP configurations to Table 83

•Updated Figure 3, Figure 16, and Figure 28

•Added Figure 27

•Updated values for ISWxLIMH and ISW3LIMH in Table 19 and Table 20

•Added ripple parameter to Table 20

•Updated values for frequency in Table 72

•Updated Table 114, Table 119, Table 124, Table 165, and Table 172

•Updated Section 12.5

•Replaced MINVSYS by VSYSMIN

•Changed document status from Product preview to Advance information

PF1550 v.1.0 20161012 Product preview — —

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

143 / 149

16 Legal information

16.1 Data sheet status

Document status[1][2] Product status[3] Definition

[short] Data sheet: product preview Development This document contains certain information on a product under development.

NXP reserves the right to change or discontinue this product without notice.

[short] Data sheet: advance information Qualification This document contains information on a new product. Specifications and

information herein are subject to change without notice.

[short] Data sheet: technical data Production This document contains the product specification. NXP Semiconductors

reserves the right to change the detail specifications as may be required to

permit improvements in the design of its products.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences

of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a

technical data data sheet shall define the specification of the product as

agreed between NXP Semiconductors and its customer, unless NXP

Semiconductors and customer have explicitly agreed otherwise in writing.

In no event however, shall an agreement be valid in which the NXP

Semiconductors product is deemed to offer functions and qualities beyond

those described in the technical data data sheet.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

144 / 149

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor

tested in accordance with automotive testing or application requirements.

NXP Semiconductors accepts no liability for inclusion and/or use of non-

automotive qualified products in automotive equipment or applications. In

the event that customer uses the product for design-in and use in automotive

applications to automotive specifications and standards, customer (a) shall

use the product without NXP Semiconductors’ warranty of the product for

such automotive applications, use and specifications, and (b) whenever

customer uses the product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at customer’s own

risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,

damages or failed product claims resulting from customer design and use

of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

145 / 149

Tables

Tab. 1. Orderable part variations ...................................6

Tab. 2. Pin description ...................................................8

Tab. 3. Thermal ratings ................................................. 9

Tab. 4. Maximum ratings .............................................10

Tab. 5. Global conditions .............................................12

Tab. 6. Input currents .................................................. 12

Tab. 7. Internal 2.7 V Regulator (INT2P7) ...................13

Tab. 8. Switch impedances and leakage currents ....... 13

Tab. 9. Linear transients ..............................................14

Tab. 10. Charger characteristics ................................... 14

Tab. 11. Power-path management ................................ 15

Tab. 12. Watchdog timer ............................................... 15

Tab. 13. Charger timer .................................................. 15

Tab. 14. Battery overcurrent protection .........................15

Tab. 15. Thermal regulation .......................................... 16

Tab. 16. Battery thermistor monitor ............................... 16

Tab. 17. USBPHY LDO ................................................. 16

Tab. 18. LED characteristics ......................................... 17

Tab. 19. SW1 and SW2 electrical characteristics ..........17

Tab. 20. SW3 electrical characteristics ......................... 18

Tab. 21. LDO1 electrical characteristics ........................19

Tab. 22. LDO2 electrical characteristics ........................20

Tab. 23. LDO3 electrical characteristics ........................21

Tab. 24. VREFDDR electrical characteristics ................ 22

Tab. 25. VSNVS electrical characteristics ..................... 22

Tab. 26. IC level electrical characteristics ..................... 23

Tab. 27. Voltage regulators ........................................... 24

Tab. 28. SWx DVS setting selection ............................. 26

Tab. 29. Buck regulator operating modes ..................... 27

Tab. 30. Buck mode control .......................................... 27

Tab. 31. SW1 and SW2 output voltage setting ..............29

Tab. 32. Acceptable inductance and capacitance

values .............................................................. 31

Tab. 33. Example inductor part numbers ...................... 31

Tab. 34. Example capacitor part numbers .....................31

Tab. 35. SW3 buck regulator operating modes ............. 32

Tab. 36. SW3 buck mode control ..................................32

Tab. 37. SW3 output voltage setting ............................. 33

Tab. 38. Acceptable inductance and capacitance

values .............................................................. 34

Tab. 39. Example inductor part numbers ...................... 34

Tab. 40. Example capacitor part numbers .....................34

Tab. 41. LDOy output voltage setting ............................36

Tab. 42. LDOy control bits ............................................ 37

Tab. 43. LDO2 output voltage setting ............................39

Tab. 44. LDO2 control bits ............................................ 40

Tab. 45. Battery regulation voltage register ...................44

Tab. 46. VSYSMIN setting ............................................ 45

Tab. 47. Charger current control register ...................... 48

Tab. 48. Constant current charge settings .................... 48

Tab. 49. Battery regulation voltage register ...................50

Tab. 50. CV settings ......................................................50

Tab. 51. Charger timers register ................................... 52

Tab. 52. Fast charge timer settings ...............................52

Tab. 53. Charger EOC configuration register ................ 53

Tab. 54. EOC current thresholds ...................................53

Tab. 55. Charger timers register ................................... 53

Tab. 56. EOC state timer settings ................................. 54

Tab. 57. VBUS input current limit register ..................... 55

Tab. 58. Input current limit settings ............................... 56

Tab. 59. Thermal regulation .......................................... 57

Tab. 60. Temperature regulation control register .......... 59

Tab. 61. Thermal regulation settings .............................59

Tab. 62. VBUS linear dynamic input voltage register .... 61

Tab. 63. Input voltage regulation thresholds ................. 61

Tab. 64. JEITA thermal control ......................................62

Tab. 65. Temperature regulation control register .......... 62

Tab. 66. JEITA temperature control register ................. 63

Tab. 67. CV voltage adjustment settings .......................64

Tab. 68. CC current adjustment settings ....................... 64

Tab. 69. Battery overcurrent thresholds ........................ 66

Tab. 70. LED modes ..................................................... 67

Tab. 71. LED enable conditions .................................... 67

Tab. 72. LED frequency setting .....................................68

Tab. 73. PWRON pin OTP configuration options .......... 68

Tab. 74. PWRON pin logic level ....................................68

Tab. 75. PWRONDBNC settings ................................... 69

Tab. 76. Standby pin polarity control .............................69

Tab. 77. STANDBY pin logic level ................................ 69

Tab. 78. WDI pin logic level .......................................... 70

Tab. 79. ONKEY pin logic level .....................................71

Tab. 80. ONKEYDBNC settings .................................... 71

Tab. 81. State transition table ....................................... 75

Tab. 82. A4 startup and power down sequence timing ...78

Tab. 83. PF1550 start up configuration ......................... 78

Tab. 84. Register DEVICE_ID - ADDR 0x00 .................80

Tab. 85. Register OTP_FLAVOR - ADDR 0x01 ............ 80

Tab. 86. Register SILICON_REV - ADDR 0x02 ............ 80

Tab. 87. Register INT_CATEGORY - ADDR 0x06 ........ 80

Tab. 88. Register SW_INT_STAT0 - ADDR 0x08 ......... 81

Tab. 89. Register SW_INT_MASK0 - ADDR 0x09 ........ 81

Tab. 90. Register SW_INT_SENSE0 - ADDR 0x0A ...... 82

Tab. 91. Register SW_INT_STAT1 - ADDR 0x0B ......... 82

Tab. 92. Register SW_INT_MASK1 - ADDR 0x0C ........82

Tab. 93. Register SW_INT_SENSE1 - ADDR 0x0D ......83

Tab. 94. Register SW_INT_STAT2 - ADDR 0x0E ......... 83

Tab. 95. Register SW_INT_MASK2 - ADDR 0x0F ........ 84

Tab. 96. Register SW_INT_SENSE2 - ADDR 0x10 ...... 84

Tab. 97. Register LDO_INT_STAT0 - ADDR 0x18 ........84

Tab. 98. Register LDO_INT_MASK0 - ADDR 0x19 .......84

Tab. 99. Register LDO_INT_SENSE0 - ADDR 0x1A .... 85

Tab. 100. Register TEMP_INT_STAT0 - ADDR 0x20 ..... 85

Tab. 101. Register TEMP_INT_MASK0 - ADDR 0x21 .... 85

Tab. 102. Register TEMP_INT_SENSE0 - ADDR 0x22 ...86

Tab. 103. Register ONKEY_INT_STAT0 - ADDR 0x24 ... 86

Tab. 104. Register ONKEY_INT_MASK0 - ADDR

0x25 .................................................................87

Tab. 105. Register ONKEY_INT_SENSE0 - ADDR

0x26 .................................................................87

Tab. 106. Register MISC_INT_STAT0 - ADDR 0x28 ...... 88

Tab. 107. Register MISC_INT_MASK0- ADDR 0x29 ...... 89

Tab. 108. Register MISC_INT_SENSE0 - ADDR 0x2A ... 89

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

146 / 149

Tab. 109. Register COINCELL_CONTROL - ADDR

0x30 .................................................................90

Tab. 110. Register SW1_VOLT - ADDR 0x32 .................90

Tab. 111. Register SW1_STBY_VOLT - ADDR 0x33 ......90

Tab. 112. Register SW1_SLP_VOLT - ADDR 0x34 ........ 90

Tab. 113. Register SW1_CTRL - ADDR 0x35 .................90

Tab. 114. Register SW1_SLP_VOLT - ADDR 0x36 ........ 91

Tab. 115. Register SW2_VOLT - ADDR 0x38 .................92

Tab. 116. Register SW2_STBY_VOLT - ADDR 0x39 ......92

Tab. 117. Register SW2_SLP_VOLT - ADDR 0x3A ........92

Tab. 118. Register SW2_CTRL - ADDR 0x3B ................ 92

Tab. 119. Register SW2_CTRL1 - ADDR 0x3C .............. 93

Tab. 120. Register SW3_VOLT - ADDR 0x3E ................ 93

Tab. 121. Register SW3_STBY_VOLT - ADDR 0x3F ..... 94

Tab. 122. Register SW3_SLP_VOLT - ADDR 0x40 ........ 94

Tab. 123. Register SW3_CTRL - ADDR 0x41 .................94

Tab. 124. Register SW3_CTRL1 - ADDR 0x42 ...............95

Tab. 125. Register VSNVS_CTRL - ADDR 0x48 ............ 95

Tab. 126. Register VREFDDR_CTRL - ADDR 0x4A ....... 95

Tab. 127. Register LDO1_VOLT - ADDR 0x4C .............. 95

Tab. 128. Register LDO1_CTRL - ADDR 0x4D .............. 96

Tab. 129. Register LDO2_VOLT - ADDR 0x4F ...............96

Tab. 130. Register LDO2_CTRL - ADDR 0x50 ............... 96

Tab. 131. Register LDO3_VOLT - ADDR 0x52 ............... 97

Tab. 132. Register LDO3_CTRL - ADDR 0x53 ............... 97

Tab. 133. Register PWRCTRL0 - ADDR 0x58 ................ 97

Tab. 134. Register PWRCTRL1 - ADDR 0x59 ................ 98

Tab. 135. Register PWRCTRL2 - ADDR 0x5A ................99

Tab. 136. Register PWRCTRL3 - ADDR 0x5B ................99

Tab. 137. Register SW1_PWRDN_SEQ - ADDR 0x5F ... 99

Tab. 138. Register SW2_PWRDN_SEQ - ADDR 0x60 .. 100

Tab. 139. Register SW2_PWRDN_SEQ - ADDR 0x61 .. 100

Tab. 140. Register LDO1_PWRDN_SEQ - ADDR

0x62 ...............................................................101

Tab. 141. Register LDO2_PWRDN_SEQ - ADDR

0x63 ...............................................................101

Tab. 142. Register LDO3_PWRDN_SEQ - ADDR

0x64 ...............................................................102

Tab. 143. Register VREFDDR_PWRDN_SEQ - ADDR

0x65 ...............................................................102

Tab. 144. Register STATE_INFO - ADDR 0x67 ............103

Tab. 145. Register I2C_ADDR - ADDR 0x68 ................ 103

Tab. 146. Register RC_16MHZ - ADDR 0x6B .............. 103

Tab. 147. Register KEY1 - ADDR 0x6B ........................103

Tab. 148. Register CHG_INT - ADDR 0x00 .................. 104

Tab. 149. Register CHG_INT_MASK - ADDR 0x02 ...... 104

Tab. 150. Register CHG_INT_OK - ADDR 0x04 ........... 105

Tab. 151. Register VBUS_SNS - ADDR 0x06 ...............106

Tab. 152. Register CHG_SNS - ADDR 0x07 ................ 107

Tab. 153. Register BATT_SNS - ADDR 0x08 ............... 108

Tab. 154. Register CHG_OPER- ADDR 0x09 ...............108

Tab. 155. Register CHG_TMR - ADDR 0x0A ................109

Tab. 156. Register CHG_EOC_CNFG - ADDR 0x0D ....109

Tab. 157. Register CHG_CURR_CNFG - ADDR 0x0E .. 110

Tab. 158. Register BATT_REG - ADDR 0x0F ...............112

Tab. 159. Register BATFET_CNFG - ADDR 0x11 ........ 113

Tab. 160. Register THM_REG_CNFG - ADDR 0x12 .... 114

Tab. 161. Register VBUS_INLIM_CNFG - ADDR 0x14 ..115

Tab. 162. Register VBUS_LIN_DPM - ADDR 0x15 .......116

Tab. 163. Register USB_PHY_LDO_CNFG - ADDR

0x16 ...............................................................116

Tab. 164. Register DBNC_DELAY_TIME - ADDR

0x18 ...............................................................117

Tab. 165. Register CHG_INT_CNFG - ADDR 0x19 ...... 117

Tab. 166. Register THM_ADJ_SETTING - ADDR

0x1A .............................................................. 117

Tab. 167. Register VBUS2SYS_CNFG - ADDR 0x1B ... 118

Tab. 168. Register LED_PWM - ADDR 0x1C ............... 119

Tab. 169. Register FAULT_BATFET_CNFG - ADDR

0x1D .............................................................. 119

Tab. 170. Register LED_CNFG - ADDR 0x1E .............. 120

Tab. 171. Register LED_CNFG - ADDR 0x1F .............. 121

Tab. 172. Register PMIC bitmap ................................... 121

Tab. 173. Register charger bitmap ................................125

Tab. 174. Register OTP bitmap .....................................127

Tab. 175. Bill of materials ..............................................133

Tab. 176. Revision history .............................................141

Figures

Fig. 1. Application diagram ...........................................3

Fig. 2. Functional block diagram .................................. 4

Fig. 3. Internal block diagram .......................................5

Fig. 4. Pinout diagram .................................................. 7

Fig. 5. SWx DVS transitions .......................................26

Fig. 6. SWx DVS and non-DVS selection ...................27

Fig. 7. SW3 block diagram .........................................31

Fig. 8. LDOy Block Diagram .......................................36

Fig. 9. LDO2 block diagram ....................................... 39

Fig. 10. VREFDDR block diagram ............................... 41

Fig. 11. VSNVS block diagram .....................................41

Fig. 12. Battery charger internal block diagram ............42

Fig. 13. Charger low battery (Startup sequence,

USB insert, VBATT = 0 V) .............................. 43

Fig. 14. Charger healthy battery (Startup sequence,

USB insert, VBATT = 3.8 V) ........................... 44

Fig. 15. Input source detection delay ........................... 45

Fig. 16. Charger state diagram .................................... 46

Fig. 17. Charging profile ...............................................47

Fig. 18. Thermal regulation .......................................... 57

Fig. 19. Thermal regulation (Current versus Temp,

example with REGTEMP[1:0] = 00 and

hysteresis ........................................................ 58

Fig. 20. Thermal regulation (Current, Temp versus

Time, example with REGTEMP[1:0] = 00

and hysteresis ................................................. 58

Fig. 21. Response to input voltage droop during

charging ...........................................................60

Fig. 22. DPM function ...................................................61

Fig. 23. CC charge current and CV charge voltage

adjustment ....................................................... 63

Fig. 24. Response to battery overcurrent ..................... 66

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

147 / 149

Fig. 25. I2C sequence .................................................. 72

Fig. 26. PMIC state machine ........................................72

Fig. 27. A4 startup and power down sequence ............ 78

Fig. 28. Typical Schematic ......................................... 132

Fig. 29. Recommended shielding for critical signals ... 135

Fig. 30. Generic buck regulator architecture .............. 135

Fig. 31. Layout example for buck regulators .............. 136

Fig. 32. Package outline SOT1369-4 (QFN) .............. 138

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Data sheet: advance information Rev. 4.0 — 28 September 2018

148 / 149

Contents

1 General description ............................................ 1

1.1 Features and benefits ........................................1

1.2 Applications ........................................................2

2 Application diagram ............................................3

2.1 Functional block diagram ...................................4

2.2 Internal block diagram ....................................... 5

3 Orderable parts ................................................... 5

4 Pinning information ............................................ 7

4.1 Pinning ...............................................................7

4.2 Pin definitions .................................................... 8

5 General product characteristics ........................ 9

5.1 Thermal characteristics ......................................9

5.2 Absolute maximum ratings .............................. 10

5.3 Electrical characteristics .................................. 12

5.3.1 Electrical characteristics – Battery charger ...... 12

5.3.2 Electrical characteristics – SW1 and SW2 .......17

5.3.3 Electrical characteristics – SW3 ...................... 18

5.3.4 Electrical characteristics – LDO1 .....................19

5.3.5 Electrical characteristics – LDO2 .....................20

5.3.6 Electrical characteristics – LDO3 .....................21

5.3.7 Electrical characteristics – VREFDDR ............. 22

5.3.8 Electrical characteristics – VSNVS .................. 22

5.3.9 Electrical characteristics – IC level bias

currents ............................................................23

6 Detailed description ..........................................23

6.1 Buck regulators ................................................24

6.2 SW1 and SW2 detailed description ................. 25

6.2.1 SWx dynamic voltage scaling description ........25

6.2.2 SWx DVS and non-DVS operation .................. 26

6.2.3 Regulator control ............................................. 27

6.2.4 Current limit protection .................................... 28

6.2.5 Output voltage setting in SWx ......................... 28

6.2.6 SWx external components ...............................31

6.3 SW3 detailed description .................................31

6.3.1 Regulator control ............................................. 32

6.3.2 Current limit protection .................................... 33

6.3.3 Output voltage setting in SW3 .........................33

6.3.4 SW3 external components .............................. 34

7 Low dropout linear regulators, VREFDDR

and VSNVS ........................................................ 34

7.1 General description ..........................................34

7.2 LDO1 and LDO3 detailed description .............. 35

7.2.1 Features summary ...........................................35

7.2.2 LDOy block diagram ........................................ 36

7.2.3 LDOy external components ............................. 36

7.2.4 LDOy output voltage setting ............................ 36

7.2.5 LDOy low power mode operation .................... 37

7.2.6 LDOy current limit protection ........................... 37

7.2.7 LDOy load switch mode .................................. 38

7.3 LDO2 detailed description ............................... 38

7.3.1 LDO2 features summary ................................. 38

7.3.2 LDO2 block diagram ........................................39

7.3.3 LDO2 external components .............................39

7.3.4 LDO2 output voltage setting ............................ 39

7.3.5 LDO2 Low-power mode operation ...................40

7.3.6 LDO2 current limit protection ...........................40

7.4 VREFDDR reference ....................................... 40

7.5 VSNVS LDO/Switch .........................................41

8 Battery charger description ............................. 42

8.1 Operating modes and behavioral description ... 43

8.2 Charger input source detection ....................... 45

8.3 Input self-discharge for reliable charger input

interrupt ............................................................45

8.4 Charger state diagram .....................................46

8.5 Charging profile ............................................... 46

8.5.1 Precharge state ............................................... 47

8.5.2 Fast charge constant current state .................. 48

8.5.3 Fast charge constant voltage state ..................50

8.5.4 End-of-charge state ......................................... 53

8.5.5 Done state ....................................................... 54

8.6 Battery supplement mode ................................54

8.7 Power path features ........................................ 55

8.7.1 VSYS regulation .............................................. 55

8.7.2 Input current limit .............................................55

8.7.3 Battery thermistor ............................................ 56

8.7.4 BATFET soft start ............................................56

8.8 Thermal ............................................................57

8.8.1 Thermal regulation ...........................................57

8.8.2 Thermal foldback ............................................. 58

8.8.3 Input voltage regulation mode ......................... 59

8.8.4 JEITA thermal control ...................................... 62

8.9 Fault states ...................................................... 64

8.9.1 Timer fault state ...............................................64

8.9.2 Watchdog timer state .......................................65

8.9.3 Thermal shutdown state .................................. 65

8.9.4 Battery overvoltage state ................................. 65

8.9.5 Charger fault priority ........................................ 65

8.9.6 Battery overcurrent limit ...................................66

8.10 LED indicator ................................................... 67

9 Control and interface signals .......................... 68

9.1 PWRON ........................................................... 68

9.2 STANDBY ........................................................ 69

9.3 RESETBMCU .................................................. 69

9.4 INTB .................................................................70

9.5 WDI ..................................................................70

9.6 ONKEY ............................................................ 70

9.7 Control interface I2C block description ............ 71

9.7.1 I2C device ID ...................................................71

9.7.2 I2C operation ................................................... 71

10 PF1550 state machine ...................................... 72

10.1 System ON states ........................................... 73

10.1.1 Run state ......................................................... 73

10.1.2 STANDBY state ...............................................73

10.1.3 SLEEP state .................................................... 74

10.2 System OFF states ..........................................74

10.2.1 REGS_DISABLE ..............................................74

10.2.2 CORE_OFF ..................................................... 74

10.2.3 SHIP .................................................................74

10.3 Turn on events ................................................ 74

10.4 Turn off events ................................................ 75

10.5 State diagram and transition conditions ...........75

10.6 Regulator power-up sequencer ....................... 76

NXP Semiconductors PF1550

Power management integrated circuit (PMIC) for low power application processors

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 28 September 2018

Document identifier: PF1550

10.7 Regulator power-down sequencer ................... 77

11 Device start up .................................................. 77

11.1 Startup timing diagram .................................... 77

11.2 Device start up configuration ........................... 78

12 Register map ..................................................... 79

12.1 Specific PMIC Registers (Offset is 0x00) .........79

12.2 Specific Charger Registers (Offset is 0x80) ... 104

12.3 Register PMIC bitmap ................................... 121

12.4 Register charger bitmap ................................ 125

12.5 Register OTP bitmap ..................................... 127

13 Application details .......................................... 131

13.1 Example schematic ........................................131

13.2 Bill of materials .............................................. 132

13.3 PF1550 layout guidelines .............................. 133

13.3.1 General board recommendations .................. 133

13.3.2 Component placement ...................................134

13.3.3 General routing requirements ........................ 134

13.3.4 Parallel routing requirements .........................134

13.3.5 Switching regulator layout recommendations . 135

13.4 Thermal information .......................................136

13.4.1 Rating data .................................................... 136

13.4.2 Estimation of junction temperature ................ 136

14 Package outline ...............................................137

15 Revision history .............................................. 141

16 Legal information ............................................ 143