Vishay Siliconix
SiC402A, SiC402BCD
Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
www.vishay.com
15
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
Power Good Output
The PGOOD (power good) output is an open-drain output
which requires a pull-up resistor. When the voltage at the FB
pin is 10 % below the nominal voltage, PGOOD is pulled low.
It is held low until the output voltage returns above - 8 % of
nominal.
PGOOD will transition low if the VFB pin exceeds + 20 % of
nominal, which is also the over-voltage shutdown threshold.
PGOOD also pulls low if the EN/PSV pin is low when VDD is
present.
Output Over-Voltage Protection
Over-voltage protection becomes active as soon as the
device is enabled. The threshold is set at 600 mV + 20 %
(720 mV). When VFB exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains off, until the EN/PSV input is
toggled or VDD is cycled. There is a 5 µs delay built into the
OVP detector to prevent false transitions. PGOOD is also low
after an OVP event.
Output Under-Voltage Protection
When VFB falls 25 % below its nominal voltage (falls to
450 mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tri-state
the MOSFETs. The controller stays off until EN/PSV is
toggled or VDD is cycled.
VDD UVLO, and POR
UVLO (Under-Voltage Lock-Out) circuitry inhibits switching
and tri-states the DH/DL drivers until VDD rises above 3 V. An
internal POR (Power-On Reset) occurs when VDD exceeds
3 V, which resets the fault latch and a soft-start counter cycle
begins which prepares for soft-start. The SiC402A/B then
begins a soft-start cycle. The PWM will shut off if VDD falls
below 2.4 V.
LDO Regulator
SiC402A/B has an option to bias the switcher by using an
internal LDO from VIN. The LDO output is connected to VDD
internally. The output of the LDO is programmable by using
external resistors from the VDD pin to AGND (see figure 32).
The feedback pin (FBL) for the LDO is regulated to 750 mV.
The LDO output voltage is set by the following equation.
A minimum capacitance of 1 µF referenced to AGND is
normally required at the output of the LDO for stability.
Note that if the LDO voltage is set lower than 4.5 V, the
minimum output capacitance for the LDO is 10 µF.
LDO ENL Functions
The ENL input is used to enable/disable the internal LDO.
When ENL is a logic low, the LDO is off. When ENL is above
the VIN UVLO threshold, the LDO is enabled and the
switcher is also enabled if the EN/PSV and VDD are above
their threshold. The table below summarizes the function of
ENL and EN/PSV pins.
The ENL pin also acts as the switcher under-voltage lockout
for the VIN supply. When SiC402A/B is self-biased from the
LDO and runs from the VIN power source only, the VIN UVLO
feature can be used to prevent false UV faults for the PWM
output by programming with a resistor divider at the VIN, ENL
and AGND pins. When SiC402A/B has an external bias
voltage at VDD and the ENL pin is used to program the
VIN UVLO feature, the voltage at FBL needs to be higher
than 750 mV to force the LDO off.
Timing is important when driving ENL with logic and not
implementing VIN UVLO. The ENL pin must transition from
high to low within 2 switching cycles to avoid the PWM output
turning off. If ENL goes below the VIN UVLO threshold and
stays above 1 V, then the switcher will turn off but the LDO
will remain on.
LDO Start-Up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
1. ENL pin
2. VIN input voltage
When the ENL pin is high and VIN is above the UVLO point,
the LDO will begin start-up. During the initial phase, when the
VDD voltage (which is the LDO output voltage) is less than
0.75 V, the LDO initiates a current-limited start-up (typically
65 mA) to charge the output capacitors while protecting from
a short circuit event. When VDD is greater than 0.75 V but still
less than 90 % of its final value (as sensed at the FBL pin),
the LDO current limit is increased to ~ 115 mA. When VDD
has reached 90 % of the final value (as sensed at the FBL
pin), the LDO current limit is increased to ~ 200 mA and the
LDO output is quickly driven to the nominal value by the
internal LDO regulator. It is recommended that during LDO
Figure 32 - LDO Output Voltage Selection
VLDO = 750 mV x 1 + RLDO1
RLDO2
EN/PSV ENL LDO Switcher
Disabled Low, < 0.4 V Off Off
Enabled Low, < 0.4 V Off On
Disabled 1 V < High < 2.6 V On Off
Enabled 1 V < High < 2.6 V On Off
Disabled High, > 2.6 V On Off
Enabled High, > 2.6 V On On