IRFR9120, IRFU9120 Data Sheet 5.6A, 100V, 0.600 Ohm, P-Channel Power MOSFETs These advanced power MOSFETs are designed, tested, and guaranteed to withstand a specific level of energy in the avalanche breakdown mode of operation. They are P-Channel enhancement mode silicon gate power field effect transistors designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate-drive power. They can be operated directly from integrated circuits. Formerly developmental type TA17501. July 1999 3987.4 Features * 5.6A, 100V * rDS(ON) = 0.600 * Temperature Compensating PSPICETM Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol Ordering Information PART NUMBER File Number D PACKAGE BRAND IRFR9120 TO-252AA IF9120 IRFU9120 TO-251AA IF9120 G NOTE: When ordering use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, e.g., IRFR91209A. S Packaging JEDEC TO-251AA JEDEC TO-252AA SOURCE DRAIN GATE GATE SOURCE DRAIN (FLANGE) DRAIN (FLANGE) 4-83 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICETM is a trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRFR9120, IRFU9120 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg IRFR9120, IRFU9120 -100 -100 20 5.6 Refer to Peak Current Curve Refer to UIS Curve 42 0.33 -55 to 150 UNITS V V V A 300 260 oC oC W W/oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS ID = 250A, VGS = 0V -100 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250A -2.0 - -4.0 V VDS = Rated BVDSS, VGS = 0V - - -25 A VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 150oC - - -250 A VGS = 20V - - 100 nA rDS(ON) ID = 3.4A, VGS = -10V, (Figure 9) - - 0.600 W tON VDD = -50V, ID = 6.8A, RL = 7.1, VGS = -10V, RGS =18 (Figures 13, 16, 17) - - 60 ns Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current Drain to Source on Resistance (Note 2) IGSS Turn-On Time Turn-On Delay Time td(ON) - 9.6 - ns tr - 29 - ns td(OFF) - 21 - ns tf - 25 - ns Rise Time Turn-Off Delay Time TEST CONDITIONS Fall Time Turn-Off Time tOFF Total Gate Charge Qg Gate to Drain Charge Qgd Gate to Source Charge Qgs VGS = 0V to -10V VDD = -80V, ID = 5.6A, RL = 14.3 IG(REF) = 1.0mA - - 60 ns - - 18 nC - - 9 nC - - 3 nC Input Capacitance CISS - 485 - pF Output Capacitance COSS - 170 - pF Reverse Transfer Capacitance CRSS - 45 - pF VDS = -25V, VGS = 0V, f = 1MHz Thermal Resistance Junction to Case RJC - - 3.00 oC/W Thermal Resistance Junction to Ambient RJA - - 100 oC/W Source to Drain Diode Ratings and Specifications PARAMETER SYMBOL Source to Drain Diode Voltage (Note 2) Reverse Recovery Time VSD trr Reverse Recovery Charge QRR TEST CONDITIONS MIN TYP MAX UNITS ISD = -5.6A - - -6.3 V ISD = -6.8A, dISD/dt = -100A/s - 130 150 ns - 0.70 1.4 C NOTES: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) 4-84 IRFR9120, IRFU9120 Unless Otherwise Specified 1.2 -6 1.0 -5 ID , DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves 0.8 0.6 0.4 0.2 -4 -3 -2 -1 0 0 0 25 50 75 100 125 25 150 50 TC , CASE TEMPERATURE (oC) 75 100 125 150 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE ZJC , TRANSIENT THERMAL IMPEDANCE 10 0.5 1 0.2 0.1 PDM 0.05 0.1 0.02 0.01 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x Z JC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t1 , RECTANGULAR PULSE DURATION (s) FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE -30 -102 100s -10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) -1 10ms 100ms DC TC = 25oC TJ = MAX RATED -0.1 -1 -10 -100 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 4-85 IDM , PEAK CURRENT (A) ID , DRAIN CURRENT (A) VGS = -20V FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS: 150 - T C I = I 25 ---------------------- 125 -101 VGS = -10V TC = 25oC TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION -100 10-5 10-4 10-3 10-2 10-1 100 t, PULSE WIDTH (ms) FIGURE 5. PEAK CURRENT CAPABILITY 101 IRFR9120, IRFU9120 Unless Otherwise Specified EAS = 210mJ CONDITIONS: VDD = -25V, IAS = -5.6A, L = 10mH, STARTING TJ = 25oC -14 -10 STARTING TJ = 25oC STARTING TJ = 150oC If R = 0 (Continued) -12 -10 0.1 1 tAV, TIME IN AVALANCHE (ms) -8 VGS = -7V -6 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX -4 0 0 10 -3 NORMALIZED DRAIN TO SOURCE ON RESISTANCE IDS(ON), DRAIN TO SOURCE CURRENT (A) 150oC 2.0 -4 -6 -8 1.0 0.5 0 -80 -10 40 80 120 160 2.0 1.5 1.0 0.5 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs TEMPERATURE ID = -250A BREAKDOWN VOLTAGE NORMALIZED DRAIN TO SOURCE NORMALIZED GATE THRESHOLD VOLTAGE 0 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE VGS = VDS, ID = -250A 4-86 -40 TJ , JUNCTION TEMPERATURE (oC) FIGURE 8. TRANSFER CHARACTERISTICS 0 -10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -10V, ID = -3.4A VGS, GATE TO SOURCE VOLTAGE (V) -40 -8 1.5 0 0 -80 -6 FIGURE 7. SATURATION CHARACTERISTICS 25oC -55oC -6 2.0 -4 VDS, DRAIN TO SOURCE VOLTAGE (V) -9 -2 -2 2.5 VDD = -15V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0 VGS = -6V VGS = -5V VGS = -4.5V FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING -12 VGS = -8V TC = 25oC -2 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) If R 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] -1 0.01 VGS = -10V VGS = -20V ID, DRAIN CURRENT (A) IAS , AVALANCHE CURRENT (A) Typical Performance Curves 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE IRFR9120, IRFU9120 Unless Otherwise Specified (Continued) 500 VGS = 0V, f = 0.1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 400 300 COSS 200 CRSS 100 VDS , DRAIN TO SOURCE VOLTAGE (V) CISS C, CAPACITANCE (pF) -10 -100 600 -80 -10 -15 -20 -6 0.75 BVDSS 0.75 BVDSS -40 -4 0.50 BVDSS 0.50 BVDSS 0.25 BVDSS 0.25 BVDSS -2 -20 0 -5 -8 RL = 1.2 IG(REF) = -1.0mA VGS = -10V -60 0 0 VDD = BVDSS VDD =BVDSS -25 20 VDS , DRAIN TO SOURCE VOLTAGE (V) IG(REF) t, TIME (s) IG(ACT) 80 IG(REF) 0 IG(ACT) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS tAV L 0 VARY tP TO OBTAIN REQUIRED PEAK IAS - RG + 0V VGS VDD DUT VDD tP IAS IAS VDS tP 0.01 BVDSS FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(OFF) td(ON) tr 0 RL DUT VGS RG VDD + tf 10% 10% VDS VGS 0 90% 90% 10% 50% 50% PULSE WIDTH 90% FIGURE 16. RESISTIVE SWITCHING TEST CIRCUIT 4-87 FIGURE 17. RESISTIVE SWITCHING WAVEFORMS VGS , GATE TO SOURCE VOLTAGE (V) Typical Performance Curves IRFR9120, IRFU9120 PSPICE Electrical Model .SUBCKT IRFU9120 2 1 3 REV 9/16/94 CA 12 8 618.9e-12 CB 15 14 633.9e-12 CIN 6 8 441.1e-12 LDRAIN 5 10 5 51 9 1 VTO - 17 EBREAK 18 + - 16 DBODY MOS2 21 - 18 20 8 LGATE RDRAIN 6 8 EVTO + RGATE ESCL + ESG + GATE LDRAIN 2 5 1e-9 LGATE 1 9 2.609e-9 LSOURCE 3 7 2.609e-9 RSCL1 RSCL2 EBREAK 5 11 17 18 -127.38 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTO 20 6 8 18 1 IT 8 17 1 2 DRAIN DPLCAP DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 6 DPLCAPMOD 6 RIN 11 MOS1 DBREAK CIN 8 RSOURCE LSOURCE 3 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 245.6e-3 RGATE 9 20 2.69 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 123.96e-3 RVTO 18 19 RVTOMOD 1 S1A 12 CA 13 8 S1B 7 S2A 14 13 13 15 17 RBREAK S2B + 6 EGS 8 - SOURCE 18 RVTO CB 14 + 5 EDS 8 - IT 19 - VBAT + S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 -0.77 ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/13.2,6))} .MODEL DBDMOD D (IS=5.1e-14 RS=9.4e-2 TRS1=-2.2e-3 TRS2=-5.2e-6 CJO=6.43e-10 TT=9.7e-8) .MODEL DBKMOD D (RS=1.45 TRS1=3.84e-4 TRS2=-9.83e-6) .MODEL DPLCAPMOD D (CJO=235e-12 IS=1e-30 N=10) .MODEL MOSMOD PMOS (VTO=-3.49 KP=1.58 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=1.01e-3 TC2=1.05e-6) .MODEL RDSMOD RES (TC1=6.23e-3 TC2=1.23e-5) .MODEL RSCLMOD RES (TC1=2.05e-3 TC2=-0.35e-5) .MODEL RVTOMOD RES (TC1=-3.46e-3 TC2=3.33e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=6.3 VOFF=4.3) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.3 VOFF=6.3) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.0 VOFF=-4.0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=1.0) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley. 4-88 IRFR9120, IRFU9120 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. 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