May 2003 Advance Information AS7C331MPFS18A (R) 1M x 18 pipelined burst synchronous SRAM Features * * * * * * * * * * * * * * Organization: 1,048,576 x18 bits Fast clock speeds to 200MHz in LVTTL/LVCMOS Fast clock to data access: 3/3.4/3.8 ns Fast OE access time: 3/3.4/3.8 ns Fully synchronous register-to-register operation Single register flow-through mode Single-cycle deselect Asynchronous output enable control Available 100-pin TQFP and 165-ball BGA packages Byte write enables Multiple chip enables for easy expansion 3.3 V core power supply 2.5 V or 3.3V I/O operation with separate VDDQ NTDTM pipelined architecture available (AS7C331MNTD18A, AS7C33512NTD32A/ AS7C33512NTD36A) Logic block diagram LBO CLK ADV ADSC ADSP CLK CS CLR 20 A[19:0] 20 Q D CS 1M [ 18 Memory array Burst logic 18 20 Address register CLK 18 18 GWE BWb D DQb Q Byte Write registers BWE CLK D DQa Q 2 Byte Write registers BWa CLK CE0 CE1 CE2 D OE Enable Q register CE CLK ZZ Input registers Output registers CLK CLK D Enable Q Power down delay register CLK OE 18 FT DQ[a,b] Selection guide Minimum cycle time Maximum clock frequency Maximum pipelined clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 5/28/03, v. 052003 Advance Info -200 5 200 3.0 370 130 70 -166 6 166 3.4 340 120 70 Alliance Semiconductor -133 7.5 133 3.8 320 110 70 Units ns MHz ns mA mA mA 1 of 21 Copyright (c) Alliance Semiconductor. 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AS7C331MPFS18A (R) Pin and ball designations NC NC NC TQFP 14 x 20 mm 1M x 18 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQa DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC LBO A A A A A1 A0 NC NC VSS VDD A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb FT VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DQPb NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE0 CE1 NC NC BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A A Pin configuration for 100-pin TQFP Ball assignments for 165-ball BGA $ NC A CE0 BWb NC % NC A CE1 NC BWa CE2 BWE CLK GWE ADSC ADV A A OE ADSP A NC & NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPa ' NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa ( NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa ) NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa * NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa + FT NC NC VDD VSS VSS VSS VDD NC NC ZZ - DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC . DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC / DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC 0 DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC 1 DQPb NC VDDQ VSS NC A NC VSS VDDQ NC NC 3 NC NC A A TDI A11 TDO A A A A TMS A01 TCK A A A A 5 LBO NC A A 1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. 5/28/03, v. 052003 Advance Info Alliance Semiconductor 2 of 21 AS7C331MPFS18A (R) Functional description The AS7C331MPFS18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words X 18 bits and incorporates a two-stage register-register pipeline for highest frequency on any given technology. Fast cycle times of 5/6/7.5 ns with clock access times (tCD) of 3/3.4/3.8 ns enable 200, 166, and 133 MHz bus frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK is carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but it is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device uses a linear count sequence. Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signals. BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled low, regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally to the next burst address if BWn and ADV are sampled low. Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow. * ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC. * WE signals are sampled on the clock edge that samples ADSC low (and ADSP high). * Master chip enable CE0 blocks ADSP, but not ADSC. The AS7C331MPFS18A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin TQFP and 165-ball BGA. TQFP and BGA capacitance Parameter Input capacitance I/O capacitance Symbol Signals Test conditions Max Unit CIN CI/O Address and control pins I/O pins VIN = 0V VIN = VOUT 5 7 pF pF 5/28/03, v. 052003 Advance Info Alliance Semiconductor 3 of 21 AS7C331MPFS18A (R) Signal descriptions Signal CLK A0-A17 DQ[a,b] I/O I I I/O Properties CLOCK SYNC SYNC CE0 I SYNC CE1, CE2 I SYNC ADSP I SYNC ADSC ADV I I SYNC SYNC GWE I SYNC BWE I SYNC BW[a,b] I SYNC OE I ASYNC LBO I STATIC TDO TDI O I SYNC SYNC TMS I SYNC TCK O SYNC FT I STATIC ZZ I ASYNC Description Clock. All inputs except OE, FT, ZZ, and LBO are synchronous to this clock. Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted. Data. Driven as output when the chip is enabled and when OE is active. Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the "Synchronous truth table" for more information. Synchronous chip enables. Active high and active low, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. Address strobe processor. Asserted low to load a new bus address or to enter standby mode. Address strobe controller. Asserted low to load a new address or to enter standby mode. Advance. Asserted low to continue burst read/write. Global write enable. Asserted low to write all 32/36 and 18 bits. When high, BWE and BW[a,b] control write enable. Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs. Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of BW[a,b] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[AB] are inactive, the cycle is a read cycle. Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read mode. Count mode. When driven high, count sequence follows Intel XOR convention. When driven low, count sequence follows linear convention. This signal is internally pulled high.18 Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only). Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only). This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK (BGA only). Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only). Flow-through mode.When low, enables single register flow-through mode. Connect to VDD if unused or for pipelined operation. Sleep. Places device in low power mode; data is retained. Connect to GND if unused. Write enable truth table (per byte) Function Write all bytes (a, b) Write byte a Write byte b Read GWE L H H H H H BWE X L L L H L BWa X L L H X H BWb X L H L X H .H\X = don't care; L = low; H = high; BWE, BWn = internal write signal 5/28/03, v. 052003 Advance Info Alliance Semiconductor 4 of 21 AS7C331MPFS18A (R) Synchronous truth table CE0 H L L L L L L L L X X X X H H H H L X H X H CE1 X L L X X H H H H X X X X X X X X H X X X X CE2 X X X H H L L L L X X X X X X X X L X X X X ADSP X L H L H L L H H H H H H X X X X H H X H X ADSC L X L X L X X L L H H H H H H H H L H H H H ADV X X X X X X X X X L L H H L L H H X L L H H BWn1 X X X X X X X F F F F F F F F F F T T T T T OE X X X X X L H L H L H L H L H L H X X X X X Address accessed NA NA NA NA NA External External External External Next Next Current Current Next Next Current Current External Next Next Current Current CLK L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H Operation Deselect Deselect Deselect Deselect Deselect Begin read Begin read Begin read Begin read Continue read Continue read Suspend read Suspend read Continue read Continue read Suspend read Suspend read Begin write Continue write Continue write Suspend write Suspend write DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z2 Hi-Z Hi-Z2 Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z D3 D D D D 1 See "Write enable truth table" on page 4 for more information. 2 Q in flow-through mode. 3 For a write operation following a read operation, OE must be high before the input data set up time and must be held high throughout the input hold time Key: X = don't care, L = low, H = high TQFP and BGA thermal resistance Description Thermal resistance (junction to ambient)1 1 layer 4 layer Thermal resistance (junction to top of case)1 Symbol JA JA Typical 40 22 C/W Units JC 8 C/W C/W Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 1 This parameter is sampled. 5/28/03, v. 052003 Advance Info Alliance Semiconductor 5 of 21 AS7C331MPFS18A (R) Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation DC output current Storage temperature (plastic) Temperature under bias Symbol VDD, VDDQ VIN VIN PD IOUT Tstg Tbias Min -0.5 -0.5 -0.5 - - -65 -65 Max +4.6 VDD + 0.5 VDDQ + 0.5 1.8 20 mA +150 +135 Unit V V V W mA o C o C Note: Stresses greater than those listed in this table may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability. Recommended operating conditions Parameter Supply voltage 3.3V I/O supply voltage 2.5V I/O supply voltage Input voltages1 Address and control pins I/O pins Ambient operating temperature Symbol VDD VSS VDDQ VSSQ VDDQ VSSQ VIH VIL VIH VIL TA Min 3.135 0.0 3.135 0.0 2.35 0.0 2.0 -0.32 2.0 -0.5 0 Nominal 3.3 0.0 3.3 0.0 2.5 0.0 - - - - - Max 3.6 0.0 3.6 0.0 2.9 0.0 VDD + 0.3 0.8 VDDQ + 0.3 0.8 70 Unit V V V V V C 1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications. 2 VIL min = -2.0V for pulse width less than 0.2 x tRC. 5/28/03, v. 052003 Advance Info Alliance Semiconductor 6 of 21 AS7C331MPFS18A (R) DC electrical characteristics for 3.3V I/O operation Parameter Input leakage current1 Output leakage current -200 -166 -133 Min Max Min Max Min Max Unit Sym Test conditions |ILI| VDD = Max, VIN = GND to VDD -2 2 -2 2 -2 2 A |ILO| OE VIH, VDD = Max, VOUT = GND to VDD -2 2 -2 2 -2 2 A - 370 - 340 - 320 mA - 320 - 275 - 250 mA - 130 - 120 - 110 - 70 - 70 - 70 - 60 - 60 - 60 - 2.4 0.4 - - 2.4 0.4 - - 2.4 0.4 - Operating power supply current2 ICC (Pipelined) Operating power supply current2 ICC (Flow-through) ISB Standby power supply current ISB1 ISB2 VOL VOH Output voltage CE0 = VIL, CE1 = VIH, CE2 = VIL, f = fMax, IOUT = 0 mA Deselected, f = fMax, ZZ VIL Deselected, f = 0, ZZ 0.2V all VIN 0.2V or VDD - 0.2V Deselected, f = fMax, ZZ VDD - 0.2V All VIN VIL or VIH IOL = 8 mA, VDDQ = 3.465V IOH = -4 mA, VDDQ = 3.135V mA V 1 LBO, FTX, and ZZX pins and the 165 BGA JTAG pins (TMSX, TDIX, and TCKX) have an internal pull-up, and input leakage = 10 a. 2 ICC given with no output loading. ICC increases with faster cycle times and greater output loading. DC electrical characteristics for 2.5V I/O operation Parameter Output leakage current Output voltage Sym |ILO| VOL VOH Test conditions OE VIH, VDD = Max, VOUT = GND to VDD IOL = 2 mA, VDDQ = 2.65V IOH = -2 mA, VDDQ = 2.35V 5/28/03, v. 052003 Advance Info -200 Min Max -166 Min Max -133 Min Max Unit -1 1 -1 1 -1 1 A - 1.7 0.7 - - 1.7 0.7 - - 1.7 0.7 - V Alliance Semiconductor 7 of 21 AS7C331MPFS18A (R) Timing characteristics over operating range Parameter Sym Clock frequency fMax Cycle time (pipelined mode) tCYC Cycle time (flow-through mode) tCYCF Clock access time (pipelined mode) tCD Clock access time (flow-through mode) tCDF Output enable low to data valid tOE Clock high to output low Z tLZC Data output invalid from clock high tOH (pipelined mode) Data Output invalid from clock high tOHF (Flow Through Mode) Output enable low to output low Z tLZOE Output enable high to output high Z tHZOE Clock high to output high Z tHZC Output enable high to invalid output tOHOE Clock high pulse width tCH Clock low pulse width tCL Address setup to clock high tAS Data setup to clock high tDS Write setup to clock high tWS Chip select setup to clock high tCSS Address hold from clock high tAH Data hold from clock high tDH Write hold from clock high tWH Chip select hold from clock high tCSH ADV setup to clock high tADVS ADSP setup to clock high tADSPS ADSC setup to clock high tADSCS ADV hold from clock high tADVH ADSP hold from clock high tADSPH ADSC hold from clock high tADSCH -200 Min Max - 200 5 - 7.5 - - 3.0 - 7.5 - 3.0 0 - -166 Min Max - 166 6 - 8.5 - - 3.4 - 8.5 - 3.4 0 - -133 Min Max - 133 7.5 - 12 - - 3.8 - 10 - 3.8 0 - 1.5 - 1.5 - 1.5 3.0 - 3.0 - 0 - - 0 1.8 1.8 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 1.4 1.4 1.4 0.4 0.4 0.4 - 3.0 3.0 - - - - - - - - - - - - - - - - - 0 - - 0 2.4 2.3 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 0.5 0.5 0.5 - 3.4 3.4 - - - - - - - - - - - - - - - - - Unit MHz ns ns ns ns ns ns Notes1 - ns 2 3.0 - ns 2 0 - - 0 2.4 2.4 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 0.5 0.5 0.5 - 3.8 3.8 - - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 5 5 6 6 6, 7 6, 8 6 6 6, 7 6, 8 6 6 6 6 6 6 1 See "Notes" on page 19. 5/28/03, v. 052003 Advance Info Alliance Semiconductor 8 of 21 AS7C331MPFS18A (R) IEEE 1149.1 serial boundary scan (JTAG) The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. The inclusion of these functions would place an added delay in the critical speed path of the SRAM. The TAP controller functionality does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. It uses JEDEC-standard 2.5V I/O logic levels. The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG feature If the JTAG function is not being implemented, its pins/balls can be left unconnected. At power-up, the device will come up in a reset state which will not interfere with the operation of the device. TAP controller state diagram TAP controller block diagram 7(67 /2*,& 5817(67 ,'/( 6(/(&7 '56&$1 6(/(&7 ,56&$1 &$3785('5 7'2 ,GHQWLILFDWLRQ5HJLVWHU [ 6+,)7,5 6HOHFWLRQ &LUFXLWU\ ,QVWUXFWLRQ5HJLVWHU 6+,)7'5 %RXQGDU\6FDQ5HJLVWHU (;,7'5 (;,7,5 7&. 3$86('5 3$86(,5 7$3&RQWUROOHU 706 (;,7'5 [ IRU WKH [ FRQILJXUDWLRQ [ IRU WKH [ (;,7,5 83'$7('5 6HOHFWLRQ &LUFXLWU\ 7', &$3785(,5 %\SDVV5HJLVWHU 83'$7(,5 1RWH7KHRUQH[WWRHDFKVWDWHUHSUHVHQWVWKHYDOXHRI706DWWKHULVLQJHGJHRI7&. Test access port (TAP) Test clock (TCK) The test clock is used with only the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test mode select (TMS) The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can leave this pin/ball unconnected if the TAP is not used. The pin/ball is pulled up internally, resulting in a logic high level. 5/28/03, v. 052003 Advance Info Alliance Semiconductor 9 of 21 AS7C331MPFS18A (R) Test data-in (TDI) The TDI pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See the TAP Controller Block Diagram.) Test data-out (TDO) The TDO output pin/ball serially clocks data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See the TAP Controller State Diagram.) Performing a TAP RESET You can perform a RESET by forcing TMS high (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and can be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP registers Registers are connected between the TDI and TDO pins/balls. They allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/ball on the rising edge of TCK. Data is output on the TDO pin/ball on the falling edge of TCK. Instruction register You can serially load three-bit instructions into the instruction register. The register is loaded when it is placed between the TDI and TDO pins/ balls as shown in the TAP Controller Block Diagram. The instruction register is loaded with the IDCODE instruction at power up and also if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level series test data path. Bypass register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO pins/balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set low (Vss) when the BYPASS instruction is executed. Boundary scan register The boundary scan register is connected to all the input and bidirectional pins/balls on the SRAM. The x36 configuration has a 72-bit-long register and the x18 configuration has a 53-bit-long register. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins/balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/RELOAD, and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The boundary scan order table shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The most significant bit (MSB) of the register is connected to TDI, and the least significant bit (LSB) is connected to TDO. Identification (ID) register The ID register has a vendor code and other information described in the Identification Register Definitions table. The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. 5/28/03, v. 052003 Advance Info Alliance Semiconductor 10 of 21 AS7C331MPFS18A (R) TAP instruction set Eight different instructions are possible with the 3-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are reserved and should not be used. Note that the TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/ PRELOAD. Instead, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins/balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST The EXTEST instruction, which executes whenever the instruction register is loaded with all 0s, is not implemented in this SRAM TAP controller. The TAP controller, however, does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a high-Z state. EXTEST is a mandatory 1149.1 instruction. this device, therefore, is not compliant with 1149.1. IDCODE The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins/balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins/balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a high-Z state. SAMPLE/PRELOAD When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional pins/balls is captured in the boundary scan register. Note that the SAMPLE/PRELOAD is a 1149.1 mandatory instruction, but the PRELOAD portion of this instruction is not implemented in this device. The TAP controller, therefore, is not fully 1149.1 compliant. Be aware that the TAP controller clock can operate only at a frequency up to 10 Mhz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output can undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is possible to capture all other signals and ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/ PRELOAD instruction will have the same effect as the Pause-DR command. BYPASS The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between TDI and TDO. 5/28/03, v. 052003 Advance Info Alliance Semiconductor 11 of 21 AS7C331MPFS18A (R) Reserved Do not use a reserved instruction.These instructions are not implemented but are reserved for future use. TAP timing diagram 7HVW&ORFN 7&. W7+7/ W7/7+ W7+7+ 7HVW0RGH6HOHFW 706 W097+ W7+0; 7HVW'DWD,Q 7', W7/29 W7/2; W'97+ W7+'; 7HVW'DWD2XW 7'2 'RQWFDUH 8QGHILQHG TAP AC electrical characteristics For notes 1 and 2, +10oC < TJ < +110oC and +2.4V < VDD < +2.6V. Description Symbol Min Max Units Clock t Clock cycle time THTH 100 f Clock frequency TF ns 10 MHz Clock high time tTHTL 40 ns Clock low time t TLTH 40 ns TCK low to TDO unknown tTLOX 0 ns TCK low to TDO valid t TDI valid to TCK high t DVTH 10 ns TCK high to TDI invalid tTHDX 10 ns t MVTH 10 ns tCS1 10 ns THMX 10 ns tCH1 10 ns Output Times TLOV 20 ns Setup Times TMS setup Capture setup Hold Times TMS hold t Capture hold 1 tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 2 Test conditions are specified using the load in the figure TAP AC output load equivalent. 5/28/03, v. 052003 Advance Info Alliance Semiconductor 12 of 21 AS7C331MPFS18A (R) TAP AC test conditions TAP AC output load equivalent 9 Input pulse levels. . . . . . . . . . . . . . . Vss to 2.5V Input rise and fall times. . . . . . . . . . . . . . . 1 ns Input timing reference levels. . . . . . . . . . 1.25V 7'2 Output reference levels . . . . . . . . . . . . . . 1.25V S) =2 Test load termination supply voltage. . . . 1.25V 3.3V VDD, TAP DC electrical characteristics and operating conditions (+10oC < TJ < +110oC and +3.135V < VDD < +3.465V unless otherwise noted) Description Conditions Symbol Min Max Units Notes Input high (logic 1) voltage VIH 2.0 VDD + 0.3 V 1, 2 Input low (logic 0) voltage VIL -0.3 0.8 V 1, 2 0V VIN VDD ILI -5.0 5.0 A Outputs disabled, 0V VIN VDDQ(DQx) ILO -5.0 5.0 A Input leakage current Output leakage current Output low voltage IOLC = 100A VOL1 0.7 V 1 Output low voltage IOLT = 2mA VOL2 0.8 V 1 Output high voltage IOHS = -100A VOH1 2.9 V 1 Output high voltage IOHT = -2mA VOH2 2.0 V 1 2.5V VDD, TAP DC electrical characteristics and operating conditions (+10oC < TJ < +110oC and +2.4V < VDD < +2.6V unless otherwise noted) Description Conditions Symbol Min Max Units Notes Input high (logic 1) voltage VIH 1.7 VDD + 0.3 V 1, 2 Input low (logic 0) voltage VIL -0.3 0.7 V 1, 2 0V VIN VDD ILI -5.0 5.0 A Outputs disabled, 0V VIN VDDQ(DQx) ILO -5.0 5.0 A IOLC = 100A VOL1 0.2 V Input leakage current Output leakage current Output low voltage 1 Output low voltage IOLT = 2mA VOL2 V 1 Output high voltage IOHS = -100A VOH1 2.1 V 1 Output high voltage IOHT = -2mA VOH2 1.7 V 1 0.7 1. All voltage referenced to VSS(GND). 2. Overshoot: VIH(AC) VDD + 1.5V for t tKHKH/2 Undershoot: VIL(AC) -0.5 for t tKHKH/2 Power-up: VIH +2.6V and VDD 2.4V and VDDQ 1.4V for t 200ms During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD, R/W, etc.) may not have pulsed widths less than tKHKL(Min) or operate at frequencies exceeding fKF(Max). 5/28/03, v. 052003 Advance Info Alliance Semiconductor 13 of 21 AS7C331MPFS18A (R) Identification register definitions Instruction field 1M x 18 Description Revision number (31:28) xxxx Reserved for version number. Device depth (27:23) xxxxx Defines the depth of 1Mb words. Device width (22:18) xxxxx Defines the width of x18 bits. Device ID (17:12) xxxxxx Reserved for future use. JEDEC ID code (11:1) 00000110100 Allows unique identification of SRAM vendor. ID register presence indicator (0) 1 Indicates the presence of an ID register. Scan register sizes Register name Bit size Instruction 3 Bypass 1 ID 32 Boundary scan x18:53 x36:72 Instruction codes Instruction Code EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to high-Z state. This instruction is not 1149.1-compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high-Z state. Reserved 011 Do not use. This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. Reserved 101 Do not use. This instruction is reserved for future use. Reserved 110 Do not use. This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 5/28/03, v. 052003 Advance Info Description Alliance Semiconductor 14 of 21 AS7C331MPFS18A (R) 165-ball BGA boundary scan order (x18) Bit #s Signal Name Ball ID Bit #s Signal Name Ball ID 1 SA 11P 28 GWE 7B 2 SA 6N 29 CLK 6B 3 SA 8P 30 CE2 6A 4 SA 8R 31 BWa 5B 5 SA 9R 32 BWb 4A 6 SA 9P 33 CE1 3B 7 SA 10P 34 CE0 3A 8 SA 10R 35 SA 2A 9 SA 11R 36 SA 2B 10 DQa 10M 37 DQb 2D 11 DQa 10L 38 DQb 2E 12 DQa 10K 39 DQb 2F 13 DQa 10J 40 DQb 2G 14 ZZ 11H 41 FT 1H 15 DQa 11G 42 DQb 1J 16 DQa 11F 43 DQb 1K 17 DQa 11E 44 DQb 1L 18 DQa 11D 45 DQb 1M 19 DQPa 11C 46 DQPb 1N 20 SA 11A 47 LBO 1R 21 SA 10A 48 SA 3P 22 SA 10B 49 SA 3R 23 ADV 9A 50 SA 4R 24 ADSP 9B 51 SA 4P 25 ADSC 8A 52 SA1 6P 26 OE 8B 53 SA0 6R 27 BWE 7A 5/28/03, v. 052003 Advance Info Alliance Semiconductor 15 of 21 AS7C331MPFS18A (R) Key to switching waveforms Rising input Falling input Undefined/don't care Timing waveform of read cycle tCH tCYC tCL CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC tAS tAH Address Load new address A1 A2 A3 tWS tWH GWE, BWE tCSS tCSH CE0, CE2 CE1 tADVS tADVH ADV ADV inserts wait states OE tCD tOH tHZOE DOUT (pipelined mode) Q(A1) Q(A2) tHZC Q(A2Y01) Q(A2Y10) Q(A2Y11) Q(A3) Q(A3Y01) Q(A3Y10) tOE tLZOE DOUT (flow-through mode) Q(A1) Q(A2Y01) Q(A2Y10) Q(A2Y11) Q(A3) Q(A3Y01) Q(A3Y10) Q(A3Y11) tHZC Read Q(A1) Suspend Read Q(A1) Read Q(A2) Burst Burst Suspend Burst Read Read Read Read Read Q(A3) Q(A 2Y01) Q(A 2Y10) Q(A 2Y10) Q(A 2Y11) Burst Burst Burst Read Read Read Q(A 3Y01) Q(A 3Y10) Q(A 3Y11) DSEL Note: Y = XOR when LBO = high/no connect; Y = ADD when LBO = low. BW[a:b] is don't care. 5/28/03, v. 052003 Advance Info Alliance Semiconductor 16 of 21 AS7C331MPFS18A (R) Timing waveform of write cycle tCH tCYC tCL CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC tAS tAH Address A1 ADSC loads new address A3 A2 tWS tWH BWE BW[a:d] tCSS tCSH CE0, CE2 CE1 tADVS tADVH ADV suspends burst ADV OE tDS tDH Data In D(A1) Read Q(A1) Suspend Write D(A1) D(A2) Read Q(A2) Suspend Write D(A 2) D(A2Y01) D(A2Y01) D(A2Y10) D(A2Y11) ADV Suspend ADV ADV Burst Write Burst Burst Write D(A 2Y01) Write Write D(A 2Y01) Q(A 2Y10) Q(A 2Y11) D(A3) D(A3Y01) D(A3Y10) Write D(A 3) Burst Write D(A 3Y01) ADV Burst Write D(A 3Y10) Note: Y = XOR when LBO = high/no connect; Y = ADD when LBO = low. 5/28/03, v. 052003 Advance Info Alliance Semiconductor 17 of 21 AS7C331MPFS18A (R) Timing waveform of read/write cycle tCYC tCL tCH CLK tADSPS tADSPH ADSP tAS tAH A2 A1 Address A3 tWS tWH GWE CE0, CE2 CE1 tADVS tADVH ADV OE tDS tDH DIN D(A2) tCD tLZOE tLZC DOUT (pipelined mode) tOH tOE tHZOE Q(A3) Q(A1) Q(A3Y01) Q(A3Y10) Q(A3Y11) tCDF DOUT (flow-through mode) Q(A1) DSEL Read Q(A1) Suspend Read Q(A1) Q(A3Y01) Read Q(A2) Suspend Write D(A 2) Read Q(A3) ADV Burst Read D(A 3Y01) ADV Burst Read Q(A 3Y10) Q(A3Y10) ADV Burst Read Q(A 3Y11) Q(A3Y11) Suspend Read Q(A 3Y11) Note: Y = XOR when LBO = high/no connect; Y = ADD when LBO = low. 5/28/03, v. 052003 Advance Info Alliance Semiconductor 18 of 21 AS7C331MPFS18A (R) AC test conditions * Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B. * Input pulse level: GND to 3V. See Figure A. Thevenin equivalent: * Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O * Input and output timing reference levels: 1.5V. +3.0V 90% 10% GND 90% 10% Figure A: Input waveform DOUT Z0 = 50 50 VL = 1.5V for 3.3V I/O; 30 pF* VL = VDDQ/2 for 2.5V I/O Figure B: Output load (A) 319/1667 DOUT 353/1538 5 pF* GND *including scope and jig capacitance Figure C: Output load(B) Notes 1 2 3 4 5 6 7 8 For test conditions, see "AC Test Conditions", Figures A, B, and C. This parameter is measured with output load condition in Figure C. This parameter is sampled but not 100% tested. tHZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage. tCH is measured as high above VIH, and tCL is measured as low below VIL. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times for all rising edges of CLK when chip is enabled. Write refers to GWE, BWE, and BW[a,b]. Chip select refers to CE0, CE1, and CE2. 5/28/03, v. 052003 Advance Info Alliance Semiconductor 19 of 21 AS7C331MPFS18A (R) Package dimensions 100-pin TQFP (quad flat pack) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e Hd D c L1 L e 0.65 nominal 15.90 16.10 He 21.90 22.10 L 0.45 0.75 1.00 nominal 0 He E Hd L1 b A1 A2 7 Dimensions in millimeters 165-ball BGA (ball grid array) $FRUQHULQGH[DUHD & ( ) + = * = ) $ 6LGH9LHZ 5/28/03, v. 052003 Advance Info ' , & Alliance Semiconductor 0$; * % ' $ % & ' ( ) * + . / 0 1 3 5 $ 0D[ % $ 7\S %RWWRP9LHZ $ % & ' ( ) * + . / 0 1 3 5 $OOPHDVXUHPHQWVDUHLQPP 0LQ 7RS9LHZ + ( ' , ; 0 = ; < 0 = 'HWDLORI6ROGHU%DOO 20 of 21 AS7C331MPFS18A (R) Ordering information Package &Width TQFP x18 -200 MHz -166 MHz -133 MHz AS7C331MPFS18A-200TQC AS7C331MPFS18A-166TQC AS7C331MPFS18A-133TQC AS7C331MPFS18A-200TQI AS7C331MPFS18A-166TQI AS7C331MPFS18A-133TQI AS7C331MPFS18A-200BC AS7C331MPFS18A-166BC AS7C331MPFS18A-133BC AS7C331MPFS18A-200BI AS7C331MPFS18A-166BI AS7C331MPFS18A-133BI BGA x18 Part numbering guide AS7C 33 1M PF S 18 A -XXX TQ or B C/I 1 2 3 4 5 6 7 8 9 10 1. Alliance Semiconductor SRAM prefix 2. Operating voltage: 33 = 3.3V 3. Organization: 1M 4. Pipelined/flow-through mode (each device works in both modes) 5. Deselect: S = single cycle deselect 6. Organization: 18 = x18 7. Production version: A = first production version 8. Clock speed (MHz) 9. Package type: TQ = TQFP; B = BGA 10. Operating temperature: C = commercial (0 C to 70 C); I = industrial (-40 C to 85 C) 5/28/03, v. 052003 Advance Info Alliance Semiconductor 21 of 21 (c) Copyright A lliance Sem iconductor Corporation. All rights reserved. O ur three-point logo, our nam e and Intelliw att are tradem arks or registered tradem arks of A lliance. A ll other brand and product nam es m ay be the tradem arks of their respective com panies. A lliance reserves the right to m ake changes to this docum ent and its products at any tim e w ithout notice. Alliance assum es no responsibility for any errors that m ay appear in this docum ent. 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