_______________General Description
The MAX1003 is a dual, 6-bit analog-to-digital converter
(ADC) that combines high-speed, low-power operation
with a user-selectable input range, an internal refer-
ence, and a clock oscillator. The dual parallel ADCs are
designed to convert in-phase (I) and quadrature (Q)
analog signals into two 6-bit, offset-binary-coded digital
outputs at sampling rates up to 90Msps. The ability to
directly interface with baseband I and Q signals makes
the MAX1003 ideal for use in direct-broadcast satellite,
VSAT, and QAM16 demodulation applications.
The MAX1003 input amplifiers feature true differential
inputs, a -0.5dB analog bandwidth of 55MHz, and user-
programmable input full-scale ranges of 125mVp-p,
250mVp-p, or 500mVp-p. With an AC-coupled input
signal, matching performance between input channels
is typically better than 0.1dB gain, 1/4LSB offset, and
0.5° phase. Dynamic performance is 5.85 effective
number of bits (ENOB) with a 20MHz analog input sig-
nal, or 5.7 ENOB with a 50MHz signal.
The MAX1003 operates with +5V analog and +3.3V digi-
tal supplies for easy interfacing to +3.3V-logic-compati-
ble digital signal processors and microprocessors. It
comes in a 36-pin SSOP package.
________________________Applications
Direct Broadcast Satellite (DBS) Receivers
VSAT Receivers
Wide Local Area Networks (WLANs)
Cable Television Set-Top Boxes
____________________________Features
♦Two Matched 6-Bit ADCs
♦High Sampling Rate: 90Msps per ADC
♦Low Power Dissipation: 350mW
♦Excellent Dynamic Performance:
5.85 ENOB with 20MHz Analog Input
5.7 ENOB with 50MHz Analog Input
♦±1/4LSB INL and DNL (typ)
♦Internal Bandgap Voltage Reference
♦Internal Oscillator with Overdrive Capability
♦55MHz (-0.5dB) Bandwidth Input Amplifiers with
True Differential Inputs
♦User-Selectable Input Full-Scale Range
(125mVp-p, 250mVp-p, or 500mVp-p)
♦1/4LSB Channel-to-Channel Offset Matching (typ)
♦0.1dB Gain and 0.5° Phase Matching (typ)
♦Single-Ended or Differential Input Drive
♦Flexible, 3.3V, CMOS-Compatible Digital Outputs
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
________________________________________________________________
Maxim Integrated Products
1
MAX1003
DATA
BUFFER
Q
CLOCK
DRIVER
DI0–DI5
DCLK
TNK+
TNK-
DQ0–DQ5
INPUT
AMP
I
IIN+
IIN-
GAIN
QIN+
QIN-
CLOCK
OUT
DATA
BUFFER
I
6
ADC
I
ADC
Q
VREF
VREF
BANDGAP
REFERENCE
OFFSET
CORREC-
TION Q
OFFSET
CORREC-
TION I
INPUT
AMP
Q
QOCC+ QOCC-
IOCC+ IOCC-
66
6
_________________________________________________________Functional Diagram
19-1236; Rev 0; 6/97
PART
MAX1003CAX 0°C to +70°C
TEMP. RANGE PIN-PACKAGE
36 SSOP
EVALUATION KIT
AVAILABLE
______________Ordering Information
Pin Configuration appears at end of data sheet.
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC = +5V ±5%, VCCO = 3.3V ±300mV, TA= TMIN to TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to GND ............................................................-0.3V to 6.5V
VCCO to OGND........................................................-0.3V to 6.5V
GND to OGND ........................................................-0.3V to 0.3V
Digital and Clock Output Pins to OGND...-0.3V to VCCO (10sec)
All Other Pins to GND...............................................-0.3V to VCC
Continuous Power Dissipation (TA= +70°C)
SSOP (derate 11.8mW/°C above +70°C) ...................941mW
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, <10sec)...........................+300°C
CONDITIONS
LSB-0.5 ±0.25 0.5INLIntegral Nonlinearity Bits6RESResolution
UNITSMIN TYP MAXSYMBOLPARAMETER
GAIN = open (mid gain)
GAIN = VCC (high gain)
No missing codes over temperature
237.5 250 262.5VFSM
118.75 125 131.25VFSH
LSB-0.5 ±0.25 0.5DNLDifferential Nonlinearity
Other analog input driven with external source
(Note 2)
Guaranteed by design
V1.75 2.75VCM
GAIN = GND (low gain)
Common-Mode Voltage Range
pF3 5CIN
Input Capacitance kΩ13 20 29RIN
Input Resistance V2.25 2.35 2.45VAOC
Input Open-Circuit Voltage
mVp-p
475 500 525VFSL
Full-Scale Input Range
Other oscillator input tied to VCC + 0.3V
ISOURCE = 50µA V0.7VCCO
VOH
Digital Outputs Logic-High
Voltage
kΩ4.8 8 12.1ROSC
Oscillator Input Resistance
ISINK = 400µA V0.5VOL
Digital Outputs Logic-Low
Voltage
VCC = 4.75V to 5.25V (Note 3)
20MHz, full-scale I and Q analog inputs,
CL= 15pF (Note 4)
mW350PDPower Dissipation
mA21ICCO
Digital Outputs Supply Current
dB-75 -40PSRRPower-Supply Rejection Ratio mA63 104ICC
Supply Current
DC ACCURACY (Note 1)
INVERTING AND NONINVERTING ANALOG INPUTS
OSCILLATOR INPUTS
DIGITAL OUTPUTS (DI0–DI5, DQ0–DQ5)
POWER SUPPLY
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(VCC = +5V ±5%, VCCO = 3.3V ±300mV, TA= +25°C, unless otherwise noted.)
Note 1: Best-fit straight-line linearity method.
Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4 and 5).
Note 3: PSRR is defined as the change in the mid-gain full-scale range as a function of the variation in VCC supply voltage,
expressed in decibels.
Note 4: The current in the VCCO supply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran-
sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig-
ital outputs to a minimum.
Note 5: Offset-correction compensation enabled, 0.22µF at Q and I compensation inputs (Figures 2 and 3).
Note 6: tPD and tSKEW are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. tDCLK is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-
itive load on the outputs is 15pF.
GAIN = GND, open, VCC
GAIN = open (mid gain), fIN = 50MHz,
-1dB below full scale
GAIN = open (mid gain)
5.7
ENOBM
5.6 5.85
Effective Number of Bits
GAIN = open (mid gain)
GAIN = GND (low gain)
Q channel
I channel
dB
CONDITIONS
MHz55BWAnalog Input -0.5dB Bandwidth Msps90fMAX
Maximum Sample Rate
-55XTLK
GAIN = VCC (high gain)
Crosstalk Between ADCs
LSB
-0.5 0.5
OFFInput Offset (Note 5) -0.5 0.5
dB35.5 37SINAD
Signal-to-Noise plus Distortion
Ratio
Bits
5.85ENOBL
5.8ENOBH
(Note 5)
dB-0.2 ±0.1 0.2AM
Amplitude Match Between
ADCs
LSB-0.5 ±0.25 0.5OMMOffset Mismatch Between ADCs
(Note 6)
(Note 6)
ns1.5tSKEW
Data Valid Skew
ns3.6tPD
Clock to Data Propagation
Delay
degrees-2 ±0.5 2PM
UNITSMIN TYP MAXSYMBOLPARAMETER
Phase Match Between ADCs
TNK+ to DCLK (Note 6) ns5.3tDCLK
Input to DCLK Delay Figure 8 ns7.5tAD
Aperture Delay
Figure 8 clock
cycle
1PDPipeline Delay
TIMING CHARACTERISTICS (Data outputs: RL= 1MΩ, CL= 15pF)
DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), VINI = VINQ = 20MHz sine, amplitude -1dB below
full scale, unless otherwise noted.)
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
4 _______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(VCC = +5V ±5%, VCCO = 3.3V ±300mV, fCLK = 90Msps, GAIN = open (midgain) MAX1003 evaluation kit, TA= +25°C, unless
otherwise noted.)
6.0
5.0 10 100
EFFECTIVE NUMBER OF BITS
vs. ANALOG INPUT FREQUENCY
5.2
MAX1003-01
ANALOG INPUT FREQUENCY (MHz)
EFFECTIVE NUMBER OF BITS
5.4
5.6
5.8
fCLK = 90Msps
-1.0 1 10 100
ANALOG INPUT BANDWIDTH
-0.8
MAX1003-02
ANALOG INPUT FREQUENCY (MHz)
MAGNITUDE (dB)
-0.6
-0.2
-0.4
0
5.5 1 10 100
EFFECTIVE NUMBER OF BITS
vs. SAMPLING/CLOCK FREQUENCY
5.6
MAX1003-03
CLOCK FREQUENCY (MHz)
EFFECTIVE NUMBER OF BITS
5.7
5.9
5.8
6.0
fIN = 20MHz
-50
1k 100k 1M
OSCILLATOR OPEN-LOOP PHASE NOISE
vs. FREQUENCY OFFSET
-110
-130
-90
-70
MAX1003-04
FREQUENCY OFFSET FROM CARRIER (Hz)
PHASE NOISE (dBc)
10k
0.50
-0.50 0 64
INTEGRAL NONLINEARITY
vs. CODE
-0.25
0.25
MAX1003-06
CODE
INL (LSB)
10 20 30 40 50 60
0
0.50
-0.50 0 64
DIFFERENTIAL NONLINEARITY
vs. CODE
-0.25
0.25
MAX1003-07
CODE
DNL (LSB)
10 20 30 40 50 60
0
-60
-40
-20
0
0 9 18 27 36 45
FFT PLOT
MAX1003-05
FREQUENCY (MHz)
AMPLITUDE (dB)
fIN = 19.9512MHz
fCLK = 90.000MHz
1024 POINTS
AC COUPLED
SINGLE ENDED
AVERAGED
_______________Detailed Description
Converter Operation
The MAX1003 contains two 6-bit analog-to-digital con-
verters (ADCs), a buffered voltage reference, and oscil-
lator circuitry. The ADCs use a flash conversion
technique to convert an analog input signal into a 6-bit
parallel digital output code. The MAX1003’s unique
design includes 63 fully differential comparators and a
proprietary encoding scheme that ensures no more
than 1LSB dynamic encoding error. The control logic
interfaces easily to most digital signal processors
(DSPs) and microprocessors (µPs) with +3.3V CMOS-
compatible logic interfaces. Figure 1 shows the
MAX1003 in a typical application.
Programmable Input Amplifiers
The MAX1003 has two (I and Q) programmable-gain
input amplifiers with a -0.5dB bandwidth of 55MHz and
true differential inputs. To maximize performance in
high-speed systems, each amplifier has less than 5pF
of input capacitance. The input amplifier gain is pro-
grammed, via the GAIN pin, to provide three possible
input full-scale ranges (FSRs) as shown in Table 1.
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
_______________________________________________________________________________________ 5
______________________________________________________________Pin Description
PIN
Gain-Select Input. Sets input full-scale range: 125/250/500mVp-p (Table 1).GAIN1
FUNCTIONNAME
Positive I-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
IOCC+2
I-Channel Noninverting Analog InputIIN+4
Negative I-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
IOCC-3
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 7).VCC
6
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 11).VCC
8
Analog GroundGND
7, 11, 12,
18, 19
I-Channel Inverting Analog InputIIN-5
Negative Oscillator/Clock InputTNK-10
Q-Channel Inverting Analog InputQIN-14 +5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 12).VCC
13
Negative Q-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
QOCC-16
Q-Channel Digital Outputs 0–5. DQ5 is the most significant bit (MSB).DQ5–DQ020–25
Positive Q-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
QOCC+17
Q-Channel Noninverting Analog InputQIN+15
Positive Oscillator/Clock InputTNK+9
Digital Output GroundOGND27
I-Channel Digital Outputs 0–5. DI5 is the most significant bit (MSB).DI0–DI530–35 Digital Clock Output. Frames the output data.DCLK29
Digital Output Supply, +3.3V ±300mV. Bypass each with a 47pF capacitor to OGND (pin 27).VCCO
26, 28
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 19).VCC
36
250Open 125VCC
GAIN
500GND
INPUT FULL-SCALE RANGE
(mVp-p)
Table 1. Input Amplifier Programming
MAX1003
Single-ended and differential AC-coupled input circuits
are shown in Figures 2 and 3. Each of the amplifier
inputs is internally biased to a 2.35V reference through
a 20kΩresistor, eliminating external DC bias circuits. A
series 0.1µF capacitor is required at each amplifier
input for AC-coupled signals.
When operating with AC-coupled inputs, the input
amplifiers’ DC offset voltage is nulled to within ±1/2LSB
by an on-chip offset-correction amplifier. An external
compensation capacitor is required to set the dominant
pole of the offset-correction amplifier’s frequency
response (Figures 2 and 3). The compensation capaci-
tor will determine the low-frequency corner of the ana-
log input response according to the following formula:
fc= 1 / (0.1 x C)
where C is the value of the compensation capacitor in
µF, and fcis the corner frequency in Hz.
Low-Power, 90Msps, Dual 6-Bit ADC
6 _______________________________________________________________________________________
0
DIV
90Msps
DATA
BUFFER
TANK
MODCTL CAR
SYNTHESIZER
FIN
IIN
AGC
CLK IN
DSP
QIN
ADC CLOCK
6 BITS
TANK
LO
TSA5055
or EQUIV.
90
MOD GND
AGC
IOUT
QOUT
VCC
FROM TANK VOLTAGE
VARACTOR-TUNED
PRESELECTION FILTER
EXTERNAL
VCO
OR
OR
KU BAND
75Ω CABLE
950MHz TO 2150MHz
F-CONNECTOR
INPUT
MAX2102
MAX1003
DATA
BUFFER
LO
RFIN
RFIN
LNB
6 BITS
Figure 1. Commercial Satellite Receiver System
For applications where a DC component of the input
signal is present, Figures 4 and 5 show single-ended
and differential DC-coupled input circuits. The ampli-
fiers’ input common-mode voltage range extends from
1.75V to 2.75V. To prevent attenuation of the input
signal’s DC component in this mode, disable the offset-
correction amplifier by grounding the _OCC+ and
_OCC- pins for the I and Q blocks (Figures 4 and 5).
ADCs
The I and Q ADC blocks receive the analog signals
from the respective I and Q input amplifiers. The ADCs
use flash conversion with 63 fully differential compara-
tors to digitize the analog input signal into a 6-bit output
in offset binary format.
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
_______________________________________________________________________________________ 7
Figure 2. Single-Ended AC-Coupled Input Figure 3. Differential AC-Coupled Input
Figure 4. Single-Ended DC-Coupled Input Figure 5. Differential DC-Coupled Input
MAX1003
INPUT
AMP
20k
2.35V INTERNAL REFERENCE
20k
_IN+
_OCC+ _OCC-
_IN-
0.1µF
0.22µF
VSOURCE
0.1µF
OFFSET
CORREC-
TION
MAX1003
INPUT
AMP
20k
2.35V INTERNAL REFERENCE
20k
_IN+
_OCC+ _OCC-
_IN-
0.1µF
0.1µF
VSOURCE
OFFSET
CORREC-
TION
0.22µF
MAX1003
INPUT
AMP
20k
2.35V INTERNAL REFERENCE
20k
_IN+
_OCC+ _OCC-
_IN-
OFFSET CORRECTION DISABLED
VSOURCE
VREF
1.75V TO 2.75V
OFFSET
CORREC-
TION
MAX1003
INPUT
AMP
20k
2.35V INTERNAL REFERENCE
20k
_IN+
_OCC+ _OCC-
_IN-
OFFSET CORRECTION DISABLED
VSOURCE
DIFFERENTIAL SOURCE
WITH COMMON MODE
FROM 1.75V TO 2.75V.
OFFSET
CORREC-
TION
MAX1003
The MAX1003 features a proprietary encoding scheme
that ensures no more than 1LSB dynamic encoding
error. Dynamic encoding errors resulting from
metastable states may occur when the analog input
voltage, at the time the sample is taken, falls close to
the decision point for any one of the input comparators.
The resulting output code for typical converters can be
incorrect, including false full- or zero-scale outputs. The
MAX1003’s unique design reduces the magnitude of
this type of error to 1LSB.
Internal Voltage Reference
An internal buffered bandgap reference is included on
the MAX1003 to drive the ADCs’ reference ladders. The
on-chip reference and buffer eliminate any external
(high-impedance) connections to the reference ladder,
minimizing the potential for noise coupling from exter-
nal circuitry while ensuring that the voltage reference,
input amplifier, and reference ladder track well with
variations of temperature and power supplies.
Oscillator Circuit
The MAX1003 includes a differential oscillator, which is
controlled by an external parallel resonant (tank) net-
work as shown in Figure 6. Alternatively, the oscillator
may be overdriven with an external clock source as
shown in Figure 7.
Internal Clock Operation (Tank)
If the tank circuit is used, the resonant inductor should
have a sufficiently high Q and a self-resonant frequen-
cy (SRF) of at least twice the intended oscillator fre-
quency. Coilcraft’s 1008HS-221, with an SRF of
700MHz and a Q of 45, works well for this application.
Generate different clock frequency ranges by adjusting
varactor and tank elements.
An internal clock-driver buffer is included to provide
sharp clock edges to the internal flash comparators.
The buffer ensures that the comparators are simultane-
ously clocked, maximizing the ADCs’ effective number
of bits (ENOB) performance.
Low-Power, 90Msps, Dual 6-Bit ADC
8 _______________________________________________________________________________________
Figure 6. Tank Resonator Oscillator Figure 7. External Clock Drive Circuit
MAX1003
CLK
DRIVER
VARACTOR DIODE PAIR IS M/A-COM MA4ST079CK-287 (SOT23 PACKAGE)
INDUCTOR COILCRAFT 1008HS-221.
VTUNE = 0V TO 8V
fOSC = 70MHz TO 110MHz
TNK-
TNK+
VTUNE 220nH
5pF
47pF
47pF
47k
47k
10k
MAX1003
CLK
DRIVER
TNK-
VCLK
VCLK = 300mVp-p TO 1.25Vp-p
TNK+
50Ω
50Ω
Z0 = 50Ω
50Ω
0.1µF
0.1µF
External Clock Operation
To accommodate designs that use an external clock,
the MAX1003’s internal oscillator can be overdriven by
an external clock source as shown in Figure 7. The
external clock source should be a sinusoid to minimize
clock phase noise and jitter, which can degrade the
ADCs’ ENOB performance. AC couple the clock source
(recommended voltage level is approximately 1Vp-p) to
the oscillator inputs as shown in Figure 7.
Output Data Format
The conversion results are output on a dual, 6-bit-wide
data bus. Data is latched into the ADC output latch fol-
lowing a pipeline delay of one clock cycle, as shown in
Figure 8. Output data is clocked out of the respective
ADC’s data output pins (D_0 through D_5) on the rising
edge of the clock output (DCLK), with a DCLK-to-data
propagation delay (tPD) of 3.6ns. The MAX1003 outputs
are +3.3V CMOS-logic compatible.
Transfer Function
Figure 9 shows the MAX1003’s nominal transfer function.
Output coding is offset binary with 1LSB = FSR / 63.
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
_______________________________________________________________________________________ 9
Figure 9. Ideal Transfer Function
111111
OUTPUT CODE
111110
111101
100001
100000
011111
011110
000011
000010
000001
000000 -FSR
20
1LSB
INPUT VOLTAGE (_IN+ TO _IN-)
FSR
2
Figure 8. MAX1003 Timing Diagram
DATA OUT 1.4V DATA VALID N - 1 DATA VALID N
1.4V
50%
tSKEW
tDCLK
tAD
tPD
TNK+
(INPUT CLOCK)
DCLK
ANALOG
INPUT
N
N + 1
N + 2
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
10 ______________________________________________________________________________________
__________Applications Information
The MAX1003 is designed with separate analog and
digital power-supply and ground connections to isolate
high-current digital noise spikes from the more sensi-
tive analog circuitry. The high-current digital output
ground (OGND) and analog ground (GND) should be
at the same DC level, connected at only one location
on the board. This will provide best noise immunity and
improved conversion accuracy. Use of separate
ground planes is strongly recommended.
The entire board needs good DC bypassing for both
analog and digital supplies. Place the power-supply
bypass capacitors close to where the power is routed
onto the board, i.e., close to the connector. 10µF elec-
trolytic capacitors with low-ESR ratings are recom-
mended. For best effective bits performance, minimize
capacitive loading at the digital outputs. Keep the digi-
tal output traces as short as possible.
The MAX1003 requires a +5V ±5% power supply for
the analog supply (VCC) and a +3.3V ±300mV power
supply connected to VCCO for the logic outputs.
Bypass each of the VCC_ supply pins to its respective
GND with high-quality ceramic capacitors located as
close to the package as possible (Table 2). Consult the
evaluation kit manual for a suggested layout and
bypassing scheme.
_____________Dynamic Performance
Signal-to-noise and distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to all
other ADC output signals. The output spectrum is limit-
ed to frequencies above DC and below one-half the
ADC sample rate.
The theoretical minimum analog-to-digital noise is
caused by quantization error, and results directly from
the ADC’s resolution: SNR = (6.02N + 1.76)dB, where
N is the number of bits of resolution. Therefore, a per-
fect 6-bit ADC can do no better than 38dB.
The FFT Plot (see
Typical Operating Characteristics
)
shows the result of sampling a pure 20MHz sinusoid at
a 90MHz clock rate. This FFT plot of the output shows
the output level in various spectral bands. The plot has
been averaged to reduce the quantization noise floor
and reveal the low-amplitude spurs. This emphasizes
the excellent spurious-free dynamic range of the
MAX1003.
The effective resolution (or effective number of bits) the
ADC provides can be measured by transposing the
equation that converts resolution to SINAD: N =
(SINAD - 1.76) / 6.02 (see
Typical Operating
Characteristics
).
Table 2. Bypassing
0.01µFOscillator/Clock 0.01µFConverter
SUPPLY
FUNCTION
0.01µFAnalog Inputs
CAPACITOR
VALUE
47pFDigital I-Output 0.01µFBuffer
47pFDigital Q-Output 27
19
11
27
12
BYPASS
TO
GND/
OGND
7
28
36
8
26
13
VCC/
VCCO
6
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
______________________________________________________________________________________ 11
__________________Pin Configuration
___________________Chip Information
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC
DI5
DI4
DI3
DI2
DI1
DQ2
DI0
DCLK
VCCO
OGND
VCCO
DQ0
DQ1
QIN-
VCC
GND
GND
TNK-
TNK+
VCC
GND
VCC
IIN-
IIN+
IOCC-
IOCC+
GAIN
SSOP
TOP VIEW
MAX1003
22
21
20
19
15
16
17
18 GND
DQ3
DQ4
DQ5
GND
QOCC+
QOCC-
QIN+
TRANSISTOR COUNT: 6097
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
________________________________________________________Package Information
SSOP2.EPS
