General Description
The MAX1086–MAX1089 are low-cost, micropower, ser-
ial output 10-bit analog-to-digital converters (ADCs)
available in a tiny 8-pin SOT23. The MAX1086/MAX1088
operate with a single +5V supply. The MAX1087/MAX1089
operate with a single +3V supply. The devices feature a
successive-approximation ADC, automatic shutdown,
fast wake-up (1.4µs), and a high-speed 3-wire inter-
face. Power consumption is only 0.5mW (VDD = +2.7V)
at the maximum sampling rate of 150ksps.
AutoShutdown™ (0.1µA) between conversions results in
reduced power consumption at slower throughput rates.
The MAX1086/MAX1087 provide 2-channel, single-
ended operation and accept input signals from 0 to
VREF. The MAX1088/MAX1089 accept true-differential
inputs ranging from 0 to VREF. Data is accessed using
an external clock through the 3-wire SPI™, QSPI™, and
MICROWIRE™-compatible serial interface. Excellent
dynamic performance, low-power, ease of use, and
small package size, make these converters ideal for
portable battery-powered data acquisition applications,
and for other applications that demand low power con-
sumption and minimal space.
Applications
Low Power Data Acquisition
Portable Temperature Monitors
Flowmeters
Touch Screens
Features
oSingle-Supply Operation
+3V (MAX1087/MAX1089)
+5V (MAX1086/MAX1088)
oAutoShutdown Between Conversions
oLow Power
200µA at 150ksps
130µA at 100ksps
65µA at 50ksps
13µA at 10ksps
1.5µA at 1ksps
0.2µA in Shutdown
oTrue-Differential Track/Hold, 150kHz Sampling Rate
oSoftware-Configurable Unipolar/Bipolar
Conversion (MAX1088/MAX1089 only)
oSPI, QSPI, MICROWIRE-Compatible Interface for
DSPs and Processors
oInternal Conversion Clock
o8-Pin SOT23 and 8-Pin TDFN Packages
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
________________________________________________________________
Maxim Integrated Products
1
CNVST
REFGND
1
2
8
7
SCLK
DOUTAIN1 (AIN+)
AIN2 (AIN-)
VDD
SOT23
TOP VIEW
( ) ARE FOR THE MAX1088/MAX1089
3
4
6
5
MAX1086
MAX1087
MAX1088
MAX1089
134
865
SCLK
CONVST
REF
MAX1086–
MAX1089
2
7
DOUT
VDD
AIN1
AIN2
GND
TDFN
+
Pin Configurations
19-2036; Rev 3; 8/10
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
AutoShutdown is a trademark of Maxim Integrated Products.
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
PART TEMP
RANGE
PIN-
PACKAGE
TOP
MARK
MAX1086EKA-T -40°C to +85°C 8 SOT23 AAEZ
MAX1086ETA+T -40°C to +85°C 8 TDFN-EP* AFQ
MAX1087EKA-T -40°C to +85°C 8 SOT23 AAEV
MAX1087ETA+T -40°C to +85°C 8 TDFN-EP* AFM
MAX1088EKA-T -40°C to +85°C 8 SOT23 AAFB
MAX1088ETA+T -40°C to +85°C 8 TDFN-EP* AFS
MAX1089EKA-T -40°C to +85°C 8 SOT23 AAEX
MAX1089ETA+T -40°C to +85°C 8 TDFN-EP* AFO
*EP = Exposed pad.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
EVALUATION KIT
AVAILABLE
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1087/MAX1089, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1086/MAX1088,
0.1µF capacitor at REF, fSCLK = 8MHz (50% duty cycle), AIN- = GND for MAX1088/MAX1089. TA= TMIN to TMAX, unless otherwise
noted. Typical values at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND.............................................................-0.3V to +6V
CNVST, SCLK, DOUT to GND......................-0.3V to (VDD+0.3V)
REF, AIN1(AIN+), AIN2(AIN-) to GND..........-0.3V to (VDD+0.3V)
Maximum Current Into Any Pin ...........................................50mA
Continuous Power Dissipation (TA= +70°C)
8-Pin SOT23 (derate 9.70mW/°C above TA= +70°C) ......777mW
8-Pin TDFN (derate 18.2mW/°C above TA= +70°C)...1454.5mW
Operating Temperature Ranges.........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow)
SOT23 ..........................................................................+240°C
TDFN ............................................................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Note 1)
Resolution 10 Bits
Relative Accuracy (Note 2) INL ±1.0 LSB
Differential Nonlinearity DNL No missing codes over temperature ±1.0 LSB
Offset Error ±0.5 ±1.0 LSB
Gain Error (Note 3) ±1.0 ±2.0 LSB
Gain Temperature Coefficient ±0.8 ppm/°C
Channel-to-Channel Offset ±0.1 LSB
Channel-to-Channel Gain Matching ±0.1 LSB
Input Common-Mode Rejection CMR VCM = 0V to VDD; zero scale input ±0.1 mV
DYNAMIC SPECIFICATIONS: (fIN (sine-wave) = 10kHz, VIN = 4.096Vp-p for MAX1086/MAX1088 or VIN = 2.5VPP
for MAX1087/MAX1089, 150ksps, fSCLK = 8MHz, AIN- = GND for MAX1088/MAX1089)
Signal to Noise Plus Distortion SINAD 61 dB
Total Harmonic Distortion
(up to the 5th harmonic) THD -70 dB
Spurious-Free Dynamic Range SFDR 70 dB
Full-Power Bandwidth -3dB point 1 MHz
Full-Linear Bandwidth SINAD > 56dB 100 kHz
CONVERSION RATE
Conversion Time tCONV 3.7 µs
T/H Acquisition Time tACQ 1.4 µs
Aperture Delay 30 ns
Aperture Jitter <50 ps
Maximum Serial Clock Frequency fSCLK 8 MHz
Duty Cycle 30 70 %
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1087/MAX1089, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1086/MAX1088,
0.1µF capacitor at REF, fSCLK = 8MHz (50% duty cycle), AIN- = GND for MAX1088/MAX1089. TA= TMIN to TMAX, unless otherwise
noted. Typical values at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Unipolar 0 VREF
Input Voltage Range (Note 4) Bipolar -VREF /2 VREF/2 V
Input Leakage Current C hannel not sel ected or conver si on stop p ed ±0.01 ±1µA
Input Capacitance 34 pF
EXTERNAL REFERENCE INPUT
Input Voltage Range VREF 1.0 VDD
+50mV V
VREF = +2.5V at 150ksps 16 30
VREF = +4.096V at 150ksps 26 45
Input Current IREF
Acquisition/Between conversions ±0.01 ±1
µA
DIGITAL INPUTS/OUTPUTS (SCLK, CNVST, DOUT)
Input Low Voltage VIL 0.8 V
Input High Voltage VIH VDD -1 V
Input Leakage Current IL±0.1 µA
Input Capacitance CIN 15 pF
ISINK = 2mA 0.4 V
Output Low Voltage VOL ISINK = 4mA 0.8 V
Output High Voltage VOH ISOURCE = 1.5mA VDD
-0.5 V
Three-State Leakage Current CNVST = GND ±10 µA
Three-State Output Capacitance COUT CNVST = GND 15 pF
POWER REQUIREMENTS
MAX1086/MAX1088 4.75 5.0 5.25
Positive Supply Voltage VDD MAX1087/MAX1089 2.7 3.0 3.6 V
fSAMPLE =150ksps 245 350
fSAMPLE =100ksps 150
fSAMPLE =10ksps 15
VDD = +3V
fSAMPLE =1ksps 2
fSAMPLE =150ksps 320 400
fSAMPLE =100ksps 215
fSAMPLE =10ksps 22
VDD = +5V
fSAMPLE =1ksps 2.5
Positive Supply Current IDD
Shutdown 0.2 5
µA
VDD = 5V ±5%; full-scale input ±0.1 1.0
Positive Supply Rejection PSR VDD = +2.7V to +3.6V; full-scale input ±0.1 ±1.2 mV
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS (Figures 1 and 2)
(VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1087/MAX1089, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1086/MAX1088,
0.1µF capacitor at REF, fSCLK = 8MHz (50% duty cycle); AIN- = GND for MAX1088/MAX1089. TA= TMIN to TMAX, unless otherwise
noted. Typical values at TA= +25°C.)
PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Pulse Width High tCH 38 ns
SCLK Pulse Width Low tCL 38 ns
SCLK Fall to DOUT Transition tDOT CLOAD = 30pF 60 ns
SCLK Rise to DOUT Disable tDOD CLOAD = 30pF 100 500 ns
CNVST Rise to DOUT Enable tDOE CLOAD = 30pF 80 ns
CNVST Fall to MSB Valid tDOV CLOAD = 30pF 3.7 μs
CNVST Pulse Width tCSW 30 ns
Note 1: Unipolar input.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: The absolute input range for the analog inputs is from GND to VDD.
• • •
• • •
• • •
CNVST
SCLK
DOUT
tDOE
HIGH-Z HIGH-Z
tCSW
tDOT
tCL
tCH
tDOD
DOUT
6kΩ
6kΩ
CL
GND
DOUT
CL
GND
VDD
a) HIGH -Z TO VOH, VOL TO VOH, AND VOH TO HIGH -Z a) HIGH -Z TO VOL, VOH TO VOL, AND VOL TO HIGH -Z
Figure 1. Detailed Serial-Interface Timing Sequence
Figure 2. Load Circuits for Enable/Disable Times
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
_______________________________________________________________________________________
5
-1.0
-0.6
-0.8
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
0 400200 600 800 1000 1200
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX1086-9 toc01
OUTPUT CODE
INL (LSB)
MAX1087/MAX1089
0 400200 600 800 1000 1200
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX1086-9 toc02
OUTPUT CODE
INL (LSB)
-1.0
-0.6
-0.8
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0 MAX1086/MAX1088
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1086-9 toc03
OUTPUT CODE
DNL (LSB)
0 400 600200 800 1000 1200
-1.0
-0.6
-0.8
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0 MAX1087/MAX1089
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1086-9 toc04
OUTPUT CODE
0 400 600200 800 1000 1200
DNL (LSB)
-1.0
-0.6
-0.8
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0 MAX1086/MAX1088 1000
1
0.001 10 1000
SUPPLY CURRENT
vs. SAMPLING RATE
10
100
MAX1086-9 toc05
SAMPLING RATE (ksps)
SUPPLY CURRENT (μA)
1.0
0.1
MAX1087/MAX1089 1000
1
SUPPLY CURRENT
vs. SAMPLING RATE
10
100
MAX1086-9 toc06
SAMPLING RATE (ksps)
SUPPLY CURRENT (μA)
0.1
MAX1086/MAX1088
0.001 10 10001.0
180
280
230
330
380
2.7 3.73.2 4.2 4.7 5.2
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1086-9 toc07
VDD (V)
SUPPLY CURRENT ( μA)
0
0.10
0.05
0.20
0.15
0.30
0.25
0.40
0.35
0.45
0.50
2.7 3.73.2 4.2 4.7 5.2
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
MAX1086-9 toc08
VDD (V)
SHUTDOWN CURRENT (nA)
Typical Operating Characteristics
(VDD = +3.0V, VREF = +2.5V for MAX1087/MAX1089 or VDD = +5.0V, VREF = +4.096V for MAX1086/MAX1088, 0.1µF capacitor at
REF, fSCLK = 8MHz, (50% Duty Cycle), AIN- = GND for MAX1088/1089, TA= +25°C, unless otherwise noted.)
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD = 3.0V, VREF = 2.5V for MAX1087/MAX1089 or VDD = 5.0V, VREF = +4.096V for MAX1086MAX1088, 0.1µF capacitor at REF,
fSCLK = 8MHz, (50% Duty Cycle), AIN- = GND for MAX1088/89, TA= +25°C, unless otherwise noted.)
0
100
50
250
200
150
300
-40 0 20-20 40 60 80
SHUTDOWN CURRENT
vs. TEMPERATURE
MAX1086-9 toc10
TEMPERATURE (°C)
SHUTDOWN CURRENT (nA)
-1.00
-0.40
0.60
-0.80
0.00
-0.20
0.80
0.60
0.40
0.20
1.00
-40 -20 0 20 40 60 80
OFFSET ERROR
vs. TEMPERATURE
MAX1086-9 toc11
TEMPERATURE (°C)
OFFSET ERROR (LSB)
-1.0
-0.6
-0.8
-0.2
-0.4
0.2
0.4
0.6
0.8
0
1.0
2.7 3.7 4.23.2 4.7 5.2
OFFSET ERROR
vs. SUPPLY VOLTAGE
MAX1086-9 toc12
VDD (V)
OFFSET ERROR (LSB)
-40 0 20-20 40 60 80
GAIN ERROR
vs. TEMPERATURE
MAX1086-9 toc13
TEMPERATURE (°C)
GAIN ERROR (LSB)
-1.0
-0.6
-0.8
-0.2
-0.4
0.2
0.4
0.6
0.8
0
1.0
2.7 3.73.2 4.2 4.7 5.2
GAIN ERROR
vs. SUPPLY VOLTAGE
MAX1086-9 toc14
VDD (V)
GAIN ERROR (LSB)
-1.0
-0.6
-0.8
-0.2
-0.4
0.2
0.4
0.6
0.8
0
1.0
-140.00
-120.00
-100.00
-80.00
-60.00
-40.00
-20.00
0.00
20.00
03015 45 60
FFT PLOT (SINAD)
MAX1086-9 toc15
FREQUENCY (kHz)
AMPLITUDE (dB)
180
280
230
330
380
-40 0-20 20 40 60 80
SUPPLY CURRENT
vs. TEMPERATURE
MAX1086-9 toc09
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
_______________________________________________________________________________________ 7
Detailed Description
The MAX1086–MAX1089 analog-to-digital converters
(ADCs) use a successive-approximation conversion (SAR)
technique and an on-chip track-and-hold (T/H) structure to
convert an analog signal into a 10-bit digital result.
The serial interface provides easy interfacing to micro-
processors (µPs). Figure 3 shows the simplified internal
structure for the MAX1086/MAX1087 (2–channels, sin-
gle-ended) and the MAX1088/MAX1089 (1–channel,
true-differential).
True-Differential Analog Input Track/Hold
The equivalent circuit of Figure 4 shows the
MAX1086–MAX1089’s input architecture which is com-
posed of a T/H, input multiplexer, comparator, and
switched-capacitor DAC. The T/H enters its tracking
mode on the rising edge of CNVST. The positive input
capacitor is connected to AIN1 or AIN2 (MAX1086/
MAX1087) or AIN+ (MAX1088/MAX1089). The negative
input capacitor is connected to GND (MAX1086/
MAX1087) or AIN- (MAX1088/MAX1089). The T/H enters
its hold mode on the falling edge of CNVST and the dif-
ference between the sampled positive and negative
input voltages is converted. The time required for the T/H
to acquire an input signal is determined by how quickly
its input capacitance is charged. If the input signal’s
source impedance is high, the acquisition time length-
ens, and CNVST must be held high for a longer period of
time. The acquisition time, tACQ, is the maximum time
needed for the signal to be acquired, plus the power-up
time. It is calculated by the following equation:
tACQ = 7 x (RS+ RIN) x 24pF + tPWR
Pin Description
NAME
PIN MAX1086
MAX1087
MAX1088
MAX1089
FUNCTION
1V
DD VDD Positive Supply Voltage. +2.7V to +3.6V (MAX1087/MAX1089); +4.75V to +5.25V
(MAX1086/MAX1088). Bypass with a 0.1µF capacitor to GND.
2 AIN1 AIN+ Analog Input Channel 1 (MAX1086/MAX1087) or Positive Analog Input (MAX1088/MAX1089)
3 AIN2 AIN- Analog Input Channel 2 (MAX1086/MAX1087) or Negative Analog Input (MAX1088/MAX1089)
4 GND GND Ground
5 REF REF External Reference Voltage Input. Sets the analog voltage range. Bypass with a 0.1µF
capacitor to GND.
6 CNVST CNVST
Conversion Start. A rising edge powers-up the IC and places it in track mode. At the falling
edge of CNVST, the device enters hold mode and begins conversion. CNVST also selects the
input channel (MAX1086/MAX1087) or input polarity (MAX1088/MAX1089).
7 DOUT DOUT
Serial Data Output. DOUT transitions the falling edge of SCLK. DOUT goes low at the start of a
conversion and presents the MSB at the completion of a conversion. DOUT goes high-
impedance once data has been fully clocked out.
8 SCLK SCLK Serial Clock Input. Clocks out data at DOUT MSB first.
— EP — Exposed Pad (TDFN only). Connect the exposed pad to ground or leave unconnected.
10-BIT
SAR
ADC
CONTROL
OSCILLATOR
INPUT SHIFT
REGISTER
T/H
REF
CNVST
SCLK
DOUT
AIN2
(AIN-)
AIN1
(AIN+)
MAX1086–MAX1089
( ) ARE FOR MAX1088/MAX1089
Figure 3. Simplified Functional Diagram
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
8 _______________________________________________________________________________________
where RIN = 1.5kΩ, RSis the source impedance of the
input signal, and tPWR = 1µs is the power-up time of the
device.
Note: tACQ is never less than 1.4µs and any source
impedance below 300Ωdoes not significantly affect the
ADC‘s AC performance. A high impedance source can
be accommodated either by lengthening tACQ or by
placing a 1µF capacitor between the positive and neg-
ative analog inputs.
Selecting AIN1 or AIN2
(MAX1086/MAX1087)
Select between the MAX1086/MAX1087’s two positive
input channels using the CNVST pin. If AIN1 is desired
(Figure 5a), drive CNVST high to power-up the ADC
and place the T/H in track mode with AIN1 connected
to the positive input capacitor. Hold CNVST high for
tACQ to fully acquire the signal. Drive CNVST low to
place the T/H in hold mode. The ADC will then perform
a conversion and shutdown automatically. The MSB is
available at DOUT after 3.7µs. Data can then be
clocked out using SCLK. Be sure to clock out all 12 bits
of data (the 10-bit result plus two sub-bits) before dri-
ving CNVST high for the next conversion. If all 12 bits of
data are not clocked out before CNVST is driven high,
AIN2 will be selected for the next conversion.
If AIN2 is desired (Figure 5b), drive CNVST high for at
least 30ns. Next, drive it low for at least 30ns, and then
high again. This will power-up the ADC and place the
T/H in track mode with AIN2 connected to the positive
input capacitor. Now hold CNVST high for tACQ to fully
acquire the signal. Drive CNVST low to place the T/H in
hold mode. The ADC will then perform a conversion
and shutdown automatically. The MSB is available at
DOUT after 3.7µs. Data can then be clocked out using
SCLK. If all 12 bits of data are not clocked out before
CNVST is driven high, AIN2 will be selected for the next
conversion.
Selecting Unipolar or Bipolar Conversions
(MAX1088/MAX1089)
Initiate true-differential conversions with the
MAX1088/MAX1089’s unipolar and bipolar modes,
using the CNVST pin. AIN+ and AIN- are sampled at
the falling edge of CNVST. In unipolar mode, AIN+ can
exceed AIN- by up to VREF. The output format is
straight binary. In bipolar mode, either input can
exceed the other by up to VREF/2. The output format is
two’s complement.
Note: In both modes, AIN+ and AIN- must not exceed
VDD by more than 50mV or be lower than GND by more
than 50mV.
If unipolar mode is desired (Figure 5a), drive CNVST
high to power-up the ADC and place the T/H in track
mode with AIN+ and AIN- connected to the input
capacitors. Hold CNVST high for tACQ to fully acquire
the signal. Drive CNVST low to place the T/H in hold
mode. The ADC will then perform a conversion and
shutdown automatically. The MSB is available at DOUT
after 3.7µs. Data can then be clocked out using SCLK.
Be sure to clock out all 12 bits (the 10-bit result plus
two sub-bits) of data before driving CNVST high for the
next conversion. If all 12 bits of data are not clocked
out before CNVST is driven high, bipolar mode will be
selected for the next conversion.
If bipolar mode is desired (Figure 5b), drive CNVST
high for at least 30ns. Next, drive it low for at least 30ns
and then high again. This will place the T/H in track
mode with AIN+ and AIN- connected to the input
capacitors. Now hold CNVST high for tACQ to fully
acquire the signal. Drive CNVST low to place the T/H in
hold mode. The ADC will then perform a conversion
and shutdown automatically. The MSB is available at
DOUT after 3.7µs. Data can then be clocked out using
SCLK. If all 12 bits of data are not clocked out before
CNVST is driven high, bipolar mode will be selected for
the next conversion.
Input Bandwidth
The ADCs input tracking circuitry has a 1MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
RIN+
+
-
HOLD
RIN-
CIN+
REF
GND DAC
CIN-
TRACK
VDD/2
COMPARATOR
GND(AIN-)
AIN2
AIN1(AIN+)
HOLD
HOLD
*( ) APPLIES TO MAX1088/1089
Figure 4. Equivalent Input Circuit
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
_______________________________________________________________________________________ 9
Analog Input Protection
Internal protection diodes which clamp the analog input
to VDD and GND allow the analog input pins to swing
from GND - 0.3V to VDD + 0.3V without damage. Both
inputs must not exceed VDD by more than 50mV or be
lower than GND by more than 50mV for accurate conver-
sions. If an off-channel analog input voltage exceeds
the supplies, limit the input current to 2mA.
Internal Clock
The MAX1086–MAX1089 operate from an internal oscilla-
tor, which is accurate within 10% of the 4MHz specified
clock rate. This results in a worse case conversion time
of 3.7µs. The internal clock releases the system micro-
processor from running the SAR conversion clock and
allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0 to
8MHz.
CNVST
SCLK
DOUT
tACQ
tCONV
SAMPLING INSTANT
41812
B9
MSB B8 B7 B6 B5
B4
B3 B2 B1 B0
LSB S1 S0
HIGH-Z
HIGH-Z
CNVST
SCLK
DOUT
tACQ
tCONV
SAMPLING INSTANT
41812
B9
MSB B8 B7 B6 B5
B4
B3 B2 B1 B0
LSB S1 S0
HIGH-Z
HIGH-Z
Figure 5b. Single Conversion AIN2 vs. GND (MAX1086/MAX1087), bipolar mode AIN+ vs. AIN- (MAX1088/MAX1089)
Figure 5a. Single Conversion AIN1 vs. GND (MAX1086/MAX1087), unipolar mode AIN+ vs. AIN- (MAX1088/MAX1089)
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
10 ______________________________________________________________________________________
Output Data Format
Figures 5a and 5b illustrate the conversion timing for
the MAX1086–MAX1089. The 10-bit conversion result is
output in MSB first format, followed by two sub-bits (S1
and S0). Data on DOUT transitions on the falling edge
of SCLK. All 12-bits must be clocked out before CNVST
transitions again. For the MAX1088/MAX1089, data is
straight binary for unipolar mode and two’s comple-
ment for bipolar mode. For the MAX1086/MAX1087,
data is always straight binary.
Applications Information
Automatic Shutdown Mode
With CNVST low, the MAX1086–MAX1089 defaults to an
AutoShutdown state (<0.2µA) after power-up and
between conversions. After detecting a rising edge on
CNVST, the part powers up, sets DOUT low and enters
track mode. After detecting a falling-edge on CNVST, the
device enters hold mode and begins the conversion. A
maximum of 3.7µs later, the device completes conver-
sion, enters shutdown and MSB is available at DOUT.
External Reference
An external reference is required for the MAX1086–
MAX1089. Use a 0.1µF bypass capacitor for best per-
formance. The reference input structure allows a volt-
age range of +1V to VDD + 50mV.
Transfer Function
Figure 6 shows the unipolar transfer function for the
MAX1086–MAX1089. Figure 7 shows the bipolar transfer
function for the MAX1088/MAX1089. Code transitions
occur halfway between successive-integer LSB values.
Connection to Standard Interfaces
The MAX1086–MAX1089 feature a serial interface that is
fully compatible with SPI, QSPI, and MICROWIRE. If a
serial interface is available, establish the CPU’s serial
interface as a master, so that the CPU generates the seri-
al clock for the ADCs. Select a clock frequency up to
8MHz.
How to Perform a Conversion
1) Use a general purpose I/O line on the CPU to hold
CNVST low between conversions.
2) Drive CNVST high to acquire AIN1(MAX1086/
MAX1087) or unipolar mode (MAX1088/MAX1089).
To acquire AIN2(MAX1086/MAX1087) or bipolar
mode (MAX1088/MAX1089), drive CNVST low and
high again.
3) Hold CNVST high for 1.4µs.
4) Drive CNVST low and wait approximately 3.7µs for
conversion to complete. After 3.7µs, the MSB is
available at DOUT.
5) Activate SCLK for a minimum of 12 rising clock
edges. DOUT transitions on SCLK’s falling edge
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
123
0FS
FS - 3/2LSB
FS = VREF
ZS = GND
INPUT VOLTAGE (LSB)
1LSB = VREF
1024
MAX1086–
MAX1089
Figure 6. Unipolar Transfer Function
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
- FS 0
INPUT VOLTAGE (LSB)
OUTPUT CODE
ZS = 0
+FS - 1LSB
*VCOM VREF / 2 *VIN = (AIN+) - (AIN-)
FS = VREF
2
-FS =
-VREF
2
1LSB = VREF
1024
≤
MAX1088/MAX1089
Figure 7. Bipolar Transfer Function
and is available in MSB-first format. Observe the
SCLK to DOUT valid timing characteristic. Clock
data into the µP on SCLK’s rising-edge.
SPI and MICROWIRE Interface
When using SPI interface (Figure 8a) or MICROWIRE
(Figure 8a and 8b), set CPOL = CPHA = 0. Two 8-bit
readings are necessary to obtain the entire 10-bit result
from the ADC. DOUT data transitions on the serial
clock’s falling edge and is clocked into the µP on
SCLK’s rising edge. The first 8-bit data stream contains
the first 8-bits of DOUT starting with the MSB. The sec-
ond 8-bit data stream contains the remaining two result
bits (B1, B0) and two trailing sub-bits (S1, S0). DOUT
then goes high impedance.
QSPI Interface
Using the high-speed QSPI interface (Figure 9a) with
CPOL = 0 and CPHA = 0, the MAX1086–MAX1089
support a maximum fSCLK of 8MHz. One 8- to16-bit
reading is necessary to obtain the entire 10-bit result
from the ADC. DOUT data transitions on the serial
clock’s falling edge and is clocked into the µP on
SCLK’s rising edge. The first 10 bits are the data and
the next two bits are sub-bits (S1, S0). DOUT then
goes high impedance (Figure 9b).
PIC16 and SSP Module and
PIC17 Interface
The MAX1086–MAX1089 are compatible with a
PIC16/PIC17 microcontroller (µC), using the synchro-
nous serial port (SSP) module
To establish SPI communication, connect the controller
as shown in Figure 10a and configure the PIC16/PIC17
as system master. This is done by initializing its syn-
chronous serial port control register (SSPCON) and
synchronous serial port status register (SSPSTAT) to
the bit patterns shown in Tables 1 and 2.
In SPI mode, the PIC16/PIC17 µCs allow eight bits of
data to be synchronously transmitted and received
simultaneously. Two consecutive 8-bit readings (Figure
10b) are necessary to obtain the entire 10-bit result
from the ADC. DOUT data transitions on the serial
clock’s falling edge and is clocked into the µC on
SCLK’s rising edge. The first 8-bit data stream contains
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
______________________________________________________________________________________ 11
Figure 8a. SPI Connections Figure 8b. MICROWIRE Connections
CNVST
SCLK
DOUT
I/O
SCK
MISO VDD
SS
SPI
MAX1086–
MAX1089
MAX1086–
MAX1089
CNVST
SCLK
DOUT
I/O
SK
SI
MICROWIRE
Table 1. Detailed SSPCON Register Content
CONTROL BIT MAX1086–MAX1089
SETTINGS SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON)
WCOL Bit 7 X Write Collision Detection Bit
SSPOV Bit 6 X Receive Overflow Detect Bit
SSPEN Bit 5 1
Synchronous Serial Port Enable Bit.
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins.
CKP Bit 4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3 Bit 3 0
SSPM2 Bit 2 0
SSPM1 Bit 1 0
SSPM0 Bit 0 1
Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects
fCLK= fOSC / 16.
X = Don’t care
MAX1086–MAX1089
the first eight data bits starting with the MSB. The sec-
ond 8-bit data stream contains the remaining bits, D1
through D0, and the two sub-bits S1 and S0.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one starpoint (Figure 11), connecting the two ground
systems (analog and digital). For lowest-noise opera-
tion, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
High-frequency noise in the power supply (VDD) may
degrade the performance of the ADC’s fast comparator.
Bypass VDD to the star ground with a 0.1µF capacitor,
located as close as possible to the MAX1086–MAX1089s
power supply pin. Minimize capacitor lead length for best
supply-noise rejection. Add an attenuation resistor (5Ω) if
the power supply is extremely noisy.
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
12 ______________________________________________________________________________________
CNVST
SCLK
DOUT
CS
SCK
MISO VDD
SS
QSPI
MAX1086–
MAX1089
Figure 9a. QSPI Connections
Table 2. Detailed SSPSTAT Register Content
X = Don’t care
D/A
CONTROL BIT MAX1086–MAX1089
SETTINGS SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)
Bit 5 X Data Address Bit
P Bit 4 X Stop Bit
S Bit 3 X
R/W
SMP Bit 7 0 SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
CKE Bit 6 1 SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
Bit 2 X
UA Bit 1 X
BF Bit 0 X
Start Bit
Buffer Full Status Bit
Update Address
Read/Write Bit Information
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
CNVST
1ST BYTE READ
SCLK
DOUT
2ND BYTE READ
SAMPLING INSTANT
418
12
B9
MSB B8 B7 B6 B5
B4
B3 B2 B1 B0
LSB S1 S0 HIGH-Z
16
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The sta-
tic linearity parameters for the MAX1086–MAX1089 are
measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
______________________________________________________________________________________ 13
CNVST
SCLK
DOUT
SAMPLING INSTANT
418
12
B9
MSB B8 B7 B6 B5
B4
B3 B2 B1 B0
LSB S1 S0 HIGH-Z
16
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
SCK
SDI
GND GND
I/O
SCLK
DOUT
CNVST
VDD VDD
MAX1086–
MAX1089
PIC16/PIC17
Figure 10a. SPI Interface Connection for a PIC16/PIC17 Controller
CNVST
1ST BYTE READ
SCLK
DOUT
2ND BYTE READ
SAMPLING INSTANT
418
12
B9
MSB B8 B7 B6 B5
B4
B3 B2 B1 B0
LSB S1 S0 HIGH-Z
16
Figure 10b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
14 ______________________________________________________________________________________
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples. Aperture delay (tAD) is
the time between the rising edge of the sampling clock
and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-to-
digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N-bits):
SNR = (6.02 N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SINAD (dB) = 20 log (SignalRMS / NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order har-
monics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest distortion
component.
Chip Information
PROCESS: BiCMOS
THD V V V V V=+++
⎛
⎝⎞
⎠
⎛
⎝
⎜⎞
⎠
⎟
⋅20 223242521
log /
+3V OR +5V VLOGIC = +5V/+3V GND
SUPPLIES
DGND+5V/+3V
GND
0.1μF
VDD
DIGITAL
CIRCUITRY
MAX1086–
MAX1089
R* = 5Ω
*OPTIONAL
Figure 11. Power-Supply and Grounding Connections
PACKAGE
TYPE
PACKAGE
CODE OUTLINE NO. LAND
PATTERN NO.
8 SOT23 K8F-4 21-0078 90-0176
8 TDFN T833+2 21-0137 90-0059
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
MAX1086–MAX1089
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23 and TDFN
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
15
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES CHANGED
1 8/07 Added TDFN packages 1, 2, 7, 15, 16, 17
2 6/08 Added ETA packaging 1, 7
3 8/10 Added lead-free variants and soldering temperature 1, 2
