ON Semiconductor MC74VHC00 Quad 2-Input NAND Gate The MC74VHC00 is an advanced high speed CMOS 2-input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. * High Speed: tPD = 3.7ns (Typ) at VCC = 5V * Low Power Dissipation: ICC = 2A (Max) at TA = 25C * High Noise Immunity: VNIH = VNIL = 28% VCC * Power Down Protection Provided on Inputs * Balanced Propagation Delays * Designed for 2V to 5.5V Operating Range * Low Noise: VOLP = 0.8V (Max) * Pin and Function Compatible with Other Standard Logic Families * Latchup Performance Exceeds 300mA * ESD Performance: HBM > 2000V; Machine Model > 200V * Chip Complexity: 32 FETs or 8 Equivalent Gates A1 B1 A2 B2 A3 B3 A4 B4 D SUFFIX 14-LEAD SOIC PACKAGE CASE 751A-03 DT SUFFIX 14-LEAD TSSOP PACKAGE CASE 948G-01 M SUFFIX 14-LEAD SOIC EIAJ PACKAGE CASE 965-01 ORDERING INFORMATION 1 3 2 4 6 5 MC74VHCXXD MC74VHCXXDT MC74VHCXXM Y1 Y2 FUNCTION TABLE Y = AB 9 8 10 12 11 13 SOIC TSSOP SOIC EIAJ Inputs Y3 Y4 Output A B Y L L H H L H L H H H H L Figure 1. LOGIC DIAGRAM VCC B4 A4 Y4 B3 A3 Y3 14 13 12 11 10 9 8 1 2 3 4 5 6 7 A1 B1 Y1 A2 B2 Y2 GND Figure 2. Pinout: 14-Lead Packages (Top View) Semiconductor Components Industries, LLC, 2001 March, 2001 - Rev. 3 1 Publication Order Number: MC74VHC00/D MC74VHC00 IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIII III IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III MAXIMUM RATINGS* Symbol Value Unit VCC DC Supply Voltage Parameter - 0.5 to + 7.0 V Vin DC Input Voltage - 0.5 to + 7.0 V Vout DC Output Voltage - 0.5 to VCC + 0.5 V IIK Input Diode Current - 20 mA IOK Output Diode Current 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature - 65 to + 150 C SOIC Packages TSSOP Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/C from 65 to 125C TSSOP Package: - 6.1 mW/C from 65 to 125C IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIII III IIIIIIIII IIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III IIII IIII IIII IIII IIIIIII IIIIIII III IIIIIIIII IIIIIII II IIII IIIIIII IIIIIII III IIII III IIII IIII IIII II IIII IIIIIII IIIIIII III IIII III IIII IIII IIII II II IIII IIIIIII IIIIIII III IIII III IIII IIII IIII IIII IIIIIII IIIIIII III IIII III IIII IIII IIII II II IIII IIIIIII IIIIIII III IIII III IIII IIII IIII IIII IIIIIII IIIIIII III IIII III IIII IIII IIIIII II IIII IIIIIII IIIIIII III IIII III IIII IIII IIII IIII IIIIIII IIIIIII III IIII III IIII IIII IIII II IIII IIIIIII IIIIIII III IIII III IIII IIII IIII II II IIII IIIIIII IIIIIII III IIII III IIII IIII IIII IIII IIIIIII IIIIIII III IIII III IIII IIII IIII II II IIII IIIIIII IIIIIII III IIII III IIII IIII IIII IIII IIIIIII IIIIIII III IIII III IIII IIII IIII II IIII IIIIIII IIIIIII III IIII III IIII IIII IIIIII RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 2.0 5.5 V DC Input Voltage 0 5.5 V DC Output Voltage 0 VCC V - 40 + 85 C 0 0 100 20 ns/V VCC DC Supply Voltage Vin Vout TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time VCC = 3.3V 0.3V VCC =5.0V 0.5V DC ELECTRICAL CHARACTERISTICS Symbol Parameter VCC V Test Conditions VIH High-Level Input Voltage 2.0 3.0 to 5.5 VIL Low-Level Input Voltage 2.0 3.0 to 5.5 VOH High-Level Output Voltage Vin = VIH or VIL IOH = - 50A Vin = VIH or VIL IOH = - 4mA IOH = - 8mA VOL Low-Level Output Voltage Vin = VIH or VIL IOL = 50A TA = 25C Min Min 1.9 2.9 4.4 3.0 4.5 2.58 3.94 3.0 4.5 http://onsemi.com Max 1.50 VCC x 0.7 0.50 VCC x 0.3 2.0 3.0 4.5 2 TA = - 40 to 85C Max 1.50 VCC x 0.7 2.0 3.0 4.5 Vin = VIH or VIL IOL = 4mA IOL = 8mA Typ 2.0 3.0 4.5 Unit V 0.50 VCC x 0.3 V V 1.9 2.9 4.4 2.48 3.80 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 0.36 0.36 0.44 0.44 V MC74VHC00 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIII III IIIIIIIII IIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIII III IIII III IIII IIII IIII II IIIIIIIII IIIIIII IIII IIIIIII IIIIIII III I III III IIII IIII IIII II IIII IIII IIIIIII IIIIIII III IIII III IIII IIII IIII II IIII IIIIIII IIIIIII III IIII III IIII IIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIII III IIII III IIII IIII IIII II IIII IIIIIIIII IIIIIIII IIIIIIIII IIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIII IIIIIIII IIII III IIII III IIII II IIIIIIIII IIIIII IIII IIIIIIIII IIIIIIII IIII III IIII III IIII II IIII IIIIIIIII IIIIIIII IIII III IIII III IIII II II IIII IIIIIIIII IIIIIIII IIII III IIII III IIII IIII IIIIIIIII IIIIIIII IIII III IIII III IIII II II IIII IIIIIIIII IIIIIIII IIII III IIII III IIII IIII IIIIIIIII IIIIIIII IIII III IIII III IIII II DC ELECTRICAL CHARACTERISTICS VCC V TA = 25C Symbol Parameter Max Unit Iin Input Leakage Current Vin = 5.5V or GND 0 to 5.5 0.1 1.0 A ICC Quiescent Supply Current Vin = VCC or GND 5.5 2.0 20.0 A Test Conditions Min Typ TA = - 40 to 85C Max Min AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25C Symbol Parameter Propagation Delay, A or B to Y tPLH, tPHL Cin Test Conditions Min TA = - 40 to 85C Typ Max Min Max Unit ns VCC = 3.3 0.3V CL = 15pF CL = 50pF 5.5 8.0 7.9 11.4 1.0 1.0 9.5 13.0 VCC = 5.0 0.5V CL = 15pF CL = 50pF 3.7 5.2 5.5 7.5 1.0 1.0 6.5 8.5 4 10 Input Capacitance 10 pF Typical @ 25C, VCC = 5.0V CPD 19 Power Dissipation Capacitance (Note 1.) pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/4 (per gate). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V, Measured in SOIC Package) TA = 25C Symbol Characteristic Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.3 0.8 V VOLV Quiet Output Minimum Dynamic VOL - 0.3 - 0.8 V VIHD Minimum High Level Dynamic Input Voltage 3.5 V VILD Maximum Low Level Dynamic Input Voltage 1.5 V TEST POINT A or B VCC 50% tPLH Y OUTPUT DEVICE UNDER TEST GND tPHL CL* 50% VCC *Includes all probe and jig capacitance Figure 3. Switching Waveforms Figure 4. Test Circuit INPUT Figure 5. Input Equivalent Circuit http://onsemi.com 3 MC74VHC00 OUTLINE DIMENSIONS D SUFFIX SOIC-14 CASE 751A-03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 8 -B- 1 P 7 PL 0.25 (0.010) 7 G M B M F R X 45 C -T- SEATING PLANE 0.25 (0.010) M T B J M K D 14 PL S A S http://onsemi.com 4 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 MC74VHC00 OUTLINE DIMENSIONS DT SUFFIX TSSOP CASE 948G-01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B -U- L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E CCC EE CCC EE CCC EE K A -V- K1 J J1 SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E http://onsemi.com 5 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC74VHC00 OUTLINE DIMENSIONS M SUFFIX SO-14 CASE 965-01 ISSUE O 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 8 Q1 E HE L 7 1 M DETAIL P Z D VIEW P A e c A1 b 0.13 (0.005) M 0.10 (0.004) http://onsemi.com 6 DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 --1.42 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 --0.056 MC74VHC00 Notes http://onsemi.com 7 MC74VHC00 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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