LTC5542
1
5542f
TYPICAL APPLICATION
DESCRIPTION
1.6GHz to 2.7GHz
High Dynamic Range
Downconverting Mixer
The LTC
®
5542 is part of a family of high dynamic range, high
gain, passive downconverting mixers covering the 600MHz
to 4GHz frequency range. The LTC5542 is optimized for
1.6GHz to 2.7GHz RF applications. The LO frequency
must fall within the 1.7GHz to 2.5GHz range for optimum
performance. A typical application is a LTE or WiMAX receiver
with a 2.3GHz to 2.7GHz RF input and low-side LO.
The LTC5542 is designed for 3.3V operation, however; the
IF amplifi er can be powered by 5V for the highest P1dB.
An integrated SPDT LO switch with fast switching accepts
two active LO signals, while providing high isolation.
The LTC5542’s high conversion gain and high dynamic
range enable the use of lossy IF fi lters in high-selectivity
receiver designs, while minimizing the total solution cost,
board space and system-level variation.
High Dynamic Range Downconverting Mixer Family
PART# RF RANGE LO RANGE
LTC5540 600MHz –1.3GHz 700MHz – 1.2GHz
LTC5541 1.3GHz – 2.3GHz 1.4GHz – 2.0GHz
LTC5542 1.6GHz – 2.7GHz 1.7GHz – 2.5GHz
LTC5543 2.3GHz – 4GHz 2.4GHz – 3.6GHz
FEATURES
APPLICATIONS
n Conversion Gain: 8dB at 2.4GHz
n IIP3: 26.8dBm at 2.4GHz
n Noise Figure: 9.9dB at 2.4GHz
n 17.3dB NF Under +5dBm Blocking
n High Input P1dB
n 3.3V Supply, 660mW Power Consumption
n Shutdown Pin
n 50Ω Single-Ended RF and LO Inputs
n LO Inputs 50Ω Matched when Shutdown
n High Isolation LO Switch
n 0dBm LO Drive Level
n High LO-RF and LO-IF Isolation
n Small Solution Size
n 20-Lead (5mm × 5mm) QFN package
n Wireless Infrastructure Receivers
(LTE, W-CDMA. TD-SCDMA, WiMAX, GSM1800)
n Point-to-Point Microwave Links
n High Dynamic Range Downmixer Applications
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
IF
AMP ADC
IF
RF
2300MHz
TO
2400MHz
LNA
BIAS
SYNTH 2
SYNTH 1
VCCIF
3.3V or 5V 22pF
22pF
0.7pF
1µF 150nH 150nH
1nF
1nF
190MHz
SAW
190MHz
BPF
IMAGE
BPF
RF
SHDN
22pF
SHDN
(0V/3.3V)
LTC5542
VCC2
VCC 3.3V
VCC1 VCC3 LOSEL
LO SELECT
(0V/3.3V)
LO
2160MHz
ALTERNATE LO FOR
FREQUENCY-HOPPING
4.7pF
4.7pF
LO1
LO2
IF+IF–
5542 TA01
1µF
LO
Wideband Receiver Wideband Conversion Gain, IIP3
and NF vs IF Output Frequency
IF OUTPUT FREQUENCY (MHz)
140
6.0
GC (dB)
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
11.0
8
IIP3 (dBm), SSB NF (dB)
26
24
22
20
18
16
14
12
10
28
150 230 240160 170 180
5542 TA01a
190 200 210 220
NF
RF = 2350 ±50MHz
LO = 2160MHz
PLO = 0dBm
TEST CIRCUIT IN FIGURE 1
±30MHz
IIP3
GC
LTC5542
2
5542f
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Mixer Supply Voltage (VCC1, VCC2)...........................3.8V
LO Switch Supply Voltage (VCC3).............................3.8V
IF Supply Voltage (IF+, IF–) ......................................5.5V
Shutdown Voltage (SHDN) ................–0.3V to VCC +0.3V
LO Select Voltage (LOSEL) ................–0.3V to VCC +0.3V
LO1, LO2 Input Power (1GHz to 3GHz) ...................9dBm
LO1, LO2 Input DC Voltage ....................................±0.5V
RF Input Power (1GHz to 3GHz) ...........................15dBm
RF Input DC Voltage ............................................... ±0.1V
Operating Temperature Range .................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Junction Temperature (TJ) .................................... 150°C
(Note 1)
20 19 18 17 16
6 7 8
TOP VIEW
21
GND
UH PACKAGE
20-LEAD (5mm s 5mm) PLASTIC QFN
9 10
5
4
3
2
1
11
12
13
14
15
NC
RF
CT
GND
SHDN
LO2
VCC3
GND
GND
LO1
IFBIAS
IF+
IF–
GND
IFGND
VCC2
LOBIAS
VCC1
LOSEL
GND
TJMAX = 150°C, θJA = 34°C/W, θJC = 3°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC5542IUH#PBF LTC5542IUH#TRPBF 5542 20-Lead (5mm x 5mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi
cations, go to: http://www.linear.com/tapeandreel/
AC ELECTRICAL CHARACTERISTICS
V
CC = 3.3V, VCCIF = 3.3V, SHDN = Low, TA = 25°C, PLO = 0dBm,
unless otherwise noted. Test circuit shown in Figure 1. (Notes 2, 3, 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
LO Input Frequency Range 1700 to 2500 MHz
RF Input Frequency Range Low-Side LO
High-Side LO
1900 to 2700
1600 to 2300
MHz
MHz
IF Output Frequency Range Requires External Matching 5 to 500 MHz
RF Input Return Loss ZO = 50, 1600MHz to 2700MHz >12 dB
LO Input Return Loss ZO = 50, 1700MHz to 2500MHz >12 dB
IF Output Return Loss Requires External Matching >12 dB
LO Input Power fLO = 1700MHz to 2500MHz –4 0 6 dBm
LO to RF Leakage fLO = 1700MHz to 2500MHz <–32 dBm
LO to IF Leakage fLO = 1700MHz to 2500MHz <–40 dBm
LO Switch Isolation LO1 Selected, 1700MHz < fLO < 2500MHz
LO2 Selected, 1700MHz < fLO < 2500MHz
49
52
dB
dB
RF to LO Isolation fRF = 1600MHz to 2700MHz >49 dB
RF to IF Isolation fRF = 1600MHz to 2700MHz >35 dB
LTC5542
3
5542f
Low-Side LO Downmixer Application: RF = 1900 to 2700MHz, IF = 190MHz, fLO = fRF–fIF
PARAMETER CONDITIONS MIN TYP MAX UNITS
Conversion Gain RF = 2150MHz
RF = 2400MHz
RF = 2650MHz
6.5
8.5
8.0
7.4
dB
Conversion Gain Flatness RF = 2350 ±30MHz, LO = 2160MHz, IF=190 ±30MHz ±0.15 dB
Conversion Gain vs Temperature TA = –40ºC to +85ºC, RF = 2400MHz –0.006 dB/°C
Input 3rd Order Intercept RF = 2150MHz
RF = 2400MHz
RF = 2650MHz
24.0
27.2
26.8
25.3
dBm
SSB Noise Figure RF = 2150MHz
RF = 2400MHz
RF = 2650MHz
9.9
9.9
10.2
dB
SSB Noise Figure Under Blocking fRF = 2400MHz, fLO = 2210MHz,
fBLOCK = 2500MHz, PBLOCK = 5dBm
17.3 dB
2RF – 2LO Output Spurious Product
(fRF = fLO + fIF/2)
fRF = 2305MHz at –10dBm, fLO = 2210MHz, fIF = 190MHz –62 dBc
3RF – 3LO Output Spurious Product
(fRF = fLO + fIF/3)
fRF = 2273.33MHz at –10dBm, fLO = 2210MHz, fIF = 190MHz –73 dBc
Input 1dB Compression RF = 2400MHz, VCCIF = 3.3V
RF = 2400MHz, VCCIF = 5V
11.3
14.7
dBm
AC ELECTRICAL CHARACTERISTICS
V
CC = 3.3V, VCCIF = 3.3V, SHDN = Low, TA = 25°C, PLO = 0dBm,
PRF = –3dBm (Δf = 2MHz for two-tone IIP3 tests),unless otherwise noted. Test circuit shown in Figure 1. (Notes 2, 3, 4)
High-Side LO Downmixer Application: RF = 1600-2300MHz, IF = 190MHz, fLO = fRF+fIF
PARAMETER CONDITIONS MIN TYP MAX UNITS
Conversion Gain RF = 1750MHz
RF = 1950MHz
RF = 2150MHz
6.5
8.8
8.5
8.0
dB
Conversion Gain Flatness RF = 1950MHz ±30MHz, LO = 2140MHz, IF = 190 ±30MHz ±0.20 dB
Conversion Gain vs Temperature TA = –40°C to 85°C, RF = 1950MHz –0.006 dB/°C
Input 3rd Order Intercept RF = 1750MHz
RF = 1950MHz
RF = 2150MHz
23.0
25.1
25.2
24.6
dBm
SSB Noise Figure RF = 1750MHz
RF = 1950MHz
RF = 2150MHz
9.0
9.4
10.3
11.0 dB
SSB Noise Figure Under Blocking fRF = 1950MHz, fLO = 2140MHz, fIF = 190MHz
fBLOCK = 1850MHz, PBLOCK = 5dBm
17.5 dB
2LO – 2RF Output Spurious Product
(fRF = fLO – fIF/2)
fRF = 2045MHz at –10dBm, fLO = 2140MHz
fIF = 190MHz
–67 dBc
3LO – 3RF Output Spurious Product
(fRF = fLO – fIF/3)
fRF = 2076.67MHz at –10dBm, fLO = 2140MHz
fIF = 190MHz
–73 dBc
Input 1dB Compression RF = 1950MHz, VCCIF = 3.3V
RF = 1950MHz, VCCIF = 5V
11.0
14.4
dBm
LTC5542
4
5542f
DC ELECTRICAL CHARACTERISTICS
V
CC = 3.3V, VCCIF = 3.3V, SHDN = Low, TA = 25°C, unless otherwise
noted. Test circuit shown in Figure 1. (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply Requirements (VCC, VCCIF)
VCC Supply Voltage (Pins 6, 8 and 14) 3.1 3.3 3.5 V
VCCIF Supply Voltage (Pins 18 and 19) 3.1 3.3 5.3 V
VCC Supply Current (Pins 6 + 8 + 14)
VCCIF Supply Current (Pins 18 + 19)
Total Supply Current (VCC + VCCIF)
99
100
199
116
120
236 mA
Total Supply Current – Shutdown SHDN = High 500 µA
Shutdown Logic Input (SHDN) Low = On, High = Off
SHDN Input High Voltage (Off) 3V
SHDN Input Low Voltage (On) 0.3 V
SHDN Input Current –0.3V to VCC + 0.3V –20 30 µA
Turn On Time 1µs
Turn Off Time 1.5 µs
LO Select Logic Input (LOSEL) Low = LO1 Selected, High = LO2 Selected
LOSEL Input High Voltage 3V
LOSEL Input Low Voltage 0.3 V
LOSEL Input Current –0.3V to VCC + 0.3V –20 30 µA
LO Switching Time 50 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC5542 is guaranteed functional over the operating
temperature range from –40°C to 85°C.
Note 3: SSB Noise Figure measured with a small-signal noise source,
bandpass fi lter and 6dB matching pad on RF input, bandpass fi lter and
6dB matching pad on the LO input, and no other RF signals applied.
Note 4: LO switch isolation is measured at the IF output port at the IF
frequency with fLO1 and fLO2 offset by 2MHz.
VCC Supply Current
vs Supply Voltage
(Mixer and LO Switch)
VCCIF Supply Current
vs Supply Voltage (IF Amplifi er)
Total Supply Current
vs Temperature (VCC + VCCIF)
TYPICAL DC PERFORMANCE CHARACTERISTICS
SHDN = Low, Test circuit shown in Figure 1.
VCC SUPPLY VOLTAGE (V)
3.0
90
SUPPLY CURRENT(mA)
108
106
104
102
100
98
96
94
92
110
3.1 3.5 3.63.2 3.3
5542 G01
3.4
85°C
25°C
–40°C
VCCIF SUPPLY VOLTAGE (V)
3.0
70
SUPPLY CURRENT (mA)
110
120
100
90
80
130
3.3 5.1 5.43.6 3.9 4.2 4.5
5542 G02
4.8
85°C
25°C
–40°C
TEMPERATURE (°C)
–45
170
SUPPLY CURRENT(mA)
220
210
190
200
180
230
–25 75 95–5 15 35
5542 G03
55
VCC = 3.3V, VCCIF = 5V
(DUAL SUPPLY)
VCC = VCCIF = 3.3V
(SINGLE SUPPLY)
LTC5542
5
5542f
TYPICAL AC PERFORMANCE CHARACTERISTICS
2150MHz Conversion Gain, IIP3
and NF vs LO Power
2400MHz Conversion Gain, IIP3
and NF vs LO Power
2650MHz Conversion Gain, IIP3
and NF vs LO Power
Conversion Gain, IIP3 and NF
vs Supply Voltage (Single Supply)
Conversion Gain, IIP3 and NF
vs IF Supply Voltage (Dual Supply)
2400MHz Conversion Gain, IIP3
and RF Input P1dB vs Temperature
Low-Side LO
VCC = 3.3V, VCCIF = 3.3V, SHDN = Low, TA = 25°C, PLO = 0dBm, PRF = –3dBm (–3dBm/tone for two-tone IIP3 tests, Δf = 2MHz),
IF = 190MHz, unless otherwise noted. Test circuit shown in Figure 1.
Conversion Gain, IIP3 and NF
vs RF Frequency LO Leakage vs LO Frequency RF Isolation vs RF Frequency
RF FREQUENCY (GHz)
1.9
6
GC (dB), IIP3 (dBm), NF (dB)
26
24
22
20
18
16
14
12
10
8
28
2.0 2.72.1 2.2 2.3 2.4 2.5
5542 G04
2.6
IIP3
GC
NF
LO FREQUENCY (GHz)
1.5
–60
LO LEAKAGE (dBm)
–30
–40
–50
–20
1.7 2.71.9 2.1 2.3 2.5
5542 G05
LO-IF
LO-RF
RF FREQUENCY (GHz)
1.5
25
ISOLATION (dB)
60
55
50
45
40
35
30
65
1.7 2.71.9 2.3 2.52.1
5541 G06
RF-LO
RF-IF
LO INPUT POWER (dBm)
–6
8
GC (dB), IIP3 (dBm)
SSB NF (dB)
26
24
22
20
18
16
14
12
10
28
0
18
16
14
12
10
8
6
4
2
20
–4 6–2 0 2
5542 G07
4
IIP3
–40°C
25°C
85°C
GC
NF
LO INPUT POWER (dBm)
–6
7
GC (dB), IIP3 (dBm)
SSB NF (dB)
25
23
21
19
17
15
13
11
9
27
0
18
16
14
12
10
8
6
4
2
20
–4 6–2 0 2
5542 G08
4
IIP3
–40°C
25°C
85°C
NF
GC
LO INPUT POWER (dBm)
–6
6
GC (dB), IIP3 (dBm)
SSB NF (dB)
24
22
20
18
16
14
12
10
8
26
1
19
17
15
13
11
9
7
5
3
21
–4 6–2 0 2
5542 G09
4
IIP3
NF
GC
–40°C
25°C
85°C
VCC, VCCIF SUPPLY VOLTAGE (V)
3.0
7
GC (dB), IIP3 (dBm)
SSB NF (dB)
25
23
21
19
17
15
13
11
9
27
0
18
16
14
12
10
8
6
4
2
20
3.1 3.63.2 3.3 3.4
5542 G10
3.5
–40°C
25°C
85°C
RF = 2400MHz
VCC = VCCIF
NF
GC
IIP3
VCCIF SUPPLY VOLTAGE (V)
3.0
7
GC (dB), IIP3 (dBm)
SSB NF (dB)
27
25
23
21
19
17
15
13
11
9
29
0
20
18
16
14
12
10
8
6
4
2
22
3.3 5.43.6 3.9 4.2 4.5 4.8
5542 G11
5.1
RF = 2400MHz
VCC = 3.3V
–40°C
25°C
85°C
NF
GC
IIP3
TEMPERATURE (°C)
–45
6
GC (dB), IIP3 (dBm), P1dB (dBm)
26
24
22
20
18
16
14
12
10
8
28
–25 95–5 15 35 55 75
5542 G12
GC
IIP3
P1dB
RF = 2400MHz
VCCIF = 3.3V
VCCIF = 5.0V
LTC5542
6
5542f
SSB Noise Figure
vs RF Blocker Level
LO Switch Isolation
vs LO Frequency–LO1 Selected
LO Switch Isolation
vs LO Frequency–LO2 Selected
Conversion Gain Distribution IIP3 Distribution SSB Noise Figure Distribution
TYPICAL AC PERFORMANCE CHARACTERISTICS
Low-Side LO
VCC = 3.3V, VCCIF = 3.3V, SHDN = Low, TA = 25°C, PLO = 0dBm, PRF = –3dBm (–3dBm/tone for 2-tone IIP3 tests, Δf = 2MHz),
IF = 190MHz, unless otherwise noted. Test circuit shown in Figure 1.
2-Tone IF Output Power, IM3 and
IM5 vs RF Input Power
Single-Tone IF Output Power, 2 × 2
and 3 × 3 Spur vs RF Input Power
2 × 2 and 3 × 3 Spur Suppression
vs LO Power
RF INPUT POWER (dBm/TONE)
–12
–80
OUTPUT POWER (dBm/TONE)
10
0
–10
–20
–30
–40
–50
–60
–70
20
–9 6–6 –3 0
5542 G13
3
IFOUT TA = 25°C
RF1 = 2399MHz
RF2 = 2401MHz
LO = 2210MHz
IM5
IM3
RF INPUT POWER (dBm)
–12
–80
OUTPUT POWER (dBm)
10
0
–10
–20
–30
–40
–50
–60
–70
20
–9 15–6 –3 0
5542 G14
36912
IFOUT
(RF = 2400MHz)
LO = 2210MHz
2RF-2LO
(RF = 2305MHz)
3RF-3LO
(RF = 2273.3MHz)
LO INPUT POWER (dBm)
–6
–80
RELATIVE SPUR LEVEL (dBc)
–55
–60
–65
–70
–75
–50
–4 6–2 0 2
5542 G15
4
RF = 2400MHz
PRF = –10dBm
LO = 2210MHz
2RF-2LO
(RF = 2305MHz)
3RF-3LO
(RF = 2273.3MHz)
RF BLOCKER POWER (dBm)
–25
9
SSB NF (dB)
14
15
16
17
18
13
12
11
10
19
–20 5–15 –10 –5
5542 G16
0
PLO = –3dBm
PLO = 0dBm
PLO = 3dBm
RF = 2400MHz
BLOCKER = 2500MHz
LO FREQUENCY (GHz)
1.5
40
ISOLATION (dB)
55
50
45
60
1.7 2.71.9 2.1 2.3 2.5
5542 G17
LOSEL = LOW
PLO1 = 0dBm
PLO2 = –3dBm
PLO2 = 0dBm
PLO2 = 3dBm
LO FREQUENCY (GHz)
1.5
40
ISOLATION (dB)
55
50
45
60
1.7 2.71.9 2.1 2.3 2.5
5542 G18
PLO1 = –3dBm
PLO1 = 0dBm
PLO1 = 3dBm
LOSEL = HIGH
PLO2 = 0dBm
High-Side LO
CONVERSION GAIN (dB)
7.5 7.7 7.9 8.1 8.3 8.5 8.7 8.9 9.1
0
DISTRIBUTION (%)
20
25
35
30
15
10
5
40
5542 G18a
85°C
25°C
–40°C
RF = 1950MHz
IIP3 (dBm)
23.8 24.2 24.6 25 25.4 25.8
0
DISTRIBUTION (%)
12
14
18
16
10
8
6
4
2
20
5542 G18b
85°C
25°C
–40°C
RF = 1950MHz
SSB NOISE FIGURE (dB)
8.2 8.6 9.0 9.4 9.8 10.2 10.6
0
DISTRIBUTION (%)
25
35
30
20
15
10
5
40
5542 G18c
85°C
25°C
–40°C
RF = 1950MHz
LTC5542
7
5542f
Conversion Gain, IIP3 and NF
vs RF Frequency
1950MHz Conversion Gain, IIP3
and RF Input P1dB vs Temperature
TYPICAL AC PERFORMANCE CHARACTERISTICS
High-Side LO
VCC = 3.3V, VCCIF = 3.3V, SHDN = Low, TA = 25°C, PLO = 0dBm, PRF = –3dBm (–3dBm/tone for 2-tone IIP3 tests, Δf = 2MHz),
IF = 190MHz, unless otherwise noted. Test circuit shown in Figure 1.
1950MHz SSB Noise Figure
vs RF Blocker Level
1750MHz Conversion Gain, IIP3
and NF vs LO Power
2150MHz Conversion Gain, IIP3
and NF vs LO Power
1950MHz Conversion Gain, IIP3
and NF vs LO Power
2-Tone IF Output Power, IM3 and
IM5 vs RF Input Power
2 × 2 and 3 × 3 Spur Suppression
vs LO Power
Single-Tone IF Output Power, 2 × 2
and 3 × 3 Spurs vs RF Input Power
RF FREQUENCY (GHz)
1.5
7
GC (dB), IIP3 (dBm)
SSB NF (dB)
23
25
21
19
17
15
13
11
9
27
5
13
14
12
11
10
9
8
7
6
15
1.6 2.31.7 1.8 1.9
5542 G19
2.0 2.1 2.2
IIP3
NF
GC
RF BLOCKER POWER (dBm)
–25
9
SSB NF (dB)
17
18
19
16
15
14
13
12
11
10
20
–20 5–15 –10 –5
5542 G20
0
RF = 1950MHz
BLOCKER = 1850MHz
PLO = –3dBm
PLO = 0dBm
PLO = 3dBm
TEMPERATURE (°C)
–45
8
GC (dB), IIP3 (dBm), P1dB (dBm)
24
22
20
18
16
14
12
10
26
–25 95–5 15 35
5542 G21
55 75
IIP3
P1dB
GC
VCCIF = 3.3V
VCCIF = 5.0V
RF = 1950MHz
LO INPUT POWER (dBm)
–6
8
GC (dB), IIP3 (dBm)
24
22
20
18
16
14
12
10
26
0
SSB NF (dB)
16
14
12
10
8
6
4
2
18
–4 6–2 0 2
5542 G22
4
IIP3
NF
–40°C
25°C
85°C
GC
LO INPUT POWER (dBm)
–6
7
GC (dB), IIP3 (dBm)
23
21
19
17
15
13
11
9
25
0
SSB NF (dB)
16
14
12
10
8
6
4
2
18
–4 6–2 0 2
5542 G23
4
IIP3
–40°C
25°C
85°C
NF
GC
RF INPUT POWER (dBm/TONE)
–12
–80
OUTPUT POWER (dBm/TONE)
10
0
–10
–20
–30
–40
–50
–60
–70
20
–9 6–6 –3 0
5542 G24
3
IM3 IM5
IFOUT
RF1 = 1949MHz
RF2 = 1951MHz
LO = 2140MHz
RF INPUT POWER (dBm)
–12
–80
OUTPUT POWER (dBm)
10
0
–10
–20
–30
–40
–50
–60
–70
20
–9 15–6 –3 0
5542 G25
36912
IFOUT
(RF = 1950MHz)
LO = 2140MHz
3LO-3RF
(RF = 2076.67MHz)
2LO-2RF
(RF = 2045MHz)
LO INPUT POWER (dBm)
–6
8
GC (dB), IIP3 (dBm)
24
22
20
18
16
14
12
10
26
0
SSB NF (dB)
16
14
12
10
8
6
4
2
18
–4 6–2 0 2
5542 G22b
4
NF
IIP3
–40°C
25°C
85°C
GC
LO INPUT POWER (dBm)
–6
–80
RELATIVE SPUR LEVEL (dBc)
–55
–60
–65
–70
–75
–50
–4 6–2 0 2
5542 G26
4
RF = 1950MHz
PRF = –10dBm
LO = 2140MHz
2LO-2RF
(RF = 2045MHz)
3LO-3RF
(RF = 2076.67MHz)
LTC5542
8
5542f
PIN FUNCTIONS
NC (Pin 1): This pin is not connected internally. It can be
left fl oating, connected to ground or to VCC.
RF (Pin 2): Single-Ended Input for the RF Signal. This pin
is internally connected to the primary side of the RF input
transformer, which has low DC resistance to ground. A
series DC-blocking capacitor should be used to avoid
damage to the integrated transformer. The RF input is
impedance matched, as long as the selected LO input is
driven with a 0dBm ±6dB source between 1.7GHz and
2.5GHz.
CT (Pin 3): RF Transformer Secondary Center-Tap. This
pin may require a bypass capacitor to ground. See the
Applications Information section. This pin has an internally
generated bias voltage of 1.2V. It must be DC-isolated
from ground and VCC.
GND (Pins 4, 10, 12, 13, 17, Exposed Pad Pin 21):
Ground. These pins must be soldered to the RF ground
plane on the circuit board. The exposed pad metal of the
package provides both electrical contact to ground and
good thermal contact to the printed circuit board.
SHDN (Pin 5): Shutdown Pin. When the input voltage is
less than 0.3V, the internal circuits supplied through pins
6, 8, 14, 18 and 19 are enabled. When the input voltage
is greater than 3V, all circuits are disabled. Typical input
current is less than 10A. This pin must not be allowed
to fl oat.
VCC2 (Pin 6) and VCC1 (Pin 8): Power Supply Pins for
the LO Buffer and Bias Circuits. These pins are internally
connected and must be externally connected to a regulated
3.3V supply, with bypass capacitors located close to the
pin. Typical current consumption is 99mA.
LOBIAS (Pin 7): This Pin Allows Adjustment of the LO
Buffer Current. Typical DC voltage is 2.2V.
LOSEL (Pin 9): LO1/LO2 Select Pin. When the input voltage
is less than 0.3V, the LO1 port is selected. When the input
voltage is greater than 3V, the LO2 port is selected. Typical
input current is 11A for LOSEL = 3.3V. This pin must not
be allowed to fl oat.
LO1 (Pin 11) and LO2 (Pin 15): Single-Ended Inputs for
the Local Oscillators. These pins are internally biased
at 0V and require external DC blocking capacitors. Both
inputs are internally matched to 50, even when the chip
is disabled (SHDN = high).
VCC3 (Pin 14): Power Supply Pin for the LO Switch. This
pin must be connected to a regulated 3.3V supply and
bypassed to ground with a capacitor near the pin. Typical
DC current consumption is less than 100A.
IFGND (Pin 16): DC Ground Return for the IF Amplifi er.
This pin must be connected to ground to complete the
IF amplifi er’s DC current path. Typical DC current is
100mA.
IF– (Pin 18) and IF+ (Pin 19): Open-Collector Differential
Outputs for the IF Amplifi er. These pins must be connected
to a DC supply through impedance matching inductors, or
a transformer center-tap. Typical DC current consumption
is 50mA into each pin.
IFBIAS (Pin 20): This Pin Allows Adjustment of the IF
Amplifi er Current. Typical DC voltage is 2.1V.
LTC5542
9
5542f
BLOCK DIAGRAM
RF
CT
SHDN
PASSIVE
MIXER
VCC2 VCC1
VCC3
GND PINS ARE
NOT SHOWN
LO1
LOSEL
LOBIAS
LO2
IF+
IFBIAS IF–IFGND EXPOSED
PAD
5542 BD
IF
AMP
16
15
14
9
11
181920
6
5
2
3
87
21
LO
AMP
BIAS
TEST CIRCUIT
RF
GND
GND
BIAS
DC1431A
BOARD
STACK-UP
(NELCO N4000-13)
0.015”
0.015”
0.062”
4:1
T1
IFOUT
190MHz
50
C10
L2L1
C8C9
LTC5542
1
7
1617181920
LO2IN
50
LO1IN
50
C7
14
15
13
12
11
C4
C3
C6C5
106 8 9
LOSEL
(0V/3.3V)
5
VCC
3.1V TO 3.5V
99mA
SHDN
(0V/3.3V)
4
3
RFIN
50
VCCIF
3.1V TO 5.3V
100mA
C1
2
IFBIAS IF+IF–GND
GND
GND
GND
LO2
LO1
VCC3
VCC2 VCC1
LOBIAS LOSEL
IFGND
NC
RF
CT
GND
SHDN
5541 TC
C11
REF DES VALUE SIZE COMMENTS
C1, C6, C7, C8 22pF 0402 AVX
C3, C4 4.7pF 0402 AVX
C5, C9 1µF 0603 AVX
C10 1000pF 0402 AVX
C11 0.7pF 0402 AVX
L1, L2 150nH 0603 Coilcraft 0603CS
T1
(Alternate)
TC4-1W-7ALN+
(WBC4-6TLB)
Mini-Circuits
(Coilcraft)
L1, L2 vs IF
Frequencies
IF (MHz) L1, L2 (nH)
140 270
190 150
240 100
300 56
380 33
Figure 1. Standard Downmixer Test Circuit Schematic (190MHz IF)
LTC5542
10
5542f
Introduction
The LTC5542 consists of a high linearity passive double-
balanced mixer core, IF buffer amplifi er, high speed single-
pole double-throw (SPDT) LO switch, LO buffer amplifi er
and bias/shutdown circuits. See Block Diagram section for
a description of each pin function. The RF and LO inputs
are single-ended. The IF output is differential. Low-side or
high-side LO injection can be used. The evaluation circuit,
shown in Figure 1, utilizes bandpass IF output matching and
an IF transformer to realize a 50 single-ended IF output.
The evaluation board layout is shown in Figure 2.
APPLICATIONS INFORMATION
Figure 2. Evaluation Board Layout
RF Input
The mixer’s RF input, shown in Figure 3, is connected to
the primary winding of an integrated transformer. A 50
match is realized when a series capacitor C1 and shunt
capacitor C11, are connected to the RF input. C1 is also
needed for DC blocking if the RF source has DC voltage
present, since the primary side of the RF transformer is
DC-grounded internally. The DC resistance of the primary
is approximately 3.6.
The secondary winding of the RF transformer is internally
connected to the passive mixer. The center-tap of the
transformer secondary is connected to pin 3 (CT) to allow
the connection of bypass capacitor, C2. The value of C2
5542 F02
5541 F02
is LO frequency-dependent and is not required for most
applications. When used, C2 should be located within
2mm of pin 3 for proper high-frequency decoupling. The
nominal DC voltage on the CT pin is 1.2V.
For the RF input to be matched, the selected LO input must
be driven. The measured RF input return loss is shown
in Figure 4 for LO frequencies of 1.7GHz, 2.1GHz and
2.5GHz. These LO frequencies correspond to the lower,
middle and upper values of the LO range. As shown in
Figure 4, the RF input impedance is somewhat dependent
on LO frequency.
LTC5542
C1
C2
RFIN
CT
RF
TO MIXER
2
3
5542 F03
C11
Figure 3. RF Input Schematic
Figure 4. RF Input Return Loss
FREQUENCY (GHz)
1.2
–30
RETURN LOSS (dB)
–5
–10
–15
–20
–25
0
3.21.7 2.2
5542 F04
2.7
LO = 2.5GHz C1 = 22pF
C11 = 0.7pF
LO = 2.1GHz
LO = 1.75GHz
LTC5542
11
5542f
APPLICATIONS INFORMATION
The RF input impedance and input refl ection coeffi cient,
versus RF frequency, is listed in Table 1. The reference
plane for this data is pin 2 of the IC, with no external
matching, and the LO is driven at 2.1GHz.
Table 1. RF Input Impedance and S11
(at Pin 2, No External Matching, LO Input Driven at 2.1GHz)
FREQUENCY
(GHz)
INPUT
IMPEDANCE
S11
MAG ANGLE
1.2 23.3 + j32.1 0.53 106.4
1.4 30.7 + j33.6 0.45 97.2
1.6 38.4 + j30.0 0.35 92.4
1.8 41.8 + j23.6 0.27 94.7
2.0 42.5 + j14.5 0.18 107.8
2.2 26.2 + j12.8 0.35 142.1
2.4 27.7 + j20.2 0.38 123.1
2.6 28.4 + j22.5 0.39 117.6
2.8 29.6 + j25.2 0.39 111.4
3.0 32.9 + j25.9 0.36 106.3
3.2 34.2 + j23.6 0.33 108.2
LO2IN
LO1IN
VCC2 VCC1
VCC3
LO BUFFER
TO
MIXER
LTC5542
LO1
LOSELLOBIAS
LO2
5542 F05
15
11
9
8
6
BIAS
7
C4
C3
4mA
14
LO Inputs
The mixer’s LO input circuit, shown in Figure 5, consists
of an integrated SPDT switch, a balun transformer, and
a two-stage high-speed limiting differential amplifi er to
drive the mixer core. The LTC5542’s LO amplifi ers are
optimized for the 1.7GHz to 2.5GHz LO frequency range.
LO frequencies above or below this frequency range may
be used with degraded performance.
Figure 5. LO Input Schematic
The LO switch is designed for high isolation and fast
(<50ns) switching. This allows the use of two active
synthesizers in frequency-hopping applications. If only
one synthesizer is used, then the unused LO input may
be grounded. The LO switch is powered by VCC3 (Pin 14)
and controlled by the LOSEL logic input (Pin 9). The LO1
and LO2 inputs are always 50-matched when VCC is
applied to the chip, even when the chip is shutdown. The
DC resistance of the selected LO input is approximately
23 and the unselected input is approximately 50. A
logic table for the LO switch is shown in Table 2. Measured
LO input return loss is shown in Figure 6.
Table 2. LO Switch Logic Table
LOSEL ACTIVE LO INPUT
Low LO1
High LO2
The LO amplifi ers are powered by VCC1 and VCC2 (pin 8
and pin 6). When the chip is enabled (SHDN = low), the
internal bias circuit provides a regulated 4mA current to the
amplifi er’s bias input, which in turn causes the amplifi ers
to draw approximately 88mA of DC current. This 4mA
reference current is also connected to LOBIAS (Pin 7)
to allow modifi cation of the amplifi er’s DC bias current
for special applications. The recommended application
circuits require no LO amplifi er bias modifi cation, so this
pin should be left open-circuited.
Figure 6. LO Input Return loss
FREQUENCY (GHz)
1.1
–30
RETURN LOSS (dB)
–5
0
–10
–15
–20
–25
5
3.11.3 1.5 1.91.7
5542 F06
2.1 2.3 2.5 2.7 2.9
SELECTED
C3 = C4 = 4.7pF
NOT SELECTED
OR SHUTDOWN
LTC5542
12
5542f
APPLICATIONS INFORMATION
The nominal LO input level is 0dBm although the limiting
amplifi ers will deliver excellent performance over a ±6dB
input power range. LO input power greater than 6dBm
may cause conduction of the internal ESD diodes. Series
capacitors C3 and C4 optimize the input match and provide
DC blocking.
The LO1 input impedance and input refl ection coeffi cient,
versus frequency, is shown in Table 3. The LO2 port
is identical due to the symmetric device layout and
packaging.
Table 3. LO1 Input Impedance vs Frequency
(at Pin 11, No External Matching, LOSEL = Low)
FREQUENCY
(GHz)
INPUT
IMPEDANCE
S11
MAG ANGLE
1.0 53.3 – j15.4 0.15 –69.3
1.2 36.3 – j9.7 0.19 –138.2
1.4 29.9 – j1.6 0.25 –174.4
1.6 29.0 + j5.7 0.27 +160.3
1.8 30.5 + j10.5 0.27 +144.1
2.0 32.3 + j13.4 0.27 +133.4
2.2 33.6 + j15.7 0.27 +125.3
2.4 34.7 + j17.8 0.27 +118.7
2.6 35.7 + j19.7 0.28 +112.8
2.8 36.4 + j21.4 0.29 +108.6
3.0 36.7 + j22.9 0.30 +105.3
IF Output
The IF amplifi er, shown in Figure 7, has differential open-
collector outputs (IF+ and IF–), a DC ground return pin
(IFGND), and a pin for modifying the internal bias (IFBIAS).
The IF outputs must be biased at the supply voltage (VCCIF),
which is applied through matching inductors L1 and L2.
Alternatively, the IF outputs can be biased through the
center tap of a transformer. Each IF output pin draws
approximately 50mA of DC supply current (100mA total).
IFGND (pin 16) must be grounded or the amplifi er will not
draw DC current. Grounding through inductor L3 may
improve LO-IF and RF-IF leakage performance in some
applications, but is otherwise not necessary. High DC
resistance in L3 will reduce the IF amplifi er supply current,
which will degrade RF performance.
For optimum single-ended performance, the differential
IF outputs must be combined through an external IF
4:1
T1 IFOUT
VCC
C10
L2L1
C8 L3 (OR SHORT)
VCCIF
16181920
IF
AMP
BIAS
100mA
4mA
IFGND
LTC5542
IFBIAS IF–
IF+
R1
(OPTION TO
REDUCE
DC POWER)
5542 F07
Figure 7. IF Amplifi er Schematic with Bandpass Match
transformer or discrete IF balun circuit. The evaluation
board (see Figures 1 and 2) uses a 4:1 ratio IF transformer
for impedance transformation and differential to single-
ended transformation. It is also possible to eliminate the
IF transformer and drive differential fi lters or amplifi ers
directly.
The IF output impedance can be modeled as 300 in
parallel with 2.1pF at IF frequencies. An equivalent small-
signal model (including bondwire inductance) is shown in
Figure 8. Frequency-dependent differential IF output
impedance is listed in Table 4. This data is referenced
to the package pins (with no external components) and
includes the effects of IC and package parasitics.
19 18
IF+IF–
0.9nH0.9nH
RIF
CIF
LTC5542
5542 F08
Figure 8. IF Output Small-Signal Model
LTC5542
13
5542f
APPLICATIONS INFORMATION
Bandpass IF Matching
The IF output can be matched for IF frequencies as low
as 90MHz or as high as 500MHz using the bandpass
IF matching shown in Figure 1 and Figure 7. L1 and L2
resonate with the internal IF output capacitance at the
desired IF frequency. The value of L1, L2 is calculated
as follows:
L1, L2 = 1/[(2 π fIF)2 • 2 • CIF]
where CIF is the internal IF capacitance (listed in Table 4).
Values of L1 and L2 are tabulated in Figure 1 for various IF
frequencies. For IF frequencies below 90MHz, the values
of L1, L2 become unreasonably high and the lowpass
topology shown in Figure 9 is preferred. Measured IF
output return loss for bandpass IF matching is plotted
in Figure 10.
Table 4. IF Output Impedance vs Frequency
FREQUENCY (MHz)
DIFFERENTIAL OUTPUT
IMPEDANCE (RIF || XIF (CIF))
90 320 || –j842 (2.1pF)
140 312 || –j541 (2.1pF)
190 300 || –j419 (2.0pF)
240 294 || –j301 (2.2pF)
300 287 || –j221 (2.4pF)
380 280 || –j161 (2.6pF)
500 269 || –j120 (2.65pF)
Lowpass IF Matching
An alternative IF matching network shown in Figure 9 uses
a lowpass topology, which provides excellent RF to IF
and LO to IF isolation. VCCIF is supplied through the center
tap of the 4:1 transformer. A 250 to 200 lowpass
impedance transformation is realized by shunt elements
R2 and C13 (in parallel with the internal RIF and CIF),
and series inductors L1 and L2. Resistor R2 is selected
to reduce the IF output resistance to 250, or it can be
deleted for the highest conversion gain. The fi nal impedance
transformation to 50 is realized by transformer T1. The
matching element values shown in Figure 9 are optimized
for a wideband 30MHz to 150MHz IF match.The demo
board (see Figure 2) has been laid out to accommodate
this matching topology with very few modifi cations.
IF Amplifi er Bias
The IF amplifi er delivers excellent performance with
VCCIF = 3.3V, which allows the VCC and VCCIF supplies
to be common. With VCCIF increased to 5V, the RF input
P1dB increases by more than 3dB, at the expense of higher
power consumption. Mixer performance at 2400MHz is
shown in Table 5 with VCCIF = 3.3V and 5V. For the highest
conversion gain, high-Q wire-wound chip inductors are
recommended for L1 and L2, especially when using
VCCIF = 3.3V. Low-cost multilayer chip inductors may be
substituted, with a slight reduction in conversion gain.
4:1
T1 IFOUT
50
VCCIF
3.1-5.3V
C8
22pF
1819 IF–
IF+
C9
1µF
C13
1.5pF
R2
1k
L1
82nH
L2
82nH
LTC5542
5542 F09
Figure 9. IF Output with Lowpass Matching
FREQUENCY (MHz)
50
–25
RETURN LOSS (dB)
–10
–5
–15
–20
0
100 400 450 500 550150 200 250 300
5542 F10
350
270nH
150nH
100nH 33nH
Figure 10. IF Output Return Loss - Bandpass Matching
LTC5542
14
5542f
APPLICATIONS INFORMATION
Table 5. Performance Comparison with VCCIF = 3.3V and 5V
(RF = 2400MHz, Low-Side LO, IF = 190MHz)
VCCIF
ICCIF
(mA)
GC
(dB)
P1dB
(dBm)
IIP3
(dBm)
NF
(dB)
3.3V 100 8.0 11.3 26.8 9.9
5V 103 7.9 14.7 27.3 10.0
The IFBIAS pin (pin 20) is available for reducing the DC
current consumption of the IF amplifi er, at the expense of
IIP3. This pin should be left open-circuited for optimum
performance. The internal bias circuit produces a 4mA
reference for the IF amplifi er, which causes the amplifi er
to draw approximately 100mA. If resistor R1 is connected
to pin 20 as shown in Figure 7, a portion of the reference
current can be shunted to ground, resulting in reduced
IF amplifi er current. For example, R1 = 1k will shunt
away 1.5mA from pin 20 and the IF amplifi er current will
be reduced by 38% to approximately 62mA. The nominal,
open-circuit DC voltage at pin 20 is 2.1V. Table 6 lists RF
performance versus IF amplifi er current.
Table 6. Mixer Performance with Reduced IF Amplifi er Current
(RF = 2400MHz, Low-Side LO, IF = 190MHz, VCC = VCCIF = 3.3V)
R1
(kΩ)
ICCIF
(mA)
GC
(dB)
IIP3
(dBm)
P1dB
(dBm)
NF
(dB)
OPEN 100 8.0 26.8 11.3 9.9
4.7 90 7.7 26.3 11.4 9.9
2.2 81 7.4 25.4 11.6 9.9
1 62 6.9 23.4 11.6 10.0
(RF = 1950MHz, High-Side LO, IF = 190MHz, VCC = VCCIF = 3.3V)
R1
(kΩ)
ICCIF
(mA)
GC
(dB)
IIP3
(dBm)
P1dB
(dBm)
NF
(dB)
OPEN 100 8.5 25.2 11.0 9.4
4.7 90 8.3 24.9 11.1 9.3
2.2 81 8.0 24.3 11.3 9.3
1 62 7.6 22.8 11.3 9.4
LTC5542
5
SHDN 500
VCC2
5542 F11
6
Figure 11. Shutdown Input Circuit
Shutdown Interface
Figure 11 shows a simplifi ed schematic of the SHDN pin
interface. To disable the chip, the SHDN voltage must be
higher than 3.0V. If the shutdown function is not required,
the SHDN pin should be connected directly to GND. The
voltage at the SHDN pin should never exceed the power
supply voltage (VCC) by more than 0.3V. If this should
occur, the supply current could be sourced through the
ESD diode, potentially damaging the IC.
The SHDN pin must be pulled high or low. If left fl oating,
then the on/off state of the IC will be indeterminate. If a
three-state condition can exist at the SHDN pin, then a
pull-up or pull-down resistor must be used.
Supply Voltage Ramping
Fast ramping of the supply voltage can cause a current
glitch in the internal ESD protection circuits. Depending on
the supply inductance, this could result in a supply voltage
transient that exceeds the maximum rating. A supply voltage
ramp time of greater than 1ms is recommended.
LTC5542
15
5542f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
5.00 p 0.10
5.00 p 0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
2019
1
2
BOTTOM VIEW—EXPOSED PAD
2.60 REF 2.70 p 0.10
0.75 p 0.05 R = 0.125
TYP
R = 0.05
TYP
0.25 p 0.05
0.65 BSC
0.200 REF
0.00 – 0.05
(UH20) QFN 0208 REV Ø
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 p0.05
0.25 p0.05
0.65 BSC
2.60 REF 2.70 p 0.05
4.10 p 0.05
5.50 p 0.05
PACKAGE
OUTLINE
PIN 1 NOTCH
R = 0.30 TYP
OR 0.35 s 45o
CHAMFER
2.70 p 0.10
2.70 p 0.05
UH Package
20-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1818 Rev Ø)
LTC5542
16
5542f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010
LT 0310 • PRINTED IN USA
RELATED PARTS
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LT5557 400MHz to 3.8GHz, 3.3V Downconverting Mixer 2.9dB Gain, 24.7dBm IIP3 and 11.7dB NF at 1950MHz, 3.3V/82mA Supply
LTC6400-X 300MHz Low Distortion IF Amp/ADC Driver Fixed Gain of 8dB, 14dB, 20dB and 26dB; >36dBm OIP3 at 300MHz, Differential I/O
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LTC6416 2GHz 16-Bit ADC Buffer 40.25dBm OIP3 to 300MHz, Programmable Fast Recovery Output Clamping
LTC6412 31dB Linear Analog VGA 35dBm OIP3 at 240MHz, Continuous Gain Range –14dB to 17dB
LT5554 Ultralow Distort IF Digital VGA 48dBm OIP3 at 200MHz, 2dB to 18dB Gain Range, 0.125dB Gain Steps
LT5575 700MHz to 2.7GHz Direct Conversion I/Q
Demodulator
Integrated Baluns, 28dBm IIP3, 13dBm P1dB, 0.03dB I/Q Amplitude Match,
0.4° Phase Match
LT5578 400MHz to 2.7GHz Upconverting Mixer 27dBm OIP3 at 900MHz, 24.2dBm at 1.95GHz, Integrated RF Transformer
LT5579 1.5GHz to 3.8GHz Upconverting Mixer 27.3dBm OIP3 at 2.14GHz, NF = 9.9dB, 3.3V Supply, Single-Ended LO and RF Ports
LTC5598 5MHz to 1.6GHz I/Q Modulator 27.7dBm OIP3 at 140MHz, 22.9dBm at 900MHz, –161.2dBm/Hz Noise Floor
RF Power Detectors
LT5534 50MHz to 3GHz Log RF Power Detector with
60dB Dynamic Range
±1dB Output Variation over Temperature, 38ns Response Time, Log Linear
Response
LT5537 Wide Dynamic Range Log RF/IF Detector Low Frequency to 1GHz, 83dB Log Linear Dynamic Range
LT5570 2.7GHz Mean-Squared Detector ±0.5dB Accuracy Over Temperature and >50dB Dynamic Range, 500ns Rise Time
LT5581 6GHz Low Power RMS Detector 40dB Dynamic Range, ±1dB Accuracy Over Temperature, 1.5mA Supply Current
ADCs
LTC2208 16-Bit, 130Msps ADC 78dBFS Noise Floor, >83dB SFDR at 250MHz
LTC2262-14 14-Bit, 150Msps ADC Ultralow Power 72.8dB SNR, 88dB SFDR, 149mW Power Consumption
LTC2242-12 12-Bit, 250Msps ADC 65.4dB SNR, 78dB SFDR, 740mW Power Consumption
TYPICAL APPLICATION
IF
RF
BIAS
22pF
0.7pF
RF
SHDN
22pF
SHDN
(0V/3.3V)
LTC5542
VCC2
VCC 3.3V
VCC1 VCC3 LOSEL
4.7pF
LO1
LO
LO2
IF+IF–
5542 TA02
1µF
LO
VCCIF
3.3V 22pF
1.5pF
1k
82nH 82nH
4:1
1µF
IFOUT
30MHz to 150MHz
IF OUTPUT FREQUENCY (MHz)
30
7
GC (dB), IIP3 (dBm)
25
23
21
19
17
15
13
11
9
27
–25
IF RETURN LOSS (dB)
–5
–10
–15
–20
0
40 120130140 15050 60 70
5542 TA03
80 90 100110
RF = 1950 ±60MHz
LO = 2040MHz
PLO = 0dBm
VCC = VCCIF = 3.3V
TA = 25°C
IIP3
GC
IF RETURN LOSS
Wideband Conversion Gain, IIP3 and
IF Output Return Loss vs Output Frequency
Wideband, Low-Frequency IF using Lowpass IF Matching