Description
The HCPL-7560 Optically Isolated Modulator and HCPL-
0872 Digital Interface IC or digital lter together form
an isolated programmable two-chip analog-to-digital
converter. The isolated modulator allows direct mea-
surement of motor phase currents in power inverters.
In operation, the HCPL-7560 Isolated Modulator (op-
tocoupler with 3750 VRMS dielectric withstand voltage
rating) converts a low-bandwidth analog input into a
high-speed one-bit data stream by means of a Sigma-
Delta (Σ-∆) over-sampling modulator. This modulation
provides for high noise margins and excellent immunity
against isolation-mode transients. The modulator data
and on-chip sampling clock are encoded and transmit-
ted across the isolation boundary where they are recov-
ered and decoded into separate high-speed clock and
data channels.
Features
• 8-bit Linearity
• 200 ns Conversion Time
(Pre-Trigger Mode 2 with HCPL-0872)
• 8-bit Eective Resolution with 5µs Signal Delay
(14-bit with 102 µs) (with HCPL-0872)
• Fast 3 µs Over-Range Detection (with HCPL-0872)
• ± 200 mV Input Range with Single 5 V Supply
• 5% Internal Reference Voltage Matching
• Oset Calibration (with HCPL-0872)
• -40°C to +85°C Operating Temperature Range
• 15 kV/µs Isolation Transient Immunity
• Safety Approval: UL 1577, CSA and
IEC/EN/DIN EN 60747-5-2
Applications
• Motor Phase and Rail Current Sensing
• Data Acquisition Systems
• Industrial Process Control
• Inverter Current Sensing
• General Purpose Current Sensing and Monitoring
HCPL-7560
Optically Isolated Sigma-Delta (Σ-∆) Modulator
Data Sheet
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation, which may be induced by ESD.
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
NOTE: A 0.1 μF bypass capacitor must be connected between pins VDD1 and GND1 and between pins VDD2 and GND2.
SIGMA-
DELTA
MOD./
ENCODE
DECODE
1
2
3
4
8
7
6
5
Input
Current
HCPL-0872
or
Digital Filter
MCU
or
DSP
HCPL-7560
--
-
2
Pin Description
1
2
3
4
8
7
6
5
V
DD1
V
IN+
V
IN-
GND1
V
DD2
MCLK
MDAT
GND2
SHIELD
ISOLATION
BOUNDARY
DECODE
SIGMA-
DELTA
MOD./
ENCODE
HCPL-7560
Symbol Description
VDD1 Supply voltage input (4.5 V to 5.5 V)
VIN+ Positive input ( ± 200mV recommended)
VIN- Negative input (normally connected to GND1)
GND1 Input ground
VDD2 Supply voltage input (4.5 V to 5.5 V)
MCLK Clock output (10 MHz typical)
MDAT Serial data output
GND2 Output ground
Ordering Information
HCPL-7560 is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Part number
Option
Package
Surface
Mount
Gull
Wing
Tape
& Reel
IEC/EN/DIN EN
60747-5-2 Quantity
RoHS
Compliant
Non-RoHS
Compliant
HCPL-7560 -000E No option 300 mil DIP-8 50 per tube
-300E -300 X X 50 per tube
-500E -500 X X X 1000 per reel
-060E -060 X 50 per tube
-360E -360 X X X 50 per tube
-560E -560 X X X X 1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-7560-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/
DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-7560 to order product of 300 mil DIP-8 package in tube packaging and non-RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
3
Package Outline Drawings
8-pin DIP Package
8-pin Gull Wing Surface Mount Option 300
0.635 ± 0.25
(0.025 ± 0.010) 12
˚
NOM.
9.65 ± 0.25
(0.380 ± 0.010)
0.51 ± 0.130
(0.020 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.80 ± 0.25
(0.386 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
1.02 (0.040)
1.27 (0.050)
10.9 (0.430)
2.0 (0.080)
LAND PATTERN RECOMMENDATION
1.080 ± 0.320
(0.043 ± 0.013)
3.56 ± 0.13
(0.140 ± 0.005)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.540
(0.100)
BSC
0.255 (0.075)
0.010 (0.003)
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED):
xx.xx = 0.01
xx.xxx = 0.005
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
MOLDED
9.80 ± 0.25
(0.386 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A 7560 Z
YYWW
DATE CODE
1.080 ± 0.320
(0.043 ± 0.013)
2.54 ± 0.25
(0.100 ± 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
5678
4321
5˚ TYP.
0.20 (0.008)
0.33 (0.013)
7.62 ± 0.25
(0.300 ± 0.010)
6.35 ± 0.25
(0.250 ± 0.010)
DIMENSIONS IN MILLIMETERS AND (INCHES).
NOTE: FLOATING LEAD PROTUSION IS 0.5 mm (20 mils) MAX.
NOTE: INITIAL OR CONTINUED VARIATION IN THE COLOR OF THE HCPL-7560’S WHITE MOLD COMPOUND IS NORMAL AND DOES NOT
AFFECT DEVICE PERFORMANCE OR RELIABILITY.
3.56 ± 0.13
(0.140 ± 0.005)
OPTION CODE
* MARKING CODE LETTER FOR OPTION NUMBERS
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
4
Solder Reow Temperature Prole
Recommended Pb-Free IR Prole
0
TIME (SECONDS)
TEMPERATURE (˚C)
200
100
50 150100 200 250
300
0
30
SEC.
50 SEC.
30
SEC.
160˚C
140˚C
150˚C
PEAK
TEMP.
245˚C
PEAK
TEMP.
240˚C
PEAK
TEMP.
230˚C
SOLDERING
TIME
200˚C
PREHEATING TIME
150˚C, 90 + 30 SEC.
2.5˚C ± 0.5˚C/SEC.
3˚C + 1˚C/-0.5˚C
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
PREHEATING RATE 3˚C + 1˚C/-0.5˚C/SEC.
REFLOW HEATING RATE 2.5˚C ± 0.5˚C/SEC.
217˚C
RAMP-DOWN
6˚C/SEC. MAX.
RAMP-UP
3˚C/SEC. MAX.
150 - 200 ˚C
260 +0/-5˚C
t 25˚C to PEAK
60 to 150 SEC.
20-40 SEC.
TIME WITHIN 5˚C of ACTUAL
PEAK TEMPERATURE
tp
ts
PREHEAT
60 to 180 SEC.
tL
TL
Tsmax
Tsmin
25
Tp
TIME (SECONDS)
TEMPERATURE (˚C)
NOTES:
THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200˚C, Tsmin = 150˚C
Note: Use of non-chlorine-activated uxes is highly recommended.
Note: Use of non-chlorine-activated uxes is highly recommended.
5
Regulatory Information
The HCPL-7560 has been approved by the following organizations:
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01.
UL
Approval under UL 1577, component recognition program up to VISO = 3750 VRMS. File E55361.
CSA
Approval under CSA Component Acceptance Notice #5, File CA 88324.
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics[1]
Notes:
1. Insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the
application. Surface Mount Classications is Class A in accordance with CECC00802.
2. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/
EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test proles.
3. Refer to the following gure for dependence of PS and IS on ambient temperature.
Description Symbol HCPL-7560 Unit
Installation classication per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 Vrms
for rated mains voltage ≤ 600 Vrms
I - IV
I - III
I - II
Climatic Classication 40/85/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 891 Vpeak
Input to Output Test Voltage, Method b[2]
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec,
Partial discharge < 5 pC
VPR 1670 Vpeak
Input to Output Test Voltage, Method a[2]
VIORM x 1.5=VPR, Type and Sample Test, tm=60 sec,
Partial discharge < 5 pC
VPR 1336 Vpeak
Highest Allowable Overvoltage
(Transient Overvoltage tini = 10 sec)
VIOTM 6000 Vpeak
Safety-limiting values - maximum values allowed in the event of a failure,
also see Figure 13.
Case Temperature
Input Current[3]
Output Power[3]
TS
IS, INPUT
PS, OUTPUT
175
400
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V RS>109W
6
Insulation and Safety Related Specications
Parameter Symbol HCPL-7560 Units Conditions
Minimum External Air Gap
(Clearance)
L(101) 7.4 mm Measured from input terminals to output
terminals, shortest distance through air.
Minimum External
Tracking (Creepage)
L(102) 8.0 mm Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.5 mm Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
Tracking Resistance
(Comparative Tracking Index)
CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classication is Class A in accordance with CECC 00802.
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Note
Storage Temperature TS-55 125 °C
Ambient Operating Temperature TA-40 85 °C
Supply Voltages VDD1, VDD2 0 5.5 V
Steady-State Input Voltage VIN+ ,VIN- -2.0 VDD1 + 0.5 V 1
Two Second Transient Input Voltage -6.0
Output Voltages MCLK, MDAT -0.5 VDD2 + 0.5 V
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane 2
Solder Reow Temperature Prole See Maximum Solder Reow Thermal Prole section
Recommended Operating Conditions
Parameter Symbol Min. Max. Units Note
Ambient Operating Temperature TA-40 +85 °C
Supply Voltages VDD1, VDD2 4.5 5.5 V
Input Voltage VIN+, VIN- -200 +200 mV 1
OUTPUT POWER - P
S
, INPUT CURRENT - I
S
0
0
T
A
- CASE TEMPERATURE -
o
C
20050
400
12525 75 100 150
600
800
200
100
300
500
700
175
P
S
(mW)
I
S
(mA)
7
Electrical Specications (DC)
Unless otherwise noted, all specications are at VIN+ = 0 V and VIN- = 0 V, all Typical specications are at TA = 25°C
and VDD1 = VDD2 = 5 V, and all Minimum and Maximum specications apply over the following ranges: TA = -40°C to
+85°C, VDD1 = 4.5 to 5.5 V and VDD2 = 4.5 to 5.5 V.
Electrical Specications (Tested with HCPL-0872 or Sinc3 Filter)
Unless otherwise noted, all specications are at VIN+ = -200 mV to +200 mV and VIN- = 0 V; all Typical
specications are at TA = 25°C and VDD1 = VDD2 = 5 V, and all Minimum and Maximum specications apply
over the following ranges: TA = -40°C to +85°C, VDD1 = 4.5 to 5.5 V and VDD2 = 4.5 to 5.5 V.
Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note
Average Input Bias Current IIN -0.8 µA 1 3
Average Input Resistance RIN 450 k W3
Input DC Common-Mode Rejection
Ratio
CMRRIN 60 dB 4
Output Logic High Voltage VOH 3.9 4.9 V IOUT = -100 µA
Output Logic Low Voltage VOL 0.1 0.6 V IOUT = 1.6 mA
Output Short Circuit Current |IOSC| 30 mA VOUT = VDD2
or GND2
5
Input Supply Current IDD1 10 20 mA VIN+ = -350 mV
to +350 mV
2
Output Supply Current IDD2 10 20 mA 3
Output Clock Frequency fCLK 7.5 10 15 MHz 4
Data Hold Time tHDDAT 15 ns 6
Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note
STATIC CHARACTERISTICS
Resolution 15 bits 7
Integral Nonlinearity INL 64 256 LSB 5 8
0.2 0.8 % 6 8
Dierential Nonlinearity DNL 1 LSB 9
Uncalibrated Input Oset VOS -6 0 6 mV VIN+ = 0 V 7
Oset Drift vs. Temperature dVOS/dTA2 35 µV/°C VIN+ = 0 V 7 10
Oset drift vs. VDD1 dVOS/dVDD1 0.12 mV/V VIN+ = 0 V 7
Internal Reference Voltage VREF 320 mV 8
Absolute Reference Voltage
Tolerance
-5 5 % 8
VREF Drift vs. Temperature dVREF/dTA150 ppm/°C. 8
VREF Drift vs. VDD1 dVREF/dVDD1 0.2 % 8
Full Scale Input Range -VREF +VREF mV 11
Recommended Input Voltage
Range
-200 +200 mV
8
Dynamic Characteristics (Digital Interface IC HCPL-0872 is set to Conversion Mode 5.)
* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your
equipment level safety specication, or Avago Technologies Application Note 1074, “Optocoupler Input-Output Endurance Voltage.”
Package Characteristics
Parameter Symbol Min. Typ. Max. Units Conditions Note
Input-Output Momentary
Withstand Voltage*
VISO 3750 Vrms RH ≤ 50%, t = 1 min;
TA = 25°C
19, 20
Input-Output Resistance RI-O ≥109WVI-O = 500 Vdc 20
Input-Output Capacitance CI-O 1.4 pF f = 1 MHz 20
Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note
Signal-to-Noise Ratio SNR 53 dB VIN+ = 35 Hz,
400 mVpk-pk
(141 mVrms)
sine wave.
9,10
Total Harmonic Distortion THD -51 dB
Signal-to-(Noise + Distortion) SND 50 dB
Eective Number of Bits ENOB 8 bits 11 12
Conversion Time tC2 0.2 0.8 µs Pre-Trigger Mode 2 1,12 13
tC1 5 8 µs Pre-Trigger Mode 1 1,12 13
tC0 10 16 µs Pre-Trigger Mode 0 1,12
Signal Delay tDSIG 5 µs 13 14
Over-Range Detect Time tOVR1 2.0 3.0 4.2 µs VIN+ = 0 to 400mV
step waveform
14 15
Threshold Detect Time
(default conguration)
tTHR1 10 µs 16
Signal Bandwidth BW 90 kHz 15 17
Isolation Transient Immunity CMR 15 20 kV/µs VISO = 1 kV 18
9
Notes:
1. If VIN- (pin 3) is brought above VDD1 - 2 V with respect to GND1 an
internal optical-coupling test mode may be activated. This test
mode is not intended for customer use.
2. Avago Technologies recommends the use of non-chlorinated sol-
der uxes.
3. Because of the switched-capacitor nature of the isolated modula-
tor, time averaged values are shown.
4. CMRRIN is dened as the ratio of the gain for dierential inputs ap-
plied between VIN+ and VIN- to the gain for common-mode inputs
applied to both VIN+ and VIN- with respect to input ground GND1.
5. Short-circuit current is the amount of output current generated
when either output is shorted to VDD2 or GND2. Use under these
conditions is not recommended.
6. Data hold time is amount of time that the data output MDAT will
stay stable following the rising edge of output clock MCLK.
7. Resolution is dened as the total number of output bits. The use-
able accuracy of any A/D converter is a function of its linearity and
signal-to-noise ratio, rather than how many total bits it has.
8. Integral nonlinearity is defined as one-half the peak-to-peak
deviation of the best-t line through the transfer curve for VIN+ =
-200 mV to +200 mV, expressed either as the number of LSBs or as
a percent of measured input range (400 mV).
9. Dierential nonlinearity is dened as the deviation of the actual
dierence from the ideal dierence between midpoints of succes-
sive output codes, expressed in LSBs.
10. Data sheet value is the average magnitude of the dierence in o-
set voltage from TA =25°C to TA= 85°C, expressed in microvolts per
°C. Three standard deviation from typical value is less than 6µV/°C.
11. Beyond the full-scale input range the output is either all zeroes or
all ones.
12. The eective number of bits (or eective resolution) is dened by
the equation ENOB = (SNR-1.76)/6.02 and represents the resolu-
tion of an ideal, quantization-noise limited A/D converter with the
same SNR.
13. Conversion time is dened as the time from when the convert
start signal CS is brought low to when SDAT goes high, indicating
that output data is ready to be clocked out. This can be as small
as a few cycles of the isolated modulator clock and is determined
by the frequency of the isolated modulator clock and the selected
Conversion and Pre-Trigger modes. For determining the true
signal delay characteristics of the A/D converter for closed-loop
phase margin calculations, the signal delay specication should
be used.
14. Signal delay is dened as the eective delay of the input signal
through the Isolated A/D converter. It can be measured by ap-
plying a -200 mV to ± 200 mV step at the input of modulator and
adjusting the relative delay of the convert start signal CS so that
the output of the converter is at mid scale. The signal delay is the
elapsed time from when the step signal is applied at the input
to when output data is ready at the end of the conversion cycle.
The signal delay is the most important specication for determin-
ing the true signal delay characteristics of the A/D converter and
should be used for determining phase margins in closed-loop
applications. The signal delay is determined by the frequency of
the modulator clock and which Conversion Mode is selected, and
is independent of the selected Pre-Trigger Mode and, therefore,
conversion time.
15. The minimum and maximum overrange detection time is deter-
mined by the frequency of the channel 1 isolated modulator clock.
16. The minimum and maximum threshold detection time is deter-
mined by the user-dened conguration of the adjustable thresh-
old detection circuit and the frequency of the channel 1 isolated
modulator clock. See the Applications Information section for fur-
ther detail. The specied times apply for the default conguration.
17. The signal bandwidth is the frequency at which the magnitude
of the output signal has decreased 3 dB below its low-frequency
value. The signal bandwidth is determined by the frequency of the
modulator clock and the selected Conversion Mode.
18. The isolation transient immunity (also known as Common-Mode
Rejection) species the minimum rate-of-rise of an isolation-mode
signal applied across the isolation boundary beyond which the
modulator clock or data signals are corrupted.
19. In accordance with UL1577, for devices with minimum VISO speci-
ed at 3750 Vrms, each isolated modulator (optocoupler) is proof-
tested by applying an insulation test voltage greater than 4500
Vrms for one second (leakage current detection limit II-O< 5µA).
This test is performed before the Method b, 100% production test
for partial discharge shown in IEC/EN/DIN EN 60747-5-2 Insulation
Characteristics Table.
20. This is a two-terminal measurement: pins 1-4 are shorted together
and pins 5-8 are shorted together.
10
Figure 1. IIN vs. VIN. Figure 2. IDD1 vs. VIN.Figure 3. IDD2 vs. VIN.
Figure 4. Clock Frequency vs. Temperature. Figure 5. INL (Bits) vs. Temperature Figure 6. INL (%) vs. Temperature
Figure 7. Oset Change vs. Temperature Figure 8. VREF Change vs. Temperature Figure 9. SNR vs. Temperature
CLOCK FREQUENCY - MHz
TEMPERATURE - oC
9.2
-15
10.0
60
8.6
9.4
9.8
-40 8510 35
8.8
9.0
9.6
VDD1 = 4.5 V
VDD1 = 5.0 V
VDD1 = 5.5 V
INL-LSB
TEMPERATURE -
o
C
4
-15
7
60
2
5
V
DD1
= 4.5 V
6
-40 8510 35
V
DD1
= 5.0 V
V
DD1
= 5.5 V
3
INL-%
TEMPERATURE - ˚C
0.012
-15
0.02
60
0.006
0.014
VDD1 = 4.5 V
0.016
-40 8510 35
VDD1 = 5.0 V
VDD1 = 5.5 V
0.008
0.018
0.01
OFFSET CHANGE - µV
TEMPERATURE - ˚C
-50
-15
150
60
-150
0
VDD1 = 4.5 V
100
-40 8510 35
VDD1 = 5.0 V
VDD1 = 5.5 V
-100
50
VREF CHANGE - %
TEMPERATURE - ˚C
0
-15
0.8
60
-0.4
0.2
V
DD1
= 4.5 V
0.6
-40 8510 35
V
DD1
= 5.0 V
V
DD1
= 5.5 V
-0.2
0.4
IIN - mA
VIN - V
-4
-5
-4
1
0
-9
-2
0
-6 6-2 2
-1
-3
-8
-6
-7
4
SNR
TEMPERATURE - ˚C
64
62
-15
68
60
61
65
VDD1 = 4.5 V
67
-40 8510 35
VDD1 = 5.0 V
VDD1 = 5.5 V
63
66
11
Figure 10. SNR vs. Conversion Mode. Figure 11. Eective Resolution vs. Conversion
Mode.
Figure 12. Conversion Time vs. Conversion Mode.
Figure 13. Signal Delay vs. Conversion Mode. Figure 14. Over-Range and Threshold Detect
Times.
Figure 15. Signal Bandwidth vs. Conversion
Mode.
SNR
CONVERSION MODE #
60
2
80
3
45
70
75
55
50
65
145
CONVERSION TIME - µs
CONVERSION MODE #
100
80
2
200
3
0
140
PRE-TRIGGER
MODE 2
180
1
160
120
60
40
20
PRE-TRIGGER
MODE 0
PRE-TRIGGER
MODE 1
4 5
SIGNAL DELAY - µs
CONVERSION MODE #
40
2
100
3
0
80
1
90
30
20
60
70
50
10
4 5
EFFECTIVE RESOLUTION (# BITS)
CONVERSION MODE #
11
2
14
3
8
12
1
13
10
9
4 5
2 µs/DIV.
VIN+ (200 mV/DIV.)
OVR1 (200 mV/DIV.)
THR1
(2 V/DIV.)
SIGNAL BANDWIDTH - kHz
CONVERSION MODE #
40
2
100
3
0
80
1
90
30
20
60
70
50
10
4 5
12
Applications Information
Digital Current Sensing
As shown in Figure 16, using the Isolated 2-chip A/D
converter to sense current can be as simple as connect-
ing a current-sensing resistor, or shunt, to the input and
reading output data through the 3-wire serial output
interface. By choosing the appropriate shunt resistance,
any range of current can be monitored, from less than 1
A to more than 100 A.
Figure 16. Typical Application Circuit.
RSHUNT
0.02
INPUT
CURRENT
VDD1
ISOLATED
+ 5 V
VIN+
VIN-
GND1
VDD2
MCLK
MDAT
GND2
C1
0.1 µF
+CDAT SCLK
CCLK V DD
CLAT CHAN
MCLK1 SDAT
MDAT1 CS
MCLK2 THR1
MDAT2 OVR1
GND RESET
NON-ISOLATED
+ 5 V
C3
10 µF
+
HCPL-7560
3-WIRE
SERIAL
INTERFACE
C2
0.1 µF
HCPL-0872
Even better performance can be achieved by fully utiliz-
ing the more advanced features of the Isolated A/D con-
verter, such as the pre-trigger circuit, which can reduce
conversion time to less than 1µs, the fast over-range
detector for quickly detecting short circuits, dierent
conversion modes giving various resolution/speed
trade-os, oset calibration mode to eliminate initial
oset from measurements, and an adjustable threshold
detector for detecting non-short circuit overload condi-
tions.
13
Product Description
The HCPL-7560 Isolated Modulator (optocoupler) uses
sigma-delta modulation to convert an analog input
signal into a high-speed (10 MHz) single-bit digital data
stream; the time average of the modulator’s single-bit
data is directly proportional to the input signal. The
isolated modulator’s other main function is to provide
galvanic isolation between the analog input and the
digital output. An internal voltage reference determines
the full-scale analog input range of the modulator (ap-
proximately ± 320 mV); an input range of ± 200 mV is
recommended to achieve optimal performance.
HCPL-7560 can be used together with HCPL-0872,
Digital Interface IC or a digital lter. The primary func-
tions of the HCPL-0872 Digital Interface IC are to derive
a multi-bit output signal by averaging the single-bit
modulator data, as well as to provide a direct micro-
controller interface. The effective resolution of the
multi-bit output signal is a function of the length of
time (measured in modulator clock cycles) over which
the average is taken; averaging over longer periods of
time results in higher resolution. The Digital Interface
IC can be congured for ve conversion modes, which
have dierent combinations of speed and resolution
to achieve the desired level of performance. Other
functions of the HCPL-0872 Digital Interface IC include
a Phase Locked Loop based pre-trigger circuit that
can either give more precise control of the eective
sampling time or reduce conversion time to less than
1µs, a fast over-range detection circuit that rapidly indi-
cates when the magnitude of the input signal is beyond
full-scale, an adjustable threshold detection circuit
that indicates when the magnitude of the input signal
is above a user adjustable threshold level, an oset
calibration circuit, and a second multiplexed input that
allows a second Isolated Modulator to be used with a
single Digital Interface IC.
The digital output format of the Isolated A/D Converter
is 15 bits of unsigned binary data. The input full-scale
range and code assignment is shown in Table 1 below.
Although the output contains 15 bits of data, the eec-
tive resolution is lower and is determined by selected
conversion mode as shown in Table 2 below.
Table 1. Input Full-Scale Range and Code Assignment.
Notes: Bold italic type indicates Default values.
Table 2. Isolated A/D Converter Typical Performance Characteristics.
Conversion
Mode
Signal-to-Noise
Ratio (dB)
Eective
Resolution
(bits)
Conversion Time (µs)
Signal
Delay(µs)
Signal Bandwidth
(kHz)
Pre-Trigger Mode
012
1 83 13.5 205 102
0.2
102 3.4
2 79 12.8 103 51 51 6.9
3 73 11.9 39 19 19 22
4 66 10.7 20 10 10 45
5 53 8.5 10 5 5 90
Analog Input Voltage Input Digital Output
Full Scale Range 640 mV 32768 LSBs
Minimum Step Size 20 µV 1 LSB
+Full Scale +320 mV 111111111111111
Zero 0 mV 100000000000000
-Full Scale -320 mV 000000000000000
14
Power Supplies and Bypassing
The recommended application circuit is shown in
Figure 17. A oating power supply (which in many ap-
plications could be the same supply that is used to
drive the high-side power transistor) is regulated to 5
V using a simple zener diode (D1); the value of resistor
R1 should be chosen to supply sucient current from
the existing oating supply. The voltage from the cur-
rent sensing resistor or shunt (Rsense) is applied to the
input of the HCPL-7560 (U2) through an RC anti-aliasing
lter (R2 and C2). And nally, the output clock and data
of the isolated modulator are connected to the digital
interface IC. Although the application circuit is relatively
simple, a few recommendations should be followed to
ensure optimal performance.
The power supply for the isolated modulator is most
often obtained from the same supply used to power the
power transistor gate drive circuit. If a dedicated supply
is required, in many cases it is possible to add an ad-
ditional winding on an existing transformer. Otherwise,
some sort of simple isolated supply can be used, such
as a line powered transformer or a high-frequency DC-
DC converter.
An inexpensive 78L05 three-terminal regulator can also
be used to reduce the oating supply voltage to 5 V. To
help attenuate high-frequency power supply noise or
ripple, a resistor or inductor can be used in series with
the input of the regulator to form a low-pass lter with
the regulator’s input bypass capacitor.
As shown in Figure 17, 0.1µF bypass capacitors (C1 and
C3) should be located as close as possible to the input
and output power-supply pins of the isolated modula-
tor (U2). The bypass capacitors are required because of
the high-speed digital nature of the signals inside the
isolated modulator. A 0.01µF bypass capacitor (C2) is
also recommended at the input due to the switched-
capacitor nature of the input circuit. The input bypass
capacitor also forms part of the anti-aliasing lter, which
is recommended to prevent high-frequency noise from
aliasing down to lower frequencies and interfering with
the input signal.
Figure 17. Recommended Application Circuit.
+-
MOTOR
HV-
HV+
RSENSE
FLOATING
POSITIVE
SUPPLY
GATE DRIVE
CIRCUIT
VDD1
VIN+
VIN-
GND1
VDD2
MCLK
MDAT
GND2
CDAT SCLK
CCLK VDD
CLAT CHAN
MCLK1 SDAT
MDAT1 CS
MCLK2 THR1
MDAT2 OVR1
GND RESET
+ 5 V
HCPL-7560
TO
CONTROL
CIRCUIT
C3
0.1 µF
C1
0.1 µF
C2
0.01 µF
R2 39Ω
R1
D1
5.1 V
HCPL-0872
15
PC Board Layout
The design of the printed circuit board (PCB) should
follow good layout practices, such as keeping bypass
capacitors close to the supply pins, keeping output
signals away from input signals, the use of ground and
power planes, etc. In addition, the layout of the PCB can
also aect the isolation transient immunity (CMR) of the
isolated modulator, due primarily to stray capacitive
coupling between the input and the output circuits. To
obtain optimal CMR performance, the layout of the PC
board should minimize any stray coupling by maintain-
ing the maximum possible distance between the input
and output sides of the circuit and ensuring that any
ground or power plane on the PC board does not pass
directly below or extend much wider than the body of
the isolated modulator.
Shunt Resistors
The current-sensing shunt resistor should have low
resistance (to minimize power dissipation), low induc-
tance (to minimize di/dt induced voltage spikes which
could adversely aect operation), and reasonable toler-
ance (to maintain overall circuit accuracy). Choosing a
particular value for the shunt is usually a compromise
between minimizing power dissipation and maximiz-
ing accuracy. Smaller shunt resistances decrease power
dissipation, while larger shunt resistances can improve
circuit accuracy by utilizing the full input range of the
isolated modulator. The rst step in selecting a shunt is
determining how much current the shunt will be sens-
ing. The graph in Figure 18 shows the RMS current in
each phase of a three-phase induction motor as a func-
tion of average motor output power (in horsepower, hp)
and motor drive supply voltage. The maximum value of
the shunt is determined by the current being measured
and the maximum recommended input voltage of the
isolated modulator. The maximum shunt resistance can
be calculated by taking the maximum recommended
input voltage and dividing by the peak current that the
shunt should see during normal operation. For example,
if a motor will have a maximum RMS current of 10 A and
can experience up to 50% overloads during normal op-
eration, then the peak current is 21.1 A (= 10 x 1.414 x
1.5). Assuming a maximum input voltage of 200 mV, the
maximum value of shunt resistance in this case would
be about 10 mW.
The maximum average power dissipation in the shunt
can also be easily calculated by multiplying the shunt
resistance times the square of the maximum RMS cur-
rent, which is about 1 W in the previous example.
Figure 18. Motor Output Horsepower vs. Motor Phase Current and Supply
Voltage.
15
5
40
15 20 25 30
25
MOTOR PHASE CURRENT - A (rms)
10
30
MOTOR OUTPUT POWER - HORSEPOWER
5 350
0
440
380
220
120
10
20
35
If the power dissipation in the shunt is too high, the
resistance of the shunt can be decreased below the
maximum value to decrease power dissipation. The
minimum value of the shunt is limited by precision
and accuracy requirements of the design. As the shunt
value is reduced, the output voltage across the shunt
is also reduced, which means that the oset and noise,
which are xed, become a larger percentage of the
signal amplitude. The selected value of the shunt will
fall somewhere between the minimum and maximum
values, depending on the particular requirements of a
specic design.
When sensing currents large enough to cause signi-
cant heating of the shunt, the temperature coecient
(tempco) of the shunt can introduce nonlinearity due to
the signal dependent temperature rise of the shunt. The
eect increases as the shunt-to-ambient thermal resis-
tance increases. This eect can be minimized either by
reducing the thermal resistance of the shunt or by us-
ing a shunt with a lower tempco. Lowering the thermal
resistance can be accomplished by repositioning the
shunt on the PC board, by using larger PC board traces
to carry away more heat, or by using a heat sink.
For a two-terminal shunt, as the value of shunt resis-
tance decreases, the resistance of the leads becomes a
signicant percentage of the total shunt resistance. This
has two primary eects on shunt accuracy. First, the ef-
fective resistance of the shunt can become dependent
on factors such as how long the leads are, how they are
bent, how far they are inserted into the board, and how
far solder wicks up the lead during assembly (these is-
sues will be discussed in more detail shortly). Second,
the leads are typically made from a material such as
copper, which has a much higher tempco than the ma-
terial from which the resistive element itself is made,
resulting in a higher tempco for the shunt overall. Both
of these eects are eliminated when a four-terminal
shunt is used. A four-terminal shunt has two additional
terminals that are Kelvin-connected directly across the
16
Shunt Connections
The recommended method for connecting the isolated
modulator to the shunt resistor is shown in Figure 17.
VIN+ (pin 2 of the HPCL-7560) is connected to the posi-
tive terminal of the shunt resistor, while VIN- (pin 3) is
shorted to GND1 with the power-supply return path
functioning as the sense line to the negative terminal of
the current shunt. This allows a single pair of wires or PC
board traces to connect the isolated modulator circuit
to the shunt resistor. By referencing the input circuit
to the negative side of the sense resistor, any load cur-
rent induced noise transients on the shunt are seen as
a common-mode signal and will not interfere with the
current-sense signal. This is important because the large
load currents owing through the motor drive, along
with the parasitic inductances inherent in the wiring of
the circuit, can generate both noise spikes and osets
that are relatively large compared to the small voltages
that are being measured across the current shunt.
If the same power supply is used both for the gate drive
circuit and for the current sensing circuit, it is very im-
portant that the connection from GND1 of the isolated
modulator to the sense resistor be the only return path
for supply current to the gate drive power supply in
order to eliminate potential ground loop problems. The
only direct connection between the isolated modulator
circuit and the gate drive circuit should be the positive
power supply line.
resistive element itself; these two terminals are used to
monitor the voltage across the resistive element while
the other two terminals are used to carry the load cur-
rent. Because of the Kelvin connection, any voltage
drops across the leads carrying the load current should
have no impact on the measured voltage.
Several four-terminal shunts from Isotek (Isabellen-
hütte) suitable for sensing currents in motor drives up
to 71 Arms (71 hp or 53 kW) are shown in Table 3; the
maximum current and motor power range for each
of the PBV series shunts are indicated. For shunt resis-
tances from 50 mW down to 10 mW, the maximum cur-
rent is limited by the input voltage range of the isolated
modulator. For the 5 mW and 2 mW shunts, a heat sink
may be required due to the increased power dissipation
at higher currents.
When laying out a PC board for the shunts, a couple of
points should be kept in mind. The Kelvin connections
to the shunt should be brought together under the
body of the shunt and then run very close to each other
to the input of the isolated modulator; this minimizes
the loop area of the connection and reduces the pos-
sibility of stray magnetic elds from interfering with the
measured signal. If the shunt is not located on the same
PC board as the isolated modulator circuit, a tightly
twisted pair of wires can accomplish the same thing.
Also, multiple layers of the PC board can be used to
increase current carrying capacity. Numerous plated-
through vias should surround each non-Kelvin terminal
of the shunt to help distribute the current between the
layers of the PC board. The PC board should use 2 or 4
oz. copper for the layers, resulting in a current carrying
capacity in excess of 20 A. Making the current carrying
traces on the PC board fairly large can also improve the
shunt’s power dissipation capability by acting as a heat
sink. Liberal use of vias where the load current enters
and exits the PC board is also recommended.
17
Table 3. Isotek (Isabellenhütte) Four-Terminal Shunt Summary.
In some applications, however, supply currents owing
through the power-supply return path may cause oset
or noise problems. In this case, better performance may
be obtained by connecting VIN+ and VIN- directly across
the shunt resistor with two conductors, and connecting
GND1 to the shunt resistor with a third conductor for
the power-supply return path, as shown in Figure 19.
When connected this way, both input pins should be
bypassed. To minimize electromagnetic interference of
the sense signal, all of the conductors (whether two or
three are used) connecting the isolated modulator to
the sense resistor should be either twisted pair wire or
closely spaced traces on a PC board.
Figure 19. Schematic for Three Conductor Shunt Connection.
Shunt
Resistor Part
Num
Shunt Resistance Tol.
Maximum RMS
Current
Motor Power Range
120 Vac-440 Vac
mW% A hp kW
PBV-R050-0.5 50 0.5 3 0.8 - 3 0.6 - 2
PBV-R020-0.5 20 0.5 7 2 - 7 0.6 - 2
PBV-R010-0.5 10 0.5 14 4 - 14 3 - 10
PBV-R005-0.5 5 0.5 25 [28] 7 - 25 [8 - 28] 5 - 19 [6 - 21]
PBV-R002-0.5 2 0.5 39 [71] 11 - 39 [19 - 71] 8 - 29 [14 - 53]
The 39W resistor in series with the input lead (R2) forms
a lowpass anti-aliasing filter with the 0.01µF input
bypass capacitor (C2) with a 400 kHz bandwidth. The
resistor performs another important function as well;
it dampens any ringing which might be present in the
circuit formed by the shunt, the input bypass capacitor,
and the inductance of wires or traces connecting the
two. Undamped ringing of the input circuit near the
input sampling frequency can alias into the baseband
producing what might appear to be noise at the output
of the device.
+-
MOTOR
HV-
HV+
RSENSE
FLOATING
POSITIVE
SUPPLY
GATE DRIVE
CIRCUIT
VDD1
VIN+
VIN-
GND1
VDD2
MCLK
MDAT
GND2
HCPL-7560
C1
0.1 µF
C2a
0.01 µF
R2a 39Ω
R1
D1
5.1 V
C2b
0.01 µF
R2b 39Ω
Note: Values in brackets are with a heatsink for the shunt.
Voltage Sensing
The HCPL-7560 Isolated Modulator can also be used to
isolate signals with amplitudes larger than its recom-
mended input range with the use of a resistive voltage
divider at its input. The only restrictions are that the
impedance of the divider be relatively small (less than 1
kW) so that the input resistance (280 kW) and input bias
current (1µA) do not aect the accuracy of the mea-
surement. An input bypass capacitor is still required,
although the 39W series damping resistor is not (the
resistance of the voltage divider provides the same
function). The low-pass lter formed by the divider re-
sistance and the input bypass capacitor may limit the
achievable bandwidth. To obtain higher bandwidth,
the input bypass capacitor (C2) can be reduced, but it
should not be reduced much below 1000 pF to maintain
adequate input bypassing of the isolated modulator.
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Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved. Obsoletes 5989-2164EN
AV02-0408EN - June 18, 2007