CD-ROM
DATA BOOK
(DVD)
[ASSP·Memory·ASIC]
MANUAL
DS04-27211-5E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP For Power Supply Applications
BIPOLAR
Switching Regulator Controller
(Supporting External Synchronization)
MB3789
DESCRIPTION
The MB3789 is a PWM (pulse width modulation) switching regulator controller supporting an external sync signal.
The MB3789 incorporates two error amplifiers which can be used respectively for voltage control and current
control, allowing the IC to serve as a DC/DC converter with current regulating functions.
The MB3789 is the ideal IC for supplying power to the back-lighting fluorescent tube for a liquid crystal display
(LCD) device such as a camera-integrated VTR.
FEATURES
• Wide range of operating power supply voltages: 3 V to 18 V
• Low current consumption: 1.5 mA (Typ)
• Wide input voltage range of error amplifier : –0.2 V to VCC – 1.8 V
• Built-in two error amplifier
• Oscillator capable of operating with an external sync signal
• Built-in timer latch short protection circuit
• Variable dead time provides control over total operating range
• Output supporting a power MOSFET
• 16-pin SSOP package mountable at high density
PACK AGE
16-pin Plastic SSOP
(FPT-16P-M05)
DS04-27211-5E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP For Power Supply Applications
BIPOLAR
Switching Regulator Controller
(Supporting External Synchronization)
MB3789
DESCRIPTION
The MB3789 is a PWM (pulse width modulation) switching regulator controller supporting an external sync signal.
The MB3789 incorporates two error amplifiers which can be used respectively for voltage control and current
control, allowing the IC to serve as a DC/DC converter with current regulating functions.
The MB3789 is the ideal IC for supplying power to the back-lighting fluorescent tube for a liquid crystal display
(LCD) device such as a camera-integrated VTR.
FEATURES
• Wide range of operating power supply voltages: 3 V to 18 V
• Low current consumption: 1.5 mA (Typ)
• Wide input voltage range of error amplifier : –0.2 V to VCC – 1.8 V
• Built-in two error amplifier
• Oscillator capable of operating with an external sync signal
• Built-in timer latch short protection circuit
• Variable dead time provides control over total operating range
• Output supporting a power MOSFET
• 16-pin SSOP package mountable at high density
PACK AGE
16-pin Plastic SSOP
(FPT-16P-M05)
DS04-27211-5E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP For Power Supply Applications
BIPOLAR
Switching Regulator Controller
(Supporting External Synchronization)
MB3789
DESCRIPTION
The MB3789 is a PWM (pulse width modulation) switching regulator controller supporting an external sync signal.
The MB3789 incorporates two error amplifiers which can be used respectively for voltage control and current
control, allowing the IC to serve as a DC/DC converter with current regulating functions.
The MB3789 is the ideal IC for supplying power to the back-lighting fluorescent tube for a liquid crystal display
(LCD) device such as a camera-integrated VTR.
FEATURES
• Wide range of operating power supply voltages: 3 V to 18 V
• Low current consumption: 1.5 mA (Typ)
• Wide input voltage range of error amplifier : –0.2 V to VCC – 1.8 V
• Built-in two error amplifier
• Oscillator capable of operating with an external sync signal
• Built-in timer latch short protection circuit
• Variable dead time provides control over total operating range
• Output supporting a power MOSFET
• 16-pin SSOP package mountable at high density
PACK AGE
16-pin Plastic SSOP
(FPT-16P-M05)
DS05-11440-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2006 FUJITSU LIMITED All rights reserved
MEMORY
CMOS
128 M-BIT (4-BANK × 1 M-WORD × 32-BIT)
SINGLE DATA RATE I/F FCRAMTM
Consumer/Embedded Application Specific Memory for SiP
MB81ES123245-10
DESCRIPTION
The Fujitsu MB81ES123245 is a Single Data Rate Interface Fast Cycle Random Access Memory (FCRAM*)
containing 134,217,728 memory cells accessible in a 32-bit format. The MB81ES123245 features a fully synchro-
nous operation referenced to a positive clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence.
The MB81ES123245 is utilized using a Fujitsu advanced FCRAM core technology and designed for low power
consumption and low voltage operation than regular synchronous DRAM (SDRAM) .
The MB81ES123245 is dedicated for SiP (System in a Package) , and ideally suited for various embedded/
consumer applications including digital AVs and image processing where a large band width and low power
consumption memory is needed.
* : FCRAM is a trademark of Fujitsu Limited, Japan.
PRODUCT LINEUP
01-542321SE18BMretemaraP
Clock Frequency (Max) CL=zHM 452
CL=zHM 8013
Burst Mode Cycle Time (Min) CL=sn 5.812
CL=sn 2.93
Access Time from CLK (Max) CL=sn 92
CL=sn 73
Am 53 )htgnel eg
ap 46( )xaM( tnerruC gnitarepO
Power Down Mode Current (Max) (IDD2PS Am 5.0 )
Self-Refresh Current (Max) Tj =+35° 002xaM C μA
DS05-11440-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2006 FUJITSU LIMITED All rights reserved
MEMORY
CMOS
128 M-BIT (4-BANK × 1 M-WORD × 32-BIT)
SINGLE DATA RATE I/F FCRAMTM
Consumer/Embedded Application Specific Memory for SiP
MB81ES123245-10
DESCRIPTION
The Fujitsu MB81ES123245 is a Single Data Rate Interface Fast Cycle Random Access Memory (FCRAM*)
containing 134,217,728 memory cells accessible in a 32-bit format. The MB81ES123245 features a fully synchro-
nous operation referenced to a positive clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence.
The MB81ES123245 is utilized using a Fujitsu advanced FCRAM core technology and designed for low power
consumption and low voltage operation than regular synchronous DRAM (SDRAM) .
The MB81ES123245 is dedicated for SiP (System in a Package) , and ideally suited for various embedded/
consumer applications including digital AVs and image processing where a large band width and low power
consumption memory is needed.
* : FCRAM is a trademark of Fujitsu Limited, Japan.
PRODUCT LINEUP
01-542321SE18BMretemaraP
Clock Frequency (Max) CL=zHM 452
CL=zHM 8013
Burst Mode Cycle Time (Min) CL=sn 5.812
CL=sn 2.93
Access Time from CLK (Max) CL=sn 92
CL=sn 73
Am 53 )htgnel eg
ap 46( )xaM( tnerruC gnitarepO
Power Down Mode Current (Max) (IDD2PS Am 5.0 )
Self-Refresh Current (Max) Tj =+35° 002xaM C μA
DS05-11440-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2006 FUJITSU LIMITED All rights reserved
MEMORY
CMOS
128 M-BIT (4-BANK × 1 M-WORD × 32-BIT)
SINGLE DATA RATE I/F FCRAMTM
Consumer/Embedded Application Specific Memory for SiP
MB81ES123245-10
DESCRIPTION
The Fujitsu MB81ES123245 is a Single Data Rate Interface Fast Cycle Random Access Memory (FCRAM*)
containing 134,217,728 memory cells accessible in a 32-bit format. The MB81ES123245 features a fully synchro-
nous operation referenced to a positive clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence.
The MB81ES123245 is utilized using a Fujitsu advanced FCRAM core technology and designed for low power
consumption and low voltage operation than regular synchronous DRAM (SDRAM) .
The MB81ES123245 is dedicated for SiP (System in a Package) , and ideally suited for various embedded/
consumer applications including digital AVs and image processing where a large band width and low power
consumption memory is needed.
* : FCRAM is a trademark of Fujitsu Limited, Japan.
PRODUCT LINEUP
01-542321SE18BMretemaraP
Clock Frequency (Max) CL=zHM 452
CL=zHM 8013
Burst Mode Cycle Time (Min) CL=sn 5.812
CL=sn 2.93
Access Time from CLK (Max) CL=sn 92
CL=sn 73
Am 53 )htgnel eg
ap 46( )xaM( tnerruC gnitarepO
Power Down Mode Current (Max) (IDD2PS Am 5.0 )
Self-Refresh Current (Max) Tj =+35° 002xaM C μA
DS06-20210-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
Semicustom
CMOS
Standard Cell
CS101 Series
DESCRIPTION
CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies user’s demands for lower power
consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three
types of core transistors with a different threshold voltage can be mixed according to user application.
The design rules match industry standards, and a wide range of IP macros are available for use.
As well as providing a maximum of 100 million gates, approximately twice the level of integration achieved in
previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the high-
speed library increases the speed by a factor of approximately 1.3, with a gate delay time of 12 ps.
FEATURES
• Technology : 90 nm Si gate CMOS
7- to 10-metal layers.
Low-K (low permittivity) material is used for all dielectric inter-layers.
Three different types of core transistors (low leak, standard, and high speed)
can be used on the same chip.
The design rules comply with industry standard processes.
• Power supply voltage : +1.2 V ± 0.1 V (standard)
• Operation junction temperature : − 40 °C to + 125 °C (standard)
• Gate delay time : tpd = 12 ps (1.2 V, Inverter, F/O = 1)
• Gate power consumption : Pd = 2.7 nW/MHz/BC (1.2 V, 2 NAND, F/O = 1)
• High level of integration : Up to 91 million gates
• Reduced chip sized realized by I/O with pad.
• Support for a wide range of cell sets (from low power versions to ultra high speed versions).
• Compliance with industry standard design rules enables non-Fujitsu commercial macros to be easily incor po-
rated.
• Compiled cell (RAM, ROM, others)
• Support for ultra high speed (up to 10 Gbps) interface macros.
• Special interfaces (LVDS, SSTL2, etc.)
• Supports use of industr y standard libraries (.LIB).
• Uses industry standard tools and suppo rts the optimum tools for the application.
(Continued)
DS06-20210-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
Semicustom
CMOS
Standard Cell
CS101 Series
DESCRIPTION
CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies user’s demands for lower power
consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three
types of core transistors with a different threshold voltage can be mixed according to user application.
The design rules match industry standards, and a wide range of IP macros are available for use.
As well as providing a maximum of 100 million gates, approximately twice the level of integration achieved in
previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the high-
speed library increases the speed by a factor of approximately 1.3, with a gate delay time of 12 ps.
FEATURES
• Technology : 90 nm Si gate CMOS
7- to 10-metal layers.
Low-K (low permittivity) material is used for all dielectric inter-layers.
Three different types of core transistors (low leak, standard, and high speed)
can be used on the same chip.
The design rules comply with industry standard processes.
• Power supply voltage : +1.2 V ± 0.1 V (standard)
• Operation junction temperature : − 40 °C to + 125 °C (standard)
• Gate delay time : tpd = 12 ps (1.2 V, Inverter, F/O = 1)
• Gate power consumption : Pd = 2.7 nW/MHz/BC (1.2 V, 2 NAND, F/O = 1)
• High level of integration : Up to 91 million gates
• Reduced chip sized realized by I/O with pad.
• Support for a wide range of cell sets (from low power versions to ultra high speed versions).
• Compliance with industry standard design rules enables non-Fujitsu commercial macros to be easily incor po-
rated.
• Compiled cell (RAM, ROM, others)
• Support for ultra high speed (up to 10 Gbps) interface macros.
• Special interfaces (LVDS, SSTL2, etc.)
• Supports use of industr y standard libraries (.LIB).
• Uses industry standard tools and suppo rts the optimum tools for the application.
(Continued)
DS06-20210-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
Semicustom
CMOS
Standard Cell
CS101 Series
DESCRIPTION
CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies user’s demands for lower power
consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three
types of core transistors with a different threshold voltage can be mixed according to user application.
The design rules match industry standards, and a wide range of IP macros are available for use.
As well as providing a maximum of 100 million gates, approximately twice the level of integration achieved in
previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the high-
speed library increases the speed by a factor of approximately 1.3, with a gate delay time of 12 ps.
FEATURES
• Technology : 90 nm Si gate CMOS
7- to 10-metal layers.
Low-K (low permittivity) material is used for all dielectric inter-layers.
Three different types of core transistors (low leak, standard, and high speed)
can be used on the same chip.
The design rules comply with industry standard processes.
• Power supply voltage : +1.2 V ± 0.1 V (standard)
• Operation junction temperature : − 40 °C to + 125 °C (standard)
• Gate delay time : tpd = 12 ps (1.2 V, Inverter, F/O = 1)
• Gate power consumption : Pd = 2.7 nW/MHz/BC (1.2 V, 2 NAND, F/O = 1)
• High level of integration : Up to 91 million gates
• Reduced chip sized realized by I/O with pad.
• Support for a wide range of cell sets (from low power versions to ultra high speed versions).
• Compliance with industry standard design rules enables non-Fujitsu commercial macros to be easily incor po-
rated.
• Compiled cell (RAM, ROM, others)
• Support for ultra high speed (up to 10 Gbps) interface macros.
• Special interfaces (LVDS, SSTL2, etc.)
• Supports use of industr y standard libraries (.LIB).
• Uses industry standard tools and suppo rts the optimum tools for the application.
(Continued)
DS07-12614-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2006 FUJITSU LIMITED All rights reserved
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95100AM Series
MB95108AM/F104AMS/F104ANS/F104AJS/F106AMS/F106ANS/F106AJS/
MB95F108AMS/F108ANS/F108AJS/F104AMW/F104ANW/F104AJW/F106AMW/
MB95F106ANW/F106AJW/F108AMW/F108ANW/F108AJW/FV100D-103
DESCRIPTION
The MB95100AM series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
FEATURE
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock (for dual clock product)
• Sub PLL clock (for dual clock product)
(Continued)
DS07-12614-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2006 FUJITSU LIMITED All rights reserved
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95100AM Series
MB95108AM/F104AMS/F104ANS/F104AJS/F106AMS/F106ANS/F106AJS/
MB95F108AMS/F108ANS/F108AJS/F104AMW/F104ANW/F104AJW/F106AMW/
MB95F106ANW/F106AJW/F108AMW/F108ANW/F108AJW/FV100D-103
DESCRIPTION
The MB95100AM series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
FEATURE
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock (for dual clock product)
• Sub PLL clock (for dual clock product)
(Continued)
DS07-12614-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2006 FUJITSU LIMITED All rights reserved
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95100AM Series
MB95108AM/F104AMS/F104ANS/F104AJS/F106AMS/F106ANS/F106AJS/
MB95F108AMS/F108ANS/F108AJS/F104AMW/F104ANW/F104AJW/F106AMW/
MB95F106ANW/F106AJW/F108AMW/F108ANW/F108AJW/FV100D-103
DESCRIPTION
The MB95100AM series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
FEATURE
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock (for dual clock product)
• Sub PLL clock (for dual clock product)
(Continued)
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of the information or package dimensions in this document.
FUJITSU SEMICONDUCTOR
DATA SHEET
LOW PROFILE QUAD FLAT PACKAGE
64 PIN PLASTIC
mm 56.0hctip daeLPFQL citsalp nip-46
Package width ×
package length 12× 12 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.70 mm MAX
Code
(Reference) P-LQFP64-12×12-0.65
64-pin plastic LQFP
(FPT-64P-M09)
(FPT-64P-M09)
C
2003 FUJITSU LIMITED F64018S-c-3-5
0.65(.026)
0.10(.004)
611
17
3249
64
3348
12.00±0.10(.472±.004)SQ
14.00±0.20(.551±.008)SQ
INDEX
0.32±0.05
(.013±.002) M
0.13(.005)
0.145±0.055
(.0057±.0022)
"A"
.059–.004
+.008
–0.10
+0.20
1.50
0~8˚
0.25(.010)
(Mounting height)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
0.10(.004)
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
FPT-64P-M09
0212
Note 1)* : These dimensions do not include resin protrusion.
Note 2)Pins width and pins thickness include plating thickness.
Note 3)Pins width do not include tie bar cutting remainder.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of the information or package dimensions in this document.
FUJITSU SEMICONDUCTOR
DATA SHEET
LOW PROFILE QUAD FLAT PACKAGE
64 PIN PLASTIC
mm 56.0hctip daeLPFQL citsalp nip-46
Package width ×
package length 12× 12 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.70 mm MAX
Code
(Reference) P-LQFP64-12×12-0.65
64-pin plastic LQFP
(FPT-64P-M09)
(FPT-64P-M09)
C
2003 FUJITSU LIMITED F64018S-c-3-5
0.65(.026)
0.10(.004)
611
17
3249
64
3348
12.00±0.10(.472±.004)SQ
14.00±0.20(.551±.008)SQ
INDEX
0.32±0.05
(.013±.002) M
0.13(.005)
0.145±0.055
(.0057±.0022)
"A"
.059–.004
+.008
–0.10
+0.20
1.50
0~8˚
0.25(.010)
(Mounting height)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
0.10(.004)
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
FPT-64P-M09
0212
Note 1)* : These dimensions do not include resin protrusion.
Note 2)Pins width and pins thickness include plating thickness.
Note 3)Pins width do not include tie bar cutting remainder.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of the information or package dimensions in this document.
FUJITSU SEMICONDUCTOR
DATA SHEET
LOW PROFILE QUAD FLAT PACKAGE
64 PIN PLASTIC
mm 56.0hctip daeLPFQL citsalp nip-46
Package width ×
package length 12× 12 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.70 mm MAX
Code
(Reference) P-LQFP64-12×12-0.65
64-pin plastic LQFP
(FPT-64P-M09)
(FPT-64P-M09)
C
2003 FUJITSU LIMITED F64018S-c-3-5
0.65(.026)
0.10(.004)
611
17
3249
64
3348
12.00±0.10(.472±.004)SQ
14.00±0.20(.551±.008)SQ
INDEX
0.32±0.05
(.013±.002) M
0.13(.005)
0.145±0.055
(.0057±.0022)
"A"
.059–.004
+.008
–0.10
+0.20
1.50
0~8˚
0.25(.010)
(Mounting height)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
0.10(.004)
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
FPT-64P-M09
0212
Note 1)* : These dimensions do not include resin protrusion.
Note 2)Pins width and pins thickness include plating thickness.
Note 3)Pins width do not include tie bar cutting remainder.