© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice. 1Doc. No. MD-1021, Rev. E
CS
SK
DI
DO
VCC
RDY/BUSY
RESET
GND
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
RDY/BUSY
RESET
GND
1
2
3
4
8
7
6
5
RDY/BUSY
VCC
CS
SK
RESET
GND
DO
DI
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
RDY/BUS
Y
RESET
GND
1
2
3
4
8
7
6
5
RDY/BUSY
VCC
CS
SK
RESET
GND
DO
DI
4K-Bit SPI Serial EEPROM
FEATURES
■SPI bus compatible
■Low power CMOS technology
■2.5V to 6.0V operation
■Self-timed write cycle with auto-clear
■Hardware reset pin
■Hardware and software write protection
■Commercial, industrial and automotive
temperature ranges
■Power-up inadvertant write protection
■RDY/BSYBSY
BSYBSY
BSY pin for end-of-write indication
■1,000,000 program/erase cycles
■100 year data retention
DESCRIPTION
The CAT64LC40 is a 4K-bit Serial EEPROM which is
configured as 256 registers by 16 bits. Each register can
be written (or read) serially by using the DI (or DO) pin.
The CAT64LC40 is manufactured using Catalyst’s
advanced CMOS EEPROM floating gate technology. It
is designed to endure 1,000,000 program/erase cycles
and has a data retention of 100 years. The device is
available in 8-pin DIP, SOIC and TSSOP packages.
BLOCK DIAGRAM
PIN CONFIGURATION
DIP Package (P, L) SOIC Package (J, W) TSSOP Package (U, Y)
PIN FUNCTIONS
Pin Name Function
CS Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
VCC +2.5V to +6.0V Power Supply
GND Ground
RESET Reset
RDY/BUSY Ready/BUSY Status
SOIC Package (S, V) TSSOP Package (UR, YR)
VCC
ADDRESS
DECODER
MEMORY ARRAY
256 x 16
DATA
REGISTER
MODE DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO
SK
CS
DI
RESET
GND
RDY/BUSY
CAT64LC40
2
CAT64LC40
Doc. No. MD-1021, Rev. E © 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice.
CAPACITANCE (TA = 25°C, f= 1.0 MHz, VCC =6.0V)
Symbol Test Max. Conditions Units
CI/O(3) Input/Output Capacitance (DO, RDY/BSY)8V
I/O = 0V pF
CIN(3) Input Capacitance (CS, SK, DI, RESET) 6 VIN = 0V pF
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units
NEND(3) Endurance 1,000,000 Cycles/Byte
TDR(3) Data Retention 100 Years
VZAP(3) ESD Susceptibility 2000 Volts
ILTH(3)(4) Latch-Up 100 mA
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
3
CAT64LC40
Doc. No. MD-1021, Rev. E
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice.
Limits
Sym. Parameter Min. Typ. Max. Test Conditions Units
ICC Operating Current 2.5V 0.4 fSK = 250 kHz mA
EWEN, EWDS, READ 6.0V 1 fSK = 1 MHz mA
ICCP Program Current 2.5V 2 mA
6.0V 3 mA
ISB(1) Standby Current 3 VIN = GND or VCC µA
CS = VCC
ILI Input Leakage Current 2 VIN = GND to VCC µA
ILO Output Leakage Current 10 VOUT = GND to VCc µA
VIL Low Level Input Voltage, DI –0.1 VCC x 0.3 V
VIH High Level Input Voltage, DI VCC x 0.7 VCC + 0.5 V
VIL Low Level Input Voltage, –0.1 VCC x 0.2 V
CS, SK, RESET
VIH High Level Input Voltage, VCC x 0.8 VCC + 0.5 V
CS, SK, RESET
VOH(1) High Level Output Voltage 2.5V VCC – 0.3 IOH = –10µA V
6.0V VCC – 0.3 IOH = –10µA V
2.4 IOH = –400µA V
VOL(1) Low Level Output Voltage 2.5V 0.4 IOL = 10µA V
6.0V 0.4 IOL = 2.1mA V
D.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +6.0V, unless otherwise specified.
Note:
(1) VOH and VOL spec applies to READY/BUSY pin also
4
CAT64LC40
Doc. No. MD-1021, Rev. E © 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) This parameter is sampled but not 100% tested.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
WRITE CYCLE LIMIITS
Symbol Parameter Min. Max. Units
tWR Program Cycle Time 2.5V 10 ms
4.5V–6.0V 5
A.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +6.0V, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Units
tCSS CS Setup Time 100 ns
tCSH CS Hold Time 100 ns
tDIS DI Setup Time 200 ns
tDIH DI Hold Time 200 ns
tPD1 Output Delay to 1 300 ns
tPD0 Output Delay to 0 300 ns
tHZ(2) Output Delay to High Impendance 500 ns
tCSMIN Minimum CS High Time 250 ns
tSKHI Minimum SK High Time 2.5V 1000 ns
4.5V–6.0V 400
tSKLOW Minimum SK Low Time 2.5V 1000 ns
4.5V–6.0V 400
tSV Output Delay to Status Valid 500 ns
fSK Maximum Clock Frequency 2.5V 250 kHz
4.5V–6.0V 1000
tRESS Reset to CS Setup Time 0 ns
tRESMIN Minimum RESET High Time 250 ns
tRESH RESET to READY Hold Time 0 ns
tRC Write Recovery 100 ns
POWER-UP TIMING(1)(3)
Symbol Parameter Min. Max. Units
tPUR Power-Up to Read Operation 10 µs
tPUW Power-Up to Program Operation 1 ms
5
CAT64LC40
Doc. No. MD-1021, Rev. E
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice.
INSTRUCTION SET
Instruction Opcode Address Data
Read 10101000 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0
Write 10100100 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0
Write Enable 10100011 X X X X X X X X
Write Disable 10100000 X X X X X X X X
[Write All Locations](1) 10100001 X X X X X X X X D15–D0
Figure 1. A.C. Testing Input/Output Waveform (2)(3)(4) (CL = 100 pF)
Note:
(1) (Write All Locations) is a test mode operation and is therefore not included in the A.C./D.C. Operations specifications.
(2) Input Rise and Fall Times (10% to 90%) < 10 ns.
(3) Input Pulse Levels = VCC x 0.2 and VCC x 0.8.
(4) Input and Output Timing Reference = VCC x 0.3 and VCC x 0.7.
INPUT PULSE LEVELS REFERENCE POINTS
VCC x 0.7
VCC x 0.3
VCC x 0.8
VCC x 0.2
6
CAT64LC40
Doc. No. MD-1021, Rev. E © 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice.
DEVICE OPERATION
The CAT64LC40 is a 4K-bit nonvolatile memory in-
tended for use with all standard controllers. The
CAT64LC40 is organized in a 256 x 16 format. All
instructions are based on an 8-bit format. There are four
16-bit instructions: READ, WRITE, EWEN, and EWDS.
The CAT64LC40 operates on a single power supply
ranging from 2.5V to 6.0V and it has an on-chip voltage
generator to provide the high voltage needed during a
programming operation. Instructions, addresses and
data to be written are clocked into the DI pin on the rising
edge of the SK clock. The DO pin is normally in a high
impedance state except when outputting data in a
READ operation or outputting RDY/BSY status when
polled during a WRITE operation.
The format for all instructions sent to this device includes
a 4-bit start sequence, 1010, a 4-bit op code and an 8-
bit address field or dummy bits. For a WRITE operation,
Figure 2. Sychronous Data Timing
Figure 3. Read Instruction Timing
* Please check the instruction set table for address
SK
DI
CS
DO
tPD0,tPD1
tCSS
tDIS
tSKHI
tSKLOW
RESET
RDY/BUSY
tRESS
tRC
tDIH
tCSH tCSMIN
tHZ tSV
tSV
tRESH
SK
DI
CS
DO
RESET
10101000 ADDRESS*
D15 D14 D1 D0
HIGH
RDY/BUSY
7
CAT64LC40
Doc. No. MD-1021, Rev. E
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice.
a 16-bit data field is also required following the 8-bit
address field.
The CAT64LC40 requires an active LOW CS in order to
be selected. Each instruction must be preceded by a
HIGH-to-LOW transition of CS before the input of the 4-
bit start sequence. Prior to the 4-bit start sequence
(1010), the device will ignore inputs of all other logical
sequence.
Figure 4. Write Instruction Timing
Figure 5. Ready/BUSYBUSY
BUSYBUSY
BUSY Status Instruction Timing
Read
Upon receiving a READ command and address (clocked
into the DI pin), the DO pin will output data one tPD after
the falling edge of the 16th clock (the last bit of the
address field). The READ operation is not affected by
the RESET input.
Write
After receiving a WRITE op code, address and data, the
device goes into the AUTO-Clear cycle and then the
* Please check instruction set table for address
SK
DI
CS
DO
RESET
10100100 ADDRESS* D15 D0
RDY/BUSY
SK
DI
CS
DO
RESET
WRITE INSTRUCTION NEXT INSTRUCTION
HIGH
LOW
RDY/BUSY
8
CAT64LC40
Doc. No. MD-1021, Rev. E © 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice.
WRITE cycle. The RDY/BSY pin will output the BUSY
status (LOW) one tSV after the rising edge of the 32nd
clock (the last data bit) and will stay LOW until the write
cycle is complete. Then it will output a logical “1” until the
next WRITE cycle. The RDY/BSY output is not affected
by the input of CS.
An alternative to get RDY/BSY status is from the DO pin.
During a write cycle, asserting a LOW input to the CS pin
will cause the DO pin to output the RDY/BSY status.
Bringing CS HIGH will bring the DO pin back to a high
impedance state again. After the device has completed
a WRITE cycle, the DO pin will output a logical “1” when
the device is deselected. The rising edge of the first “1”
input on the DI pin will reset DO back to the high
impedance state again.
The WRITE operation can be halted anywhere in the
operation by the RESET input. If a RESET pulse occurs
during a WRITE operation, the device will abort the
operation and output a READY status.
NOTE: Data may be corrupted if a RESET occurs while
the device is BUSY. If the reset occurs before the BUSY
period, no writing will be initiated. However, if RESET
occurs after the BUSY period, new data will have been
written over the old data.
Figure 6. RESET During BUSYBUSY
BUSYBUSY
BUSY Instruction Timing
Figure 7. EWEN Instruction Timing
5064 FHD F09
* Please check instruction set table for address
SK
DI
CS
DO
RESET
10100100 ADDRESS* D15 D0
tWR
RDY/BUSY
SK
DI
CS
DO
RESET
10100011
HIGH-Z
HIGH
RDY/BUSY
9
CAT64LC40
Doc. No. MD-1021, Rev. E
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice.
RESET
The RESET pin, when set to HIGH, will reset or abort a
WRITE operation. When RESET is set to HIGH while the
WRITE instruction is being entered, the device will not
execute the WRITE instruction and will keep DO in High-
Z condition.
When RESET is set to HIGH, while the device is in a
clear/write cycle, the device will abort the operation and
will display READY status on the RDY/BSY pin and on
the DO pin if CS is low.
The RESET input affects only the WRITE and WRITE
ALL operations. It does not reset any other operations
such as READ, EWEN and EWDS.
ERASE/WRITE ENABLE and DISABLE
The CAT64LC40 powers up in the erase/write disabled
state. After power-up or while the device is in an erase/
write disabled state, any write operation must be pre-
ceded by an execution of the EWEN instruction. Once
enabled, the device will stay enabled until an EWDS has
been executed or a power-down has occured. The
EWDS is used to prevent any inadvertent over-writing of
the data. The EWEN and EWDS instructions have no
affect on the READ operation and are not affected by the
RESET input.
Figure 8. EWDS Instruction Timing
SK
DI
CS
DO
RESET
10100000
HIGH-Z
HIGH
RDY/BUSY
10
CAT64LC40
Doc. No. MD-1021, Rev. E © 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice.
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a 64LC40SI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
P: PDIP
S: SOIC (JEDEC)
J: SOIC (JEDEC)
U: TSSOP
UR: TSSOP (Rotated)
L: PDIP (Lead free, Halogen free)
V: SOIC (JEDEC) (Lead free, Halogen free)
W: SOIC (JEDEC) (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
YR: TSSOP (Rotated) (Lead free, Halogen free)
64LC40
11
CAT64LC40
Doc. No. MD-1021, Rev. E
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice.
PACKAGING OUTLINE DRAWING
TSSOP 8-Lead (U)
A2
E1 E
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
θ1
L1 L
SYMBOL MIN NOM MAX
A 1.20
A1 0.05 0.15
A2 0.80 0.90 1.05
b 0.19 0.30
c 0.09 0.20
D 2.90 3.00 3.10
E 6.30 6.40 6.50
E1 4.30 4.40 4.50
e 0.65 BSC
L 1.00 REF
L1 0.50 0.60 0.75
θ1 0° 8°
Notes:
1. All dimensions are in millimeters. Angles in degrees.
2. Complies with JEDEC standard MO-153.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
12
CAT64LC40
Doc. No. MD-1021, Rev. E © 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice.
REVISION HISTORY
Date Revision Description
3-Sep-04 B Added Green packages in all areas
Updated DC Operating Characteristics table & notes
17-Nov-04 C Changed ISB from 1µA, Max to 3µA, Max in DC
Operating Characteristics table
21-May-06 D Discontinued the CAT64LC10 and CATLC205
11-Nov-08 E Update Package Outline Drawing
Change logo and fine print to ON Semicondctor
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out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights
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