IM6653/IM6654 4096-Bit CMOS UV EPROM GENERAL DESCRIPTION The intersil IM6653 and IM6654 are fully decoded 4096 bit CMOS electrically programmable ROMs (EPROMs)} fabricated with Intersil's advanced CMOS processing tech- nology. In ali static states these devices exhibit the micro- watt power dissipation typical of CMOS. Inputs and three- state outputs are TTL compatible and allow for direct interface with common system bus structures. On-chip address registers and chip select functions simplify system interfacing requirements. The IM6653 and IM6654 are specifically designed for program development applications where rapid turn-around for program changes is required. The devices may be erased by exposing their transparent lids to ultra-violet light, and then re-programmed. ORDERING INFORMATION SINMERSIL FEATURES Organization IM6653: 1024 x 4 IM6654: 512x8 @ Low Power770uW Maximum Standby High Speed ~300ns 10V Access Time For IM6653/54 Al -450ns 5V Access Time For IM6653/5411 Single +5V Supply Operation UV Erasable @ Synchronous Operation For Low Power Dissipation Three-State Outputs and Chip Select for Easy System Expansion NUMBER RANGE. PACKAGE IM663/41JG -40C to +85C 24-Pin CERDIP IM6653/4~11JG -40C to +85C 24-Pin CERDIP IM6653/4AIJG -40C to +85C 24-Pin CERDIP IM6653/4MJG* -55C to +125C 24-Pin CERDIP IM6653/4AMJG* -55C to +125C _ 24-Pin CERDIP "Add /HR for HiRel processing re one pRoaRAM AgAn : Yoo ? ; 128 x 64 ARRAY z ADORESS. LATCH X-DECODER eecceee eencces OUTPUT BUFFER 2s a J BO0024 1+ Figure 1: Functional Diagram eDonssti 000561! Figure 2: Pin Configurations 9-25 002 Note: All typical values have been guaranteed by characterization and are not tested. = a 9 a @ = = a aIMG653/IM6654 IMG6653/IM6654 EIINUERSIL ABSOLUTE MAXIMUM RATINGS (IM6653/54 I, -11, M) Supply Voltages Vpo - Vss Vcc - Vss +8.0V Input or Output Voltage ....(Vsg ~0.3V) to (Vpp +0.3V) NOTE: Stresses above those listed under Absolute Maximum Ratin: functional operation of the device at these or any other conditions Exposure to absolute maximum rating conditions for extended per DC ELECTRICAL CHARACTERISTICS above those Operating Range Range (Ta) Industrial Military Storage Temperature Range Lead Temperature (Soldering, 10sec) ~40C to +85C ~55C to +125C ~65C to + 150C igs May Cause permanent damage to the device. These are stress ratings only, and indicated in the operational sections of the specifications is not implied. riods may affect device reliability. (Vcc = Vpp = 5V +10% Vsg = OV, Ta = Operating Temperature Range) TEST 1M6653/541, -11, M SYMBOL PARAMETER CONDITIONS UNIT MIN MAX Vi Logical ''1" Input Voltage E,,5 Vop - 2.0 ViH Address Pins 27 v ViL Logical ''0"' Input Voltage 0.8 I Input Leakage GND < Vin < Voo ~1.0 1.0 BA VoH Logical ''1"' Output Voltage lon = -0.2mA 2.4 Vor Logical ''0"' Output Voltage lou = 2.0mA 0.45 v lok Output Leakage GND Vo Voc -1.0 4.0 IsTey Standby Supply Current Vin = Yoo 100 BA loc Vin = Vopo 40 \pp Operating Supply Current (1) f= 1MHz 6 mA Cc Input Capacitance Note 1 7.0 Co Output Capacitance Note 1 10.0 pF Note: 1. For design reference only, not 100% tested. AC ELECTRICAL CHARACTERISTICS (Vcc = Vop = 5V +10% Vs = OV, C_ = 50pf, Ta = Operating Temperature Range) IM6653/54-1f IM6653/54 | (IM6653/54 M SYMBOL PARAMETER UNIT MIN MAX MIN MAX MIN MAX TE;LOV Access Time From Ey 450 550 600 TSLQV Output Enable Time 410 140 150 TEHOZ Output Disable Time 110 140 150 TEyHEqL E; Pulse Width {Positive) 130 150 150 TE,LEH E; Pulse Width (Negative) 450 550 600 ns TAVE,L Address Setup Time 0 0 0 TELAX Address Hold Time 80 100 100 TEaVEqL Chip Enabie Setup Time (6654) 0 0 0 TE,LEaXx Chip Enable Hold Time (6654) 80 100 100 9-26 Note: All typical values have been quaranteed by characterization and are not tested.IMG6653/IM6654 EAIINIERSIL ABSOLUTE MAXIMUM RATINGS (IM6653/54Al, AM) Supply Voltages VDD VSS. occ eee cee ce ece cece eceeeeeecceesan tenes VOC VSS oe eee cee ccc ce eee ecceecceeenetseeevaneaees +11.0V Input or Output Voltage ....(vgg -0.3V) to (Vpp +0.3) Operating Temperature Range Industrial 0.0.0... ee -40C to +85C Military ......0....... 55C ta +125C Storage Temperature Range............ -65C ta + 150C Lead Temperature (Soldering, 10sec) NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Vcc = Vpp = 4.5V to 10.5V Vsg = OV, Ta = Operational Temperature Range) IM6653/54Al, AM SYMBOL PARAMETER TEST CONDITIONS UNIT MIN MAX Vi" Logical ''1"' input Voltage E,, 5 Voo - 2.0 Vin Address Pins Vop - 2.0 Vv VIL Logical ''0"' Input Voltage 0.6 \ input Leakage GND < Vin = Vop -1.0 1.0 uA Vou Logical ''1"' Output Voitage lout =0 (Note 1) Voc - 0.01 Vou Logical "0'' Output Voltage lout = 0 (Note 1) Vss + 0.01 Vv lok Output Leakage Vss Vo S Voc -1.0 1.0 IstBy Standby Supply Current Vin = Vpp 100 pA Icc Vin = Vop 40 Ippo Operating Supply Current f = 1MHz 12 mA Cy input Capacitance Note 1 7.0 Co Output Capacitance Note 1 10.0 pF Note: 1. For design reference only, not 100% tested. AC ELECTRICAL CHARACTERISTICS (Vcc = Vpp = 10V +5% Vgs = OV, C, = 50pf, Ta = Operating Temperature Range) IM6653/54 Al 1M6653/54 AM SYMBOL PARAMETER UNIT MIN MAX MIN MAX TEsLQV Accass Time From Ey 300 350 TSLQV Output Enable Time 60 70 TE,HQZ Output Disable Time 60 70 TEyHEyL E; Pulse Width (Positive) 125 125 TE1LE,H E, Pulse width (Negative) 300 350 ns TAVE4L Address Setup Time 0 a TE1LAX Address Hold Time 60 60 TE2VEqL Chip Enable Setup Time (6654) 0 0 TE;LE2Xx Chip Enable Hoid Time (6654) 60 60 9-27 Note: Ail typical values have been guaranteed by characterization and are not tested. bSOOWI/ES9ONIIMG653/IM6654 IM6653/IM6654 PIN ASSIGNMENTS @IINTERSIL ACTIVE PiN SYMBOL LEVEL DESCRIPTION 1-8,23 Ao-A7,Ag - Address Lines 9-11, 13-17 Qo-Q7 - Data Out lines, 6654 Qo-Q3 - Data Out lines, 6653 12 Vss - Negative Supply 18 Program - Programming pulse input 19 Voo - Chip positive supply, normally tied to Voc 20 Ey L Strobe line, latches both address lines and, for 6654, Chip enable Eo 21 $s L Chip select line, must be low far valid data out 22 Ag - Additional address line for 6653 _ Eo Chip enabie line, latched by Chip enable E; on 6654 24 Voc ~ Output buffer positive supply Spans READ MODE OPERATION . In a typical READ operation address lines and chip enable E>* are latched by tne falling edge of chip enabie E, z (T = 0). Valid data appears at the outputs one access time (TELQV) later, provided level-sensitive chip select line S is tow (T = 3). Data remains vaiid until either E; or S returns to a high level (T = 4). Outputs are then forced to a high-Z state. TE,HEE View TAVELL TEVE,L Aadress lines and Ez must be valid one setup time before (TAVEL), and one hold time after (VELAX), the falling edge of E, starting the read cycle. Before becoming vaiid, Q output lines become active (T = 2). The Q output lines return to a high-Z state one output disable time (TE;HQZ) after any rising edge on E; or S. Sv The program line remains high throughout the READ PROGRAM cycle. he IMBESS only, E2 1M6654 oniy Chip enable tine E, must remain high one minimum positive puise width (TEHEL) before the next cycle can begin. WFOOSBO! Figure 3: Read Cycle Timing FUNCTION TABLE TIME INPUTS OUTPUTS REF Q NOTES E1 | 2 | 5 A t x | x x z DEVICE INACTIVE 9 ~ | cl x Vv z CYCLE BEGINS: ADDRESSES, Es LATCHED* 1 c |x f x x z INTERNAL OPERATIONS ONLY 2 Li x do x A OUTPUTS ACTIVE UNDER CONTROL OF Ey, 3 Lyx du x Vv OUTPUTS VALID AFTER ACCESS TIME 4 rfl x foe x Vv READ COMPLETE 5 H | x | x x Z CYCLE ENDS (SAME AS -1) 9-28 Note: All typical values have been guaranteed by characterization and are not tested.IM6653/IM6654 INTERSIL I READ | | READ _______ WFOCS9OI Figure 4: Read and Program Cycle Timing DC CHARACTERISTICS FOR PROGRAMMING OPERATION (Vcc = Vpp = 5V +5% Vss= OV, Ta = 25C) SYMBOL PARAMETER TEST MIN TYP MAX UNIT CONDITIONS iPROG Program Pin Load Current 80 100 mA VpROG Programming Pulse Amplitude ~38 ~40 -42 Vv oc Voc Current 01 5 lbp Vpp Current 40 100 mA VIHA Address Input High Voltage Vop-2.0 VILA Address Input Low Voltage 0.8 Vin Data input High Voltage Vop-20 Vv Vit Oata Input Low Voltage 0.8 AC CHARACTERISTICS FOR PROGRAMMING OPERATION (Voc = Vop = 5V +5% Vss = OV, Ta = 25) SYMBOL PARAMETER TEST MIN TYP MAX UNIT CONDITIONS TPLPH Program Pulse Width tnse = tall = SHS 18 20 22 ms Program Puise Duty Cycle 75% TOVPL Data Setup Time 9 TPHDX Data Hold Time 9 us TE,HEyL Strobe Pulse Width 150 TAVE,L Address Setup Time 0 TE1LE,x Address Hold Time 100 ns TE,;LOQV Access Time 1000 PROGRAM MODE OPERATION initially, all 4096 bits of the EPROM are in the logic one {output high) state. Selective programming of proper bit locations to ''O''s is performed electrically. In the PROGRAM mode for alt EPROMs, Voc and Vop are tied together to a +5V operating supply. High logic levels at all of the appropriate chip inputs and outputs must be set at Vpp -2V minimum. Low iogic levels must be set at Vgs +0.8V maximum. Addressing of the desired location in PROGRAM mode is done as in the READ mode. Address and data lines are set at the desired logic levels, and PROGRAM and chip select (S) pins are set high. The address is latched by the downward edge on the strobe line (E1). During valid DATA IN time, the PROGRAM pin is pulsed from Vpp to -40V. This pulse initiates the program- 9-29 Note: All typical values have been guaranteed by characterization and are not tested. PSOONI/ESOSNMIIM6653 /IM6654 IM6653/IM6654 ming of the device to the levels set on the data outputs. Duty cycle limitations are specified from chip heat dissipa- tion considerations. PULSE RISE AND FALL TIMES MUST NOT BE FASTER THAN 5uys. Intelligent programmer equipment with successive READ/PROGRAM/VERIFY sequences is recommended. PROGRAMMING SYSTEM CHARACTERISTICS 1. During programming the power supply should be capable of timiting peak instantaneous current to 100mA. 2. The programming pin is driven from Vpp to -40 volts (t2V) by pulses of 20 milliseconds duration. These pulses should be applied in the sequence shown in the flow chart. Pulse rise and fail times of 10 microseconds are recommended. Note that any individual location may be programmed at any time. 9-30 EAIINWERSIL 3. Addresses and data should be presented to the device within the recommended setup/hoid time and high/iow logic tevel margins. Both "A" (10V) and non "A" EPROMs are programmed at Vcc, Vpp of 5V +5%. 4. Programming is to be done at room temperature. ERASING PROCEDURE The IM6653/54 are erased by exposure to high intensity short-wave ultraviolet light at a wavelength of 2537A. The recommended integrated dose (i.e., UV intensity x exposure time) is 10W sec/cm?. The lamps should be used without short-wave filters, and the IM6653/54 to be erased should be placed about one inch away from the lamp tubes. For best results it is recommended that the device remain inactive for 5 minutes after erasure, before reprogramming. The erasing effect of UV light is cumulative. Care should be taken to protect EPROMs from exposure to direct sunlight or fluorescent lamps radiating UV light in the 2000A to 4000A range. Note: All typical values have been guaranteed by characterization and are not tested.IM6653/IM6654 INTERSIL POWER DOW ALL INPUTS, Veo, Vw = Voo = GND PSOONI/ESOONI POWER UP Voc TO APPROPRA VOLTAGE POWER UP weuTs REA THROUGH ALL ADDRESSES TO VERIFY ALL 1S (ERASED) AT SV SET LEVELS OW Q DATA LINES PROGRAM SAME LOCATION & MORE THES Looas101 Figure 5: Programming Flow Chart 9-31 Note: Ali typical values have been guaranteed by characterization and are not tested.IM6653/IM6654 IM6653/IM6654 ESINITERSIL ODtF Veo Voo 3 vss Q INPUT AFO2 1411 Figure 6: IM6653 CMOS EPROMS as External Program Memory with the IM80C35 HMAG6S4 S208 CMOS EPROM 48001001 Figure 7: Using IM6654 CMOS EPROM To Extend Program Memory 9-32 Note: All typical values have been guaranteed by characterization and are not tested.