© Semiconductor Components Industries, LLC, 2001
October, 2017 − Rev. 11
1Publication Order Number:
SL05T1/D
SL05T1G Series
ESD Protection Diode
Low Capacitance
This family of surge protection offers transient overvoltage protection
with significantly reduced capacitance. The capacitance is lowered by
integrating a compensating diode in series. This integrated solution
offers ESD protection for high speed interfaces such as communication
systems, computers, and computer peripherals.
Features
•Surge protection Diode in Series with a Compensating Diode Offers
<5 pF Capacitance
•ESD Protection Meeting IEC 61000−4−2, 4−4, 4−5
•Peak Power Rating of 300 W, 8 × 20 ms
•Bi−Direction Protection Can Be Achieved By Using Two Devices
•Flammability Rating UL 94 V−0
•SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Mechanical Characteristics:
CASE: Void-free, transfer-molded, thermosetting plastic case
FINISH: Corrosion resistant finish, easily solderable
MAXIMUM CASE TEMPERATURE FOR SOLDERING PURPOSES:
260°C for 10 Seconds
Package designed for optimal automated board assembly
Small package size for high density applications
Available in 8 mm Tape and Reel
Use the Device Number to order the 7 inch/3,000 unit reel.
Replace the “T1” with “T3” in the Device Number to order the
13 inch/10,000 unit reel.
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SOT−23 (TO−236)
CASE 318
STYLE 26
21
3 (NC)
1
2
3
Device Package Shipping†
ORDERING INFORMATION
SL05T1G SOT−23
(Pb−Free)
3000/Tape & Reel
SL15T1G SOT−23
(Pb−Free)
3000/Tape & Reel
SL24T1G SOT−23
(Pb−Free)
3000/Tape & Reel
Lxx M G
G
MARKING
DIAGRAM
See specific marking information in the device marking
column of the table on page 2 of this data sheet.
DEVICE MARKING INFORMATION
Lxx = Device Code
xx = 05, 12, 15, or 24
M = Date Code*
G= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or overbar may vary
depending upon manufacturing location.
SZSL24T1G SOT−23
(Pb−Free)
3000/Tape & Reel
SZSL15T1G SOT−23
(Pb−Free)
3000/Tape & Reel
SZSL05T1G SOT−23
(Pb−Free)
3000/Tape & Reel
SL12T1G SOT−23
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
SZSL12T1G SOT−23
(Pb−Free)
3000/Tape & Reel
SL05T1G Series
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2
MAXIMUM RATINGS
Rating Symbol Value Unit
Peak Power Dissipation @ 8x20 usec (Note 1)
@ TL ≤ 25°C
Ppk 300 W
IEC 61000−4−2 Level 4
Contact Discharge
Air Discharge
IEC 61000−4−4 EFT
IEC 61000−4−5 Lightning
Vpp
±8
±16
40
12
kV
kV
A
A
Total Power Dissipation on FR−5 Board (Note 2) @ TA = 25°C
Derate above 25°C
°PD°225
1.8
°mW°
mW/°C
Thermal Resistance Junction to Ambient RqJA 556 °C/W
Total Power Dissipation on Alumina Substrate (Note 3) @ TA = 25°C
Derate above 25°C
°PD°300
2.4
°mW
mW/°C
Thermal Resistance Junction−to−Ambient RqJA 417 °C/W
Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C
Lead Solder Temperature − Maximum (10 Second Duration) TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Non−repetitive current pulse per Figure 2
2. FR−5 = 1.0 x 0.75 x 0.62 in.
3. Alumina = 0.4 x 0.3 x 0.024 in., 99.5% alumina
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
UNIDIRECTIONAL
Symbol Parameter
IPP Maximum Reverse Peak Pulse Current
VCClamping Voltage @ IPP
VRWM Working Peak Reverse Voltage
IRMaximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
ITTest Current
QVBR Maximum Temperature Coefficient of VBR
IFForward Current
VFForward Voltage @ IF
ZZT Maximum Zener Impedance @ IZT
IZK Reverse Current
ZZK Maximum Zener Impedance @ IZK
Uni−Directional
IPP
IF
V
I
IR
IT
VRWM
VCVBR
VF
ELECTRICAL CHARACTERISTICS
Device
Device
Marking
VRWM IR @ VRWM
Breakdown Voltage
(Note 4)
VC, Clamping Voltage
(Note 5) Max
IPP
Capacitance
VBR @ 1 mA (Volts) @ 1 A @ 5 A @ VR = 0 V, 1 MHz (pF)
(V) (mA) Min Max (V) (V) (A) Typ Max
SL05 L05 5.0 20 6.0 8.0 9.8 11 17 3.5 5.0
SL12 L12 12 1.0 13.3 15.5 19 24 12 3.5 5.0
SL15 L15 15 1.0 16.7 18.5 24 30 10 3.5 5.0
SL24 L24 24 1.0 26.7 29 43 55 5.0 3.5 5.0
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. VBR measured at pulse test current of 1 mA at an ambient temperature of 25°C
5. Surge current waveform per Figure 2
SL05T1G Series
www.onsemi.com
3
TYPICAL CHARACTERISTICS
0.1 10
10
Figure 1. Maximum Peak Power Rating
1
PULSE WIDTH (ms)
100 1000
1
0.1
0.01
Figure 2. 8 × 20 ms Pulse Waveform
PPK, PEAK POWER (kW)
100
90
80
70
60
50
40
30
20
10
00204060
t, TIME (ms)
% OF PEAK PULSE CURRENT
tP
tr
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE IRSM @ 8 ms
HALF VALUE IRSM/2 @ 20 ms
80
Figure 3. Typical Junction Capacitance
−55 25 150
10
1
0.1
0.01
Figure 4. Typical Leakage Over Temperature
TEMPERATURE (°C)
@ 50% VRWM
4
3.5
3
2
1.5
0.5
0
C, CAPACITANCE (pF), 1 MHz FREQ.
2.5
1
@ ZERO BIAS @ VRWM
SL05
SL15
SL24
LEAKAGE (mA)
SL05T1
SL05T1G Series
www.onsemi.com
4
Applications Background
This family of surge protection devices (SL05T1 series)
are designed to protect sensitive electronics such as
communications systems, computers, and computer
peripherals against damage due to ESD conditions or
transient voltage conditions. Because of their low
capacitance value (less than 5 pF), they can be used in high
speed I/O data lines. Low capacitance is achieved by
integrating a compensating diode in series with the surge
protection which is basically based in the below theoretical
principle:
•Capacitance in parallel: CT = C1+C2+....+Cn
•Capacitance in series: 1/CT = (1/C1)+(1/C2)+....+(1/Cn)
The Figure 5 shows the integrated solution of the SL05T1
series device:
Figure 5.
COMPENSATING
DIODE
Surge
protection
In the case that an over−voltage condition occurs in the I/O
line protected by the SL05T1 series device, the surge
protection is reversed−biased while the compensation diode
is forward−biased so the resulting current due to the
transient voltage is drained to ground.
If protection in both polarities is required, an additional
device is connected in inverse−parallel with reference to the
first one, the Figure 6 illustrates the inverse−parallel
connection for bi−directional or unidirectional lines:
Figure 6.
3
2
1
3
2
1
An alternative solution to protect unidirectional lines, is to
connect a fast switching steering diode in parallel with the
SL05T1 series device. When the steering diode is
forward−biased, the surge protection will avalanche and
conduct in reverse direction. It is important to note that by
adding a steering diode, the effective capacitance in the
circuit will be increased, therefore the impact of adding a
steering diode must be taken in consideration to establish
whether the incremental capacitance will affect the circuit
functionality or not. The Figure 7 shows the connection
between the steering diode and the SL05T1 series device:
Figure 7.
STEERING DIODE
SL05T1 DEVICE
Another typical application in which the SL05T1 series
device can be utilized, is to protect multiple I/O lines. The
protection in each of the I/O lines is achieved by connecting
two devices in inverse−parallel. The Figure 8 illustrates how
multiple I/O line protection is achieved:
Figure 8.
OUTPUTINPUT
For optimizing the protection, it is recommended to use ground planes and short path lengths to minimize the PCB’s ground inductance.
SL05T1G Series
www.onsemi.com
5
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AR
D
A1
3
12
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
SOLDERING FOOTPRINT*
VIEW C
L
0.25
L1
e
EE
b
A
SEE VIEW C
DIM
A
MIN NOM MAX MIN
MILLIMETERS
0.89 1.00 1.11 0.035
INCHES
A1 0.01 0.06 0.10 0.000
b0.37 0.44 0.50 0.015
c0.08 0.14 0.20 0.003
D2.80 2.90 3.04 0.110
E1.20 1.30 1.40 0.047
e1.78 1.90 2.04 0.070
L0.30 0.43 0.55 0.012
0.039 0.044
0.002 0.004
0.017 0.020
0.006 0.008
0.114 0.120
0.051 0.055
0.075 0.080
0.017 0.022
NOM MAX
L1
H
2.10 2.40 2.64 0.083 0.094 0.104
HE
0.35 0.54 0.69 0.014 0.021 0.027
c
0−−− 10 0 −−− 10
T°°°°
T
3X
TOP VIEW
SIDE VIEW
END VIEW
2.90
0.80
DIMENSIONS: MILLIMETERS
0.90
PITCH
3X
3X 0.95
RECOMMENDED
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLE 26:
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
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SL05T1/D
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