Integrated Circuit Systems, Inc. ICS85311 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS85311 is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V ECL/ HiPerClockSTM LVPECL Fanout Buffer and a member of the HiPerClockSTM family of High Perfor mance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels.T h e ICS85311 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and par tto-par t skew characteristics make the ICS85311 ideal for those clock distribution applications demanding well defined perfor mance and repeatability. * Two differential 2.5V/3.3V LVPECL / ECL outputs ICS * One CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency: 1GHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input * Output skew: 15ps (maximum) * Part-to-part skew: 100ps (maximum) * Propagation delay: 1.4ns (maximum) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.465V * 0C to 70C ambient operating temperature * Available in both, Standard and RoHS/Lead-Free compliant packages * Industrial temperature information available upon request BLOCK DIAGRAM CLK nCLK PIN ASSIGNMENT Q0 nQ0 Q1 nQ1 Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 Vcc CLK nCLK VEE ICS85311 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View ICS85311AM www.icst.com/products/hiperclocks.html 1 REV. C APRIL 11, 2007 ICS85311 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type 1, 2 Q0, nQ0 Output Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5 VEE Power Negative supply pin. 6 nCLK Input 7 CLK Input 8 VCC Power Pullup Description Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Positive supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k ICS85311AM www.icst.com/products/hiperclocks.html 2 REV. C APRIL 11, 2007 ICS85311 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 112C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Positive Supply Voltage 3.135 3.3 3.465 V VCC Positive Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 25 mA TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = 0C TO 70C Symbol Parameter IIH Input High Current IIL Input Low Current Maximum Units CLK VCC = VIN = 3.465V or 2.625V Test Conditions Minimum Typical 150 A nCLK VCC = VIN = 3.465V or 2.625V 5 A CLK VCC = 3.465V or 2625V, VIN = 0V -5 A nCLK VCC = 3.465V or 2.625V, VIN = 0V -150 A VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VEE + 0.5 VCMR NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltag for CLK, nCLK is VCC + 0.3V. 1.3 V VCC - 0.85 V TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = 0C TO 70C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCC - 1.4 VCC - 0.9 V VCC - 2.0 VCC - 1.7 V 0.65 1.0 V NOTE 1: Outputs terminated with 50 to VCC - 2V. ICS85311AM www.icst.com/products/hiperclocks.html 3 REV. C APRIL 11, 2007 Integrated Circuit Systems, Inc. ICS85311 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER TABLE 4. AC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = 0C TO 70C Symbol Parameter fMAX Maximum Output Frequency t PD Propagation Delay; NOTE 1 Test Conditions 1GHz Minimum Typical 0.9 Maximum Units 1 GHz 1.4 ns tsk(o) Output Skew; NOTE 2, 4 15 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 100 ps tR Output Rise Time 20% to 80% @ 50MHz 300 700 ps tF Output Fall Time 20% to 80% @ 50MHz 300 700 ps 52 % odc Output Duty Cycle 48 All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. ICS85311AM www.icst.com/products/hiperclocks.html 4 REV. C APRIL 11, 2007 Integrated Circuit Systems, Inc. ICS85311 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V 2V V CC Qx SCOPE V CC Qx SCOPE LVPECL LVPECL nQx VEE nQx VEE -0.5V 0.125V -1.3V 0.165V 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT V CC nQx nCLK Qx V Cross Points PP V CMR nQy CLK0 Qy tsk(o) VEE OUTPUT SKEW DIFFERENTIAL INPUT LEVEL PART 1 nQx 80% 80% Qx VSW I N G PART 2 nQy Clock Outputs 20% 20% tF tR Qy tsk(pp) OUTPUT RISE/FALL TIME PART-TO-PART SKEW nQx nCLK Qx CLK0 t PW t nQ0, nQ1 Q0, Q1 odc = tPD t PW x 100% t PERIOD PROPAGATION DELAY ICS85311AM PERIOD Output Duty Cycle/Pulse Width/PERIOD www.icst.com/products/hiperclocks.html 5 REV. C APRIL 11, 2007 ICS85311 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR 3.3V LVPECL OUTPUTS 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50 125 FOUT 125 FIN Zo = 50 Zo = 50 FOUT 50 RTT = 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o Zo = 50 VCC - 2V RTT 84 FIGURE 2A. LVPECL OUTPUT TERMINATION ICS85311AM FIN 50 84 FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 6 REV. C APRIL 11, 2007 Integrated Circuit Systems, Inc. ICS85311 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. 2.5V VCC=2.5V 2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm R3 250 + Zo = 50 Ohm + Zo = 50 Ohm - Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVPECL OUTPUTS: All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. ICS85311AM www.icst.com/products/hiperclocks.html 7 REV. C APRIL 11, 2007 ICS85311 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE ICS85311AM www.icst.com/products/hiperclocks.html 8 REV. C APRIL 11, 2007 Integrated Circuit Systems, Inc. ICS85311 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85311. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85311 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 25mA = 86.6mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 86.6mW + 60mW = 146.6mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.147W * 103.3C/W = 85.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5. THERMAL RESISTANCE JA FOR 8-PIN SOIC, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3C/W 112.7C/W 128.5C/W 103.3C/W 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. ICS85311AM www.icst.com/products/hiperclocks.html 9 REV. C APRIL 11, 2007 ICS85311 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CC * For logic high, VOUT = V OH_MAX (V CC_MAX * -V OH_MAX OL_MAX CC_MAX -V OL_MAX CC_MAX - 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CC_MAX - 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V - (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= Pd_H = [(V OH_MAX CC_MAX CC_MAX OH_MAX CC_MAX OH_MAX CC_MAX OH_MAX L L [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(V OL_MAX - (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V )= OL_MAX [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ICS85311AM www.icst.com/products/hiperclocks.html 10 REV. C APRIL 11, 2007 Integrated Circuit Systems, Inc. ICS85311 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3C/W 112.7C/W 128.5C/W 103.3C/W 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85311 is: 225 ICS85311AM www.icst.com/products/hiperclocks.html 11 REV. C APRIL 11, 2007 Integrated Circuit Systems, Inc. ICS85311 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUN MAXIMUM N 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 e 4.00 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 Reference Document: JEDEC Publication 95, MS-012 ICS85311AM www.icst.com/products/hiperclocks.html 12 REV. C APRIL 11, 2007 ICS85311 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS85311AM 85311AM 8 lead SOIC tube 0C to 70C ICS85311AMT 85311AM 8 lead SOIC 2500 tape & reel 0C to 70C ICS85311AMLF 85311ALF 8 lead "Lead Free" SOIC tube 0C to 70C ICS85311AMLFT 85311ALF 8 lead "Lead Free" SOIC 2500 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS85311AM www.icst.com/products/hiperclocks.html 13 REV. C APRIL 11, 2007 Integrated Circuit Systems, Inc. ICS85311 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER REVISION HISTORY SHEET Rev Table A Page Added Termination for LVPECL Outputs section. 3.3V Output Load Test Circuit Diagram - corrected VEE equation to read -1.3V 0.165V from 0.135V. T2 7 1 2 3 3 T8 T8 5 6 7 8 13 7 13 T3C 3 Updated Output Rise/Fall Time Diagram. Add Lead-Free bullet in Features section. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings, updated Outputs rating. Combined 3.3V & 2.5V Power tables and Differential DC Characteristics tables. Updated Parameter Measurement Information. Updated Single Ended Signal Driving Differential Input diagram. Added Termination for 2.5V LVPECL Output section. Added Differential Clock Input Interface section. Ordering Information table - added Lead Free par t number. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - corrected Lead-Free marking and added Lead-Free Note. LVPECL DC Characteristics Table -corrected VOH max. from VCC - 1.0V to VCCO - 0.9V; and VSWING max. from 0.9V to 1.0V. Power Considerations - corrected power dissipation to reflect VOH max in Table 3C. A B B C ICS85311AM Description of Change 8 5 9 - 10 www.icst.com/products/hiperclocks.html 14 Date 5/30/02 9/23/02 6/17/04 7/28/05 4/11/07 REV. C APRIL 11, 2007