ICS85311AM www.icst.com/products/hiperclocks.html REV. C APRIL 11, 2007
1
Integrated
Circuit
Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS85311 is a low skew, high perfor-
mance 1-to-2 Differential-to-2.5V/3.3V ECL/
LVPECL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance
Clock Solutions from ICS. The CLK, nCLK pair
can accept most standard differential input levels.The
ICS85311 is characterized to operate from either a 2.5V
or a 3.3V power supply. Guaranteed output and part-
to-part skew characteristics make the ICS85311 ideal
for those clock distribution applications demanding
well defined performance and repeatability.
FEATURES
•Two differential 2.5V/3.3V LVPECL / ECL outputs
•One CLK, nCLK input pair
•CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•Maximum output frequency: 1GHz
•Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
•Output skew: 15ps (maximum)
•Part-to-part skew: 100ps (maximum)
•Propagation delay: 1.4ns (maximum)
•LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
•ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.465V
•0°C to 70°C ambient operating temperature
•Available in both, Standard and RoHS/Lead-Free
compliant packages
•Industrial temperature information available upon request
BLOCK DIAGRAM PIN ASSIGNMENT
ICS85311
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
HiPerClockS™
ICS
Vcc
CLK
nCLK
VEE
8
7
6
5
Q0
nQ0
Q1
nQ1
CLK
nCLK
ICS85311AM www.icst.com/products/hiperclocks.html REV. C APRIL 11, 2007
2
Integrated
Circuit
Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
rebmuNemaNepyTnoitpircseD
2,10Qn,0QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
4,31Qn,1QtuptuO.sleveleca
fretniLCEPVL.riaptuptuolaitnereffiD
5V
EE
rewoP.nipylppusevitageN
6KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
7KLCtupnInwodlluP.tupnikcolclaitnereffi
dgnitrevni-noN
8V
CC
rewoP.nipylppusevitisoP
:ETON pulluP dna nwodlluP .seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisert
upnilanretniotrefer
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
ICS85311AM www.icst.com/products/hiperclocks.html REV. C APRIL 11, 2007
3
Integrated
Circuit
Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSevitisoP 531.33.3564.3V
V
CC
egatloVylppuSevitisoP 573.25.2526.2V
I
EE
tnerruCylppuSrewoP 52Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCV
CC
V=
NI
V526.2roV564.3=051Aµ
KLCnV
CC
V=
NI
V526.2roV564.3=5Aµ
I
LI
tnerruCwoLtupnI KLCV
CC
V,V5262roV564.3=
NI
V0=5-Aµ
KLCnV
CC
V,V526.2roV564.3=
NI
V0=051-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 51.03.1V
V
RMC
;egatloVtupnIedoMnommoC
2,1ETON V
EE
5.0+V
CC
58.0-V
VsadenifedsiegatlovedomnommoC:1ETON
HI
.
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CC
.V3.0+
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC 4.6V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA 112°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
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HO
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CC
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CC
9.0-V
V
LO
1ETON;egatloVwoLtuptuOV
CC
0.2-V
CC
7.1-V
V
GNIWS
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05htiwdetanimretstuptuO:1ETON ΩVot
CC
.V2-
ICS85311AM www.icst.com/products/hiperclocks.html REV. C APRIL 11, 2007
4
Integrated
Circuit
Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
TABLE 4. AC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
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ICS85311AM www.icst.com/products/hiperclocks.html REV. C APRIL 11, 2007
5
Integrated
Circuit
Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
OUTPUT SKEW
PART-TO-PART SKEW OUTPUT RISE/FALL TIME
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
PROPAGATION DELAY Output Duty Cycle/Pulse Width/PERIOD
SCOPE
Qx
nQx
LVPECL
2V
-1.3V ± 0.165V
V
CMR
Cross Points
V
PP
VCC
VEE
CLK0
nCLK
t
sk(o)
nQx
Qx
nQy
Qy
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
Qx
nQx
tPD
CLK0
nCLK
Q0, Q1
nQ0, nQ1
tsk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
VEE
VCC
SCOPE
Qx
nQx
LVPECL
2V
-0.5V ± 0.125V
VEE
VCC
ICS85311AM www.icst.com/products/hiperclocks.html REV. C APRIL 11, 2007
6
Integrated
Circuit
Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
APPLICATION INFORMATION
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
V
CC
- 2V
50Ω50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
FIGURE 2B. LVPECL OUTPUT TERMINATIONFIGURE 2A. LVPECL OUTPUT T ERMINATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
3.3V
125Ω125Ω
84Ω84Ω
Zo = 50Ω
Zo = 50Ω
FOUT FIN
V_REF
R1
1K
C1
0.1u R2
1K
Single Ended Clock Input
CLK
nCLK
VCC
ICS85311AM www.icst.com/products/hiperclocks.html REV. C APRIL 11, 2007
7
Integrated
Circuit
Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in Figure 3C.
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER T ERMINATION EXAMPLE
FIGURE 3A. 2.5V LVPECL DRIVER T ERMINATION EXAMPLE
R2
62.5
Zo = 50 Ohm
R1
250
+
-
2.5V
2,5V LVPECL
Driv er
R4
62.5
R3
250
Zo = 50 Ohm
2.5V
VCC=2.5V
R1
50
R3
18
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
VCC=2.5V
2.5V
R2
50
2,5V LVPECL
Driv er
VCC=2.5V
R1
50
R2
50
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
+
-
OUTPUTS:
LVPECL OUTPUTS:
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
ICS85311AM www.icst.com/products/hiperclocks.html REV. C APRIL 11, 2007
8
Integrated
Circuit
Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to 4E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 4A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
ICS85311AM www.icst.com/products/hiperclocks.html REV. C APRIL 11, 2007
9
Integrated
Circuit
Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85311.
Equations and example calculations are also provided.
1. P ower Dissipation.
The total power dissipation for the ICS85311 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 25mA = 86.6mW
•Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 86.6mW + 60mW = 146.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.147W * 103.3°C/W = 85.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 5. THERMAL RESISTANCE θθ
θθ
θJA FOR 8-PIN SOIC, FORCED CONVECTION
ICS85311AM www.icst.com/products/hiperclocks.html REV. C APRIL 11, 2007
10
Integrated
Circuit
Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CC
- 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX - VOH_MAX
) = 0.9V
• For logic low, VOUT = VOL_MAX = VCC_MAX
– 1.7V
(VCC_MAX - VOL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX
))/R
L
] * (VCC_MAX
- VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX
))/R
L
] * (VCC_MAX
- VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 5. LVPECL DRIVER CIRCUIT AND T ERMINATION
Q1
VOUT
VCC
RL
50
VCC - 2V
ICS85311AM www.icst.com/products/hiperclocks.html REV. C APRIL 11, 2007
11
Integrated
Circuit
Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS85311 is: 225
TABLE 6. θJAVS. AIR FLOW T ABLE FOR 8 LEAD SOIC
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS85311AM www.icst.com/products/hiperclocks.html REV. C APRIL 11, 2007
12
Integrated
Circuit
Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-012
LOBMYS sretemilliM
NUMINIMMUMIXAM
N8
A53.157.1
1A01.052.0
B33.015.0
C91.052.0
D08.400.5
E08.300.4
eCISAB72.1
H08.502.6
h52.005.0
L04.07
2.1
α°0°8
ICS85311AM www.icst.com/products/hiperclocks.html REV. C APRIL 11, 2007
13
Integrated
Circuit
Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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ICS85311AM www.icst.com/products/hiperclocks.html REV. C APRIL 11, 2007
14
Integrated
Circuit
Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
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fnItnemerusaeMretemaraPdetadpU
.margaidtupnIlaitnereffiDgnivirDlangiSdednEelgniSdetadpU
.noitcestuptuOL
CEPVLV5.2rofnoitanimreTdeddA
.noitcesecafretnItupnIkcolClaitnereffiDdeddA
.rebmuntrapeerFdaeLdedda-elba
tnoitamrofnIgniredrO
40/71/6
B8T
7
31
.sniPtuptuOdnatupnIdesunUrofsnoitadnemmoceRdeddA
deddadnagnikrameerF-d
aeLdetcerroc-elbaTnoitamrofnIgniredrO
.etoNeerF-daeL
50/82/7
C
C3T3
01-9
-elbaTscitsiretcarahCCDLCEPVLVdetcer
roc
HO
Vmorf.xam
CC
VotV0.1-
OCC
Vdna;V9.0-
GNIWS
.V0.1otV9.0morf.xam
Vtcelferotnoitapissidrewopdetcerroc-snoitaredisnoCrewoP
HO
elbaTnixam
.C3
70/11/4
