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FEATURES DESCRIPTION
APPLICATIONS
1
2
3
4
8
7
6
5
DIN
SCLK
CS
DOUT
VDD
OUT
REFIN
AGND
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
10-BIT DIGITAL-TO-ANALOG CONVERTERS
•10-Bit CMOS Voltage Output DAC in an
The TLC5615 is a 10-bit voltage output8-Terminal Package
digital-to-analog converter (DAC) with a bufferedreference input (high impedance). The DAC has an•5V Single Supply Operation
output voltage range that is two times the reference•3-Wire Serial Interface
voltage, and the DAC is monotonic. The device is•High-Impedance Reference Inputs
simple to use, running from a single supply of 5V. Apower-on-reset function is incorporated to ensure•Voltage Output Range: 2 Times the Reference
repeatable start-up conditions.Input Voltage•Internal Power-On Reset
Digital control of the TLC5615 is over a three-wireserial bus that is CMOS compatible and easily•Low Power Consumption: 1.75mW Max
interfaced to industry standard microprocessor and•Update Rate of 1.21MHz
microcontroller devices. The device receives a 16-bit•Settling Time to 0.5LSB: 12.5 µs Typ
data word to produce the analog output. The digitalinputs feature Schmitt triggers for high noise•Monotonic Over Temperature
immunity. Digital communication protocols include•Pin-Compatible With the Maxim MAX515
the SPI™, QSPI™, and Microwire™ standards.
The 8-terminal small-outline D package allows digitalcontrol of analog functions in space-critical•Battery-Powered Test Instruments
applications. The TLC5615C is characterized for•Digital Offset and Gain Adjustment
operation from 0 °C to +70 °C. The TLC5615I is•Battery Operated/Remote Industrial Controls
characterized for operation from –40 °C to +85 °C.•Machine and Motion Control Devices
D, P, OR DGK PACKAGE•Cellular Telephones
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SPI, QSPI are trademarks of Motorola, Inc.Microwire is a trademark of National Semiconductor Corporation.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 1996–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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_
+
DAC
10-Bit DAC Register
Power-ON
Reset
Control
Logic
16-Bit Shift Register
4
Dummy
Bits
2
0s 10 Data Bits
(LSB) (MSB)
REFIN
AGND
CS
SCLK
DIN
OUT
(Voltage Output)
_
+
DOUT
R R
2
PACKAGE/ORDERING INFORMATION
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
FUNCTIONAL BLOCK DIAGRAM
Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME NO.
DIN 1 I Serial data inputSCLK 2 I Serial clock inputCS 3 I Chip select, active lowDOUT 4 O Serial data output for daisy chainingAGND 5 Analog groundREFIN 6 I Reference inputOUT 7 O DAC analog voltage outputV
DD
8 Positive power supply
For the most current package and ordering information, see the Package Option Addendum at the end of thisdocument, or see the TI website at www.ti.com .
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage (V
DD
to AGND) 7VDigital input voltage range to AGND –0.3V to V
DD
+ 0.3VReference input voltage range to AGND –0.3V to V
DD
+ 0.3VOutput voltage at OUT from external source V
DD
+ 0.3VContinuous current at any terminal ±20mAOperating free-air temperature range, T
A
TLC5615C 0 °C to +70 °CTLC5615I –40 °C to +85 °CStorage temperature range, T
stg
–65 °C to +150 °CLead temperature 1,6mm (1/16 inch) from case for 10 seconds +260 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
MIN NOM MAX UNIT
Supply voltage, V
DD
4.5 5 5.5 VHigh-level digital input voltage, V
IH
2.4 VLow-level digital input voltage, V
IL
0.8 VReference voltage, V
ref
to REFIN terminal 2 2.048 V
DD
–2 VLoad resistance, R
L
2 k ΩTLC5615C 0 70 °COperating free-air temperature, T
A
TLC5615I 40 85 °C
over recommended operating free-air temperature range, V
DD
= 5V ±5%, V
ref
= 2.048V (unless otherwise noted)
STATIC DAC SPECIFICATIONS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 10 bitsIntegral nonlinearity, end point adjusted (INL) V
ref
= 2.048V, See
(1)
±1 LSBDifferential nonlinearity (DNL) V
ref
= 2.048V, See
(2)
±0.1 ±0.5 LSBE
ZS
Zero-scale error (offset error at zero scale) V
ref
= 2.048V, See
(3)
±3 LSBZero-scale-error temperature coefficient V
ref
= 2.048V, See
(4)
3 ppm/ °CE
G
Gain error V
ref
= 2.048V, See
(5)
±3 LSBGain-error temperature coefficient V
ref
= 2.048V, See
(6)
1 ppm/ °CZero scale 80PSRR Power-supply rejection ratio See
(7) (8)
dBGain 80Analog full scale output R
L
= 100k Ω2V
ref
(1023/1024) V
(1) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output fromthe line between zero and full scale excluding the effects of zero code and full-scale errors (see text). Tested from code 3 to code 1024.(2) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1LSBamplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant)as a change in the digital input code. Tested from code 3 to code 1024.(3) Zero-scale error is the deviation from zero-voltage output when the digital input code is zero (see text).(4) Zero-scale-error temperature coefficient is given by: E
ZS
TC = [E
ZS
(T
max
) – E
ZS
(T
min
)]/V
ref
×10
6
/(T
max
– T
min
).(5) Gain error is the deviation from the ideal output (V
ref
– 1LSB) with an output load of 10k Ωexcluding the effects of the zero-scale error.(6) Gain temperature coefficient is given by: E
G
TC = [E
G
(T
max
) – E
G
(T
min
)]/V
ref
×10
6
/(T
max
– T
min
).(7) Zero-scale-error rejection ratio (EZS-RR) is measured by varying the V
DD
from 4.5V to 5.5V dc and measuring the proportion of thissignal imposed on the zero-code output voltage.(8) Gain-error rejection ratio (EG-RR) is measured by varying the V
DD
from 4.5V to 5.5V dc and measuring the proportion of this signalimposed on the full-scale output voltage after subtracting the zero-scale change.
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VOLTAGE OUTPUT (OUT)
DIGITAL INPUT TIMING REQUIREMENTS (See Figure 1 )
OUTPUT SWITCHING CHARACTERISTICS
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
O
Voltage output range R
L
= 10k Ω0 V
DD
–0.4 VOutput load regulation accuracy V
O(OUT)
= 2V, R
L
= 2k Ω0.5 LSBI
OSC
Output short circuit current OUT to V
DD
or AGND 20 mAV
OL(low)
Output voltage, low-level I
O(OUT)
≤5mA 0.25 VV
OH(high)
Output voltage, high-level I
O(OUT)
≤– 5mA 4.75 V
REFERENCE INPUT (REFIN)
V
I
Input voltage 0 V
DD
–2 Vr
i
Input resistance 10 M ΩC
i
Input capacitance 5 pF
DIGITAL INPUTS (DIN, SCLK, CS)
V
IH
High-level digital input voltage 2.4 VV
IL
Low-level digital input voltage 0.8 VI
IH
High-level digital input current V
I
= V
DD
±1µAI
IL
Low-level digital input current V
I
= 0 ±1µAC
i
Input capacitance 8 pF
DIGITAL OUTPUT (DOUT)
V
OH
Output voltage, high-level I
O
= –2mA V
DD
–1 VV
OL
Output voltage, low-level I
O
= 2mA 0.4 V
POWER SUPPLY
V
DD
Supply voltage 4.5 5 5.5 VV
DD
= 5.5V, No load,
V
ref
= 0 150 250 µAAll inputs = 0V or V
DDI
DD
Power supply current
V
DD
= 5.5V, No load,
V
ref
= 2.048V 230 350 µAAll inputs = 0V or V
DD
ANALOG OUTPUT DYNAMIC PERFORMANCE
V
ref
= 1V
PP
at 1kHz + 2.048Vdc,Signal-to-noise + distortion, S/(N+D) 60 dBcode = 11 1111 1111
(1)
(1) The limiting frequency value at 1V
PP
is determined by the output-amplifier slew rate.
PARAMETER MIN NOM MAX UNIT
t
su(DS)
Setup time, DIN before SCLK high 45 nst
h(DH)
Hold time, DIN valid after SCLK high 0 nst
su(CSS)
Setup time, CS low to SCLK high 1 nst
su(CS1)
Setup time, CS high to SCLK high 50 nst
h(CSH0)
Hold time, SCLK low to CS low 1 nst
h(CSH1)
Hold time, SCLK low to CS high 0 nst
w(CS)
Pulse duration, minimum chip select pulse width high 20 nst
w(CL)
Pulse duration, SCLK low 25 nst
w(CH)
Pulse duration, SCLK high 25 ns
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t
pd(DOUT)
Propagation delay time, DOUT C
L
= 50pF 50 ns
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OPERATING CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
over recommended operating free-air temperature range, V
DD
= 5V ±5%, V
ref
= 2.048V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG OUTPUT DYNAMIC PERFORMANCE
C
L
= 100pF,SR Output slew rate R
L
= 10k Ω, 0.3 0.5 V/ µsT
A
= +25 °CTo 0.5LSB,t
s
Output settling time C
L
= 100pF,
(1)
12.5 µsR
L
= 10k Ω,Glitch energy DIN = All 0s to all 1s 5 nV-s
REFERENCE INPUT (REFIN)
Reference feedthrough REFIN = 1V
PP
at 1kHz + 2.048Vdc
(2)
–80 dBReference input
REFIN = 0.2V
PP
+ 2.048Vdc 30 kHzbandwidth (f–3dB)
(1) Settling time is the time for the output signal to remain within ±0.5LSB of the final measured value for a digital input code change of 000hex to 3FF hex or 3FF hex to 000 hex.(2) Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V
ref
input = 2.048Vdc + 1V
pp
at 1kHz.
Figure 1. Timing Diagram
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TYPICAL CHARACTERISTICS
15
10
5
0
20
25
30
54.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3
VDD = 5 V
VREFIN = 2.048 V
TA = 25°C
- Output Source Current - mA
IO
VO - Output Pullup Voltage - V
8
6
2
0
0.1 0.2 0.4 0.6
- Output Sink Current - mA
10
14
16
0.8 1
4
12
18
20
0.3 0.5 0.7 0.9 1.1 1.2
VDD = 5 V
VREFIN = 2.048 V
TA = 25°C
IO
VO - Output Pulldown Voltage - V
80
- Supply Current -
200
280
240
160
120
40
0- 60 - 40 - 20 0 20 40 60 80 100 120 140
Aµ
t - Temperature - °C
VDD = 5 V
VREFIN = 2.048 V
TA = 25°C
IDD
1 100 1 k 10 k 100 k
G - Relative Gain - dB
4
2
0
- 2
- 4
- 6
- 8
- 10
- 12
- 14
VDD = 5 V
VREFIN = 0.2 VPP + 2.048 V dc
TA = 25°C
fI - Input Frequency - Hz
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
OUTPUT SINK CURRENT OUTPUT SOURCE CURRENTvs vsOUTPUT PULLDOWN VOLTAGE OUTPUT PULLUP VOLTAGE
Figure 2. Figure 3.
SUPPLY CURRENT V
REFIN
TO V
(OUT)
RELATIVE GAINvs vsTEMPERATURE INPUT FREQUENCY
Figure 4. Figure 5.
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40
50
1 k
Signal-To-Noise + Distortion - dB
70
30
Frequency - Hz
20
10
0
60
10 k 100 k 300 k
VDD = 5 V
TA = 25°C
VREFIN = 4 VPP
Differential Nonlinearity – LSB
–0.2
0.2
0.1
0
–0.05
0.15
0.05
–0.1
–0.15
Input Code
255 511 767 10230
Integral Nonlinearity – LSB
–0.6
Input Code
1
0
–0.2
255 511 767 10230
0.8
0.6
0.4
0.2
–0.4
–0.8
–1
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE + DISTORTION
vsINPUT FREQUENCY AT REFIN
Figure 6.
Figure 7. Differential Nonlinearity With Input Code
Figure 8. Integral Nonlinearity With Input Code
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APPLICATION INFORMATION
GENERAL FUNCTION
_
+
Resistor
String
DAC
5 V
0.1 µF
AGND VDD
OUT
REFIN
DIN SCLK CS DOUT
R
R
_
+
2ǒVREFINǓ1023
1024
2ǒVREFINǓ513
1024
2ǒVREFINǓ512
1024 +VREFIN
2ǒVREFINǓ511
1024
2ǒVREFINǓ1
1024
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
The TLC5615 uses a resistor string network buffered with an op amp in a fixed gain of 2 to convert 10-bit digitaldata to analog voltage levels (see functional block diagram and Figure 9 ). The output of the TLC5615 is thesame polarity as the reference input (see Table 1 ).
An internal circuit resets the DAC register to all zeros on power up.
Figure 9. TLC5615 Typical Operating Circuit
Table 1. Binary Code Table (0V to 2V
REFIN
Output)
,
Gain = 2
INPUT
(1)
OUTPUT
1111 1111 11(00)
: :
1000 0000 01(00)
1000 0000 00(00)
0111 1111 11(00)
: :
0000 0000 01(00)
0000 0000 00(00) 0 V
(1) A 10-bit data word with two bits below the LSB bit (sub-LSB) with 0 values must be written since the DAC input latch is 12 bits wide.
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BUFFER AMPLIFIER
EXTERNAL REFERENCE
LOGIC INTERFACE
SERIAL CLOCK AND UPDATE RATE
f(SCLK)max +1
twǒCHǓ)twǒCLǓ
tp(CS) +16 ǒtwǒCHǓ)twǒCLǓǓ)twǒCSǓ
SERIAL INTERFACE
10 Data Bits x x
12 Bits
MSB LSB 2 Extra (Sub-LSB) Bits
x = don’t care
10 Data Bits x x
16 Bits
MSB LSB 2 Extra (Sub-LSB) Bits
4 Upper Dummy Bits
x = don’t care
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2k Ωload with a 100pF loadcapacitance. Settling time is 12.5 µs typical to within 0.5LSB of final value.
The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore,the REFIN input resistance is 10M Ωand the REFIN input capacitance is typically 5pF independent of inputcode. The reference voltage determines the DAC full-scale output.
The logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achievesthe lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logiclevels.
Figure 1 shows the TLC5615 timing. The maximum serial clock rate is:
or approximately 14MHz. The digital update rate is limited by the chip-select period, which is:
and is equal to 820ns which is a 1.21MHz update rate. However, the DAC settling time to 10 bits of 12.5 µs limitsthe update rate to 80kHz for full-scale input step transitions.
When chip select ( CS) is low, the input data is read into a 16-bit shift register with the input data clocked in mostsignificant bit first. The rising edge of the SLCK input shifts the data into the input register.
The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot beclocked into the input register. All CS transitions should occur when the SCLK input is low.
If the daisy chain (cascading) function (see daisy-chaining devices section) is not used, a 12-bit input datasequence with the MSB first can be used as shown in Figure 10 :
Figure 10. 12-Bit Input Data Sequence
or 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first.
Figure 11. 16-Bit Input Data Sequence
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SCLK
DIN
CS
DOUT
TLC5615
SK
SO
I/O
SI
Microwire
Port
NOTE A: The DOUT -SI connection is not required for writing to
the TLC5615 but may be used for verifying data
transfer if desired.
SCLK
DIN
CS
DOUT
TLC5615
SCK
MOSI
I/O
MISO
SPI/QSPI
Port
NOTE A: The DOUT -MISO connection is not required for writing to the
TLC5615 but may be used for verifying data transfer.
CPOL = 0, CPHA = 0
DAISY-CHAINING DEVICES
LINEARITY, OFFSET, AND GAIN ERROR USING SINGLE-ENDED SUPPLIES
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
The data from DOUT requires 16 falling edges of the input clock and, therefore, requires an extra clock width.When daisy chaining multiple TLC5615 devices, the data requires 4 upper dummy bits because the data transferrequires 16 input-clock cycles plus one additional input-clock falling edge to clock out the data at the DOUTterminal (see Figure 1).
The two extra (sub-LSB) bits are always required to provide hardware and software compatibility with 12-bit dataconverter transfers.
The TLC5615 three-wire interface is compatible with the SPI, QSPI, and Microwire serial standards. Thehardware connections are shown in Figure 12 and Figure 13.
The SPI and Microwire interfaces transfer data in 8-bit bytes; therefore, two write cycles are required to inputdata to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DACinput register in one write cycle.
Figure 12. Microwire Connection
Figure 13. SPI/QSPI Connection
DACs can be daisy-chained by connecting the DOUT terminal of one device to the DIN of the next device in thechain, providing that the setup time, t
su(CSS)
( CS low to SCLK high), is greater than the sum of the setup time,t
su(DS)
, plus the propagation delay time, t
pd(DOUT)
, for proper timing (see digital input timing requirements section).The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. DOUT is a totem-poledoutput for low power. DOUT changes on the SCLK falling edge when CS is low. When CS is high, DOUTremains at the value of the last data bit and does not go into a high-impedance state.
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative.With a positive offset, the output voltage changes on the first code change. With a negative offset the outputvoltage may not change with the first code depending on the magnitude of the offset voltage.
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DAC Code
Output
Voltage
0 V
Negative
Offset
POWER-SUPPLY BYPASSING AND GROUND MANAGEMENT
0.1 µF
Analog Ground Plane
1
2
3
4
8
7
6
5
SAVING POWER
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
The output amplifier attempts to drive the output to a negative voltage. However, because the most negativesupply rail is ground, the output cannot drive below ground and clamps the output at 0V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltageto overcome the negative offset voltage, resulting in the transfer function shown in Figure 14 .
Figure 14. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed thedotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs '0') and full-scale code (all inputs '1') afteroffset and full scale are adjusted out or accounted for in some way. However, single supply operation does notallow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity ismeasured between full-scale code and the lowest code that produces a positive output voltage. For theTLC5615, the zero-scale (offset) error is ±3LSB maximum. The code is calculated from the maximumspecification for the negative offset.
Printed circuit boards that use separate analog and digital ground planes offer the best system performance.Wire-wrap boards do not perform well and should not be used. The two ground planes should be connectedtogether at the low-impedance power-supply source. The best ground connection may be achieved byconnecting the DAC AGND terminal to the system analog ground plane making sure that analog ground currentsare well managed and there are negligible voltage drops across the ground plane.
A 0.1 µF ceramic-capacitor bypass should be connected between V
DD
and AGND and mounted with short leadsas close as possible to the device. Use of ferrite beads may further isolate the system analog supply from thedigital power supply.
Figure 15 shows the ground plane layout and bypassing technique.
Figure 15. Power-Supply Bypassing
Setting the DAC register to all 0s minimizes power consumption by the reference resistor array and the outputload when the system is not using the DAC.
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AC CONSIDERATIONS
Digital Feedthrough
Analog Feedthrough
TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
Even with CS high, high-speed serial data at any of the digital input or output terminals may couple through theDAC package internal stray capacitance and appear at the DAC analog output as digital feedthrough. Digitalfeedthrough is tested by holding CS high and transmitting 0101010101 from DIN to DOUT.
Higher frequency analog input signals may couple to the output through internal stray capacitance. Analogfeedthrough is tested by holding CS high, setting the DAC code to all 0s, sweeping the frequency applied toREFIN, and monitoring the DAC output.
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TLC5615C , TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from D Revision (August 2003) to E Revision ............................................................................................... Page
•Added ESD statement. ......................................................................................................................................................... 2•Changed —moved package option table from front page. ................................................................................................... 2
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PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC5615CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5615CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5615CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TLC5615CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TLC5615CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TLC5615CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TLC5615CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5615CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5615CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC5615CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC5615ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5615IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5615IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TLC5615IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TLC5615IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5615IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5615IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC5615IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC5615CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLC5615CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC5615CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC5615IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC5615IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC5615CDGKR VSSOP DGK 8 2500 367.0 367.0 35.0
TLC5615CDR SOIC D 8 2500 367.0 367.0 35.0
TLC5615CDR SOIC D 8 2500 340.5 338.1 20.6
TLC5615IDR SOIC D 8 2500 340.5 338.1 20.6
TLC5615IDR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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