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to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
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Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
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© 2005 Fairchild Semiconductor Corporation DS005367 www.fairchildsemi.com
Februa ry 198 4
Revised May 2005
MM74HCT373 • MM74HCT374 3-STATE Octal D-Type Latch • 3-STATE Oct al D-Type Flip-Flop
MM74HCT373 MM74HCT374
3-STATE Octal D-Type Latch
3-STATE Octal D-Type Flip-Flop
General Descript ion
The MM74HCT373 octal D-type latches and
MM74HCT374 Octal D-type flip flops advanced silicon-gate
CMOS techno logy, which provid es the inherent b enefits of
low power co nsumpti on and wide po wer supp ly range, but
are LS- TTL input and output char acteristic & p in-out com -
patible. The 3-STATE outputs are capable of driving 15 LS-
TTL loads. All inputs are protected from damage due to
static discharge by internal diodes to VCC and ground.
When the MM74HCT373 LATCH ENABLE input is HIGH,
the Q outputs will follow the D inputs. When the LATCH
ENABLE goes LOW, data at the D inputs will be retained at
the outputs until LATCH ENABLE returns HIGH again.
When a high logic level is applied to the OUTPUT CON-
TROL input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs
and the state of the storage elements.
The MM74HCT374 are positive edge triggered flip-flops.
Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on po sitive
going transitions of the CLOCK (CK) input. When a high
logic level is applied to the OUTPUT CONTROL (OC)
input, a ll outputs go to a high impeda nce state, reg ardless
of what signals are present at the other inputs and the state
of the storage elements.
MM74HCT devices ar e intended to interfa ce betwe en TTL
and NMOS components and standard CMOS devices.
These parts are also plug in replacements for LS-TTL
devices and can be used to red uce power consump tion in
existing designs.
Features
TTL input characteristic compatible
Typical propagation delay: 20 ns
Low input current: 1
P
A maximum
Low quiescent current: 80
P
A maximum
Compatible with bus-oriented systems
Output drive capability: 15 LS-TTL loads
Ordering Code:
Devices also available in Tape and R eel. Sp ec if y by appending the suffix lett er “X” to the orde ring code.
Order Number Package Number Package Descriptions
MM74HCT373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HCT373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74HCT374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HCT374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT374MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
www.fairchildsemi.com 2
MM74HCT373 MM74HCT374
Connection Diagrams
Top View
MM74HCT373 Top View
MM74HCT374
Truth Tables
MM74HCT373
H
HIGH Level
L
LOW Level
Q0
Level of output before steady- state input conditions were esta blished.
Z
High Impedance
MM74HCT374
H
HIG H L e vel
L
LOW Le vel
X
Don’t Ca re
n
Transi tion from LOW-to-HIGH
Z
High Impedance State
Q0
The level of the output before steady state input conditions were
established.
Output LE Data 373
Control Output
LHHH
LHLL
LLXQ
0
HXXZ
Output Clock Data Output
Control (374)
L
n
HH
L
n
LL
LLXQ
0
HXXZ
3 www.fairchildsemi.com
MM74HCT373 MM74HCT374
Logic Diagrams
MM74HCT373
MM74HCT374
www.fairchildsemi.com 4
MM74HCT373 MM74HCT374
Absolute Maximum Ratings(No t e 1)
(Note 2) Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings a re those va lues beyon d which d am-
age to the device may occur.
Note 2: Unless ot herwise sp ec ified all vo ltages ar e referenc ed to ground.
Note 3: Power Dis sipation temp erature de rating plastic N package:
12 mW/
q
C from 65
q
C to 85
q
C.
DC Electrical Characteristics
VCC
5V
r
10% (unless otherwise specified)
Note 4: Measured per pin. Al l ot hers tied to VCC or ground.
Supply Voltage (VCC)
0.5 to
7.0V
DC Input Voltage (VIN)
1.5 to VCC
1.5V
DC Output Voltage (VOUT)
0.5 to VCC
0.5V
Clamp Diode Current (IIK, IOK)
r
20 mA
DC Output Current, per pin (IOUT)
r
35 mA
DC VCC or GND Current, per pin (ICC)
r
70 mA
Storage Temperature Range (TSTG)
65
q
C to
150
q
C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering 10 seconds) 260
q
C
Min Max Units
Supply Voltage (VCC)4.55.5V
DC Input or Output V oltage 0 VCC V
(VIN, VOUT)
Operating Temperature Range (TA)
40
85
q
C
Input Rise or Fall Times
(tr, tf) 500 ns
Symbol Parameter Conditions TA
25
q
CT
A
40 to 85
q
CT
A
55 to 125
q
CUnits
Typ Guaranteed Limits
VIH Minimum HIGH Level 2.0 2.0 2.0 V
Input Voltage
VIL Maximum LOW Level 0.8 0.8 0.8 V
Input Voltage
VOH Minimum HIGH Level VIN
VIH or VIL
Output Voltage |IOUT|
20
P
AV
CC VCC
0.1 VCC
0.1 VCC
0.1 V
|IOUT|
6.0 mA, VCC
4.5V 4.2 3.98 3.84 3.7 V
|IOUT|
7.2 mA, VCC
5.5V 5.7 4.98 4.84 4.7 V
VOL Maximum LOW Level VIN
VIH or VIL
Voltage |IOUT|
20
P
A 0 0.1 0.1 0.1 V
|IOUT|
6.0 mA, VCC
4.5V 0.2 0.26 0.33 0.4 V
|IOUT|
7.2 mA, VCC
5.5V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN
VCC or GND,
r
0.1
r
1.0
r
1.0
P
A
Current VIH or VIL
IOZ Maximum 3-STATE VOUT
VCC or GND
Output Leakage Enable
VIH or VIL
r
0.5
r
5.0
r
10
P
A
Current
ICC Maximum Quiescent VIN
VCC or GND 8.0 80 160
P
A
Supply Current IOUT
0
P
A
VIN
2.4V or 0.5V (Note 4) 1.0 1.3 1.5 mA
5 www.fairchildsemi.com
MM74HCT373 MM74HCT374
AC Electrical Characteristics
MM74HCT373: VCC
5.0V, tr
tf
6 ns TA
25
q
C (unless otherwise specified)
AC Electrical Characteristics
MM74HCT373: VCC
5.0V
r
10%, tr
tf
6 ns (unless otherwise specified)
Note 5: CPD determines the no load dynamic power consumption, PD
CPD VCC2 f
ICC VCC, and th e no load dyna m ic c urrent cons um ption,
IS
CPD VCC f
ICC.
Symbol Parameter Conditions Typ Guaranteed Units
Limit
tPHL, tPLH Maximum Propagation Delay CL
45 pF 18 25 ns
Data to Output
tPHL, tPLH Maximum Propagation Delay CL
45 pF 21 30 ns
Latch Enable to Output
tPZH, tPZL Maximum Enable Propagation Delay CL
45 pF 20 28 ns
Control to Output RL
1 k
:
tPHZ, tPLZ Maximum Disable Propagation Delay CL
5 pF 18 25 ns
Control to Output RL
1 k
:
tWMinimum Clock Pulse Width 16 ns
tSMinimum Setup Time Data to Clock 5 ns
tHMinimum Hold Time Clock to Data 10 ns
Symbol Parameter Conditions TA
25
q
CT
A
40 to 85
q
CT
A
55 to 125
q
CUnits
Typ Guar ant eed Lim i ts
tPHL, tPLH Maximum Propagation CL
50 pF 22 30 37 45 ns
Delay Data to Output CL
150 pF 30 40 50 60 ns
tPHL, tPLH Maximum Propagation Delay CL
50 pF 25 35 44 53 ns
Latch Enable to Output CL
150 pF 32 45 56 68 ns
tPZH, tPZL Maximum E nable Propagation CL
50 pF 21 30 37 45 ns
Delay Control to Output CL
150 pF 30 40 50 60 ns
RL
1 k
:
tPHZ, tPLZ Maximum Disable Propagation CL
50 pF 21 30 37 45 ns
Delay Control to Output RL
1 k
:
tTHL, tTLH Maximum Output Rise CL
50 pF 8 12 15 18 ns
and Fall Time
tWMinimum Clock Pulse Width 16 2 0 24 ns
tSMini mum Setup Time Data to Cloc k 5 6 8 ns
tHMinimum Hold Time Clock to Data 10 13 20 ns
CIN Maximum Input Capacitance 10 10 10 pF
COUT Maximum Output Capacitance 20 20 20 pF
CPD Power Dissipation Capacitance OC
VCC 5pF
(Note 5) OC
GND 52 pF
www.fairchildsemi.com 6
MM74HCT373 MM74HCT374
AC Electrical Characteristics
MM74HCT374: VCC
5.0V, tr
tf
6 ns TA
25
q
C (unless otherwise specified)
AC Electrical Characteristics
MM74HCT374: VCC
5.0V
r
10%, tr
tf
6 ns (unless otherwise specified)
Note 6: CPD determines t he no load pow er consum pt ion, PD
CPD VCC2 f
ICC VCC, and th e no load dyna m ic c urrent cons um ption, IS
CPD VCC f
ICC.
Symbol Parameter Conditions Typ Guaranteed Units
Limit
fMAX Maximum Clock Frequency 50 30 MHz
tPHL, tPLH Maximum Propagation Delay CL
45 pF 20 32 ns
to Output
tPZH, tPZL Maximum Enable Propagation Delay CL
45 pF 19 28 ns
Control to Output RL
1 k
:
tPHZ, tPLZ Maximum Disable Propagation Delay CL
5 pF 17 25 ns
Control to Output RL
1 k
:
tWMinimum Clock Pulse Width 20 ns
tSMinimum Setup Time Data to Clock 5 ns
tHMinimum Hold Tim e Clock to Data 16 ns
Symbol Parameter Conditions TA
25
q
CT
A
40 to 85
q
CT
A
55 to 125
q
CUnits
Typ Guaranteed Limits
fMAX Maximum Clock Frequency 30 24 20 MHz
tPHL, tPLH Maximum Propagation Delay CL
50 pF 22 36 45 48 ns
to Output CL
150 pF 30 46 57 69 ns
tPZH, tPZL Maximum Enable Propagation CL
50 pF 21 30 37 45 ns
Delay Control to Output CL
150 pF 30 40 50 60 ns
RL
1 k
:
tPHZ, tPLZ Maximum Disable Propagation CL
50 pF 21 30 37 45 ns
Delay Control to Output RL
1 k
:
tTHL, tTLH Maximum Output Rise CL
50 pF 8 12 15 18 ns
and Fall Time
tWMinimum Clock Pulse Width 16 20 24 ns
tSMinimum Setup Time Data to Clock 20 25 30 ns
tHMinimum Hold Time Clock to Data 5 5 5 ns
CIN Maximum Input Capacitance 10 10 10 pF
COUT Maximum Output Capacitance 20 20 20 pF
CPD Power Dissipation Capa citance OC
VCC 5pF
(Note 6) OC
GND 58 pF
7 www.fairchildsemi.com
MM74HCT373 MM74HCT374
Physical Dim ensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
www.fairchildsemi.com 8
MM74HCT373 MM74HCT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP ), EIAJ TYPE II, 5.3mm W ide
Package Number M20D
9 www.fairchildsemi.com
MM74HCT373 MM74HCT374
Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)
20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP), JED EC MO-1 53, 4.4mm Wide
Package Number MTC20
www.fairchildsemi.com 10
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent in any componen t of a life support
device or system whose failure to perform can be rea-
sonabl y ex pect ed to cause the fa ilu re of the lif e su pp ort
device or system, or to affect it s safety or effectiveness.
www.fairchildsemi.com
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/PatentMarking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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