NCV7608
http://onsemi.com
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independently of the input state (serial or parallel).
Overtemperature shutdown is a latched event.
Since thermal warning precedes an overtemperature
shutdown, software polling of this bit will allow for load
control and possible prevention of overtemperature
shutdown conditions.
Thermal Warning Retrieval
Thermal warning information can be retrieved
immediately without performing a complete SPI access
cycle. Figure 26 below displays how this is accomplished.
Bringing the CSB pin from a 1 to a 0 condition immediately
displays the information on the output data bit 0, thermal
warning, even in the absence of a SCLK signal. As the
temperature of the NCV7608 changes from a condition from
below the thermal warning threshold to above the thermal
warning threshold, the state of the SO pin changes and this
level is available immediately when the CSB goes to 0. A 0
on SO indicates there is no thermal warning, while a 1
indicates the IC is above the thermal warning threshold.
Figure 26. Accessing Thermal Warning Bit
Power Supply Monitoring
Undervoltage shutdown
Both supply voltages (VCC and VS) are monitored for
undervoltage. When VCC goes below the threshold, all
outputs are turned OFF and the input and output registers are
cleared. An undervoltage condition on VS will cause all
channels to shut down. The fault bit (Bit #15) is latched in
the Output Data Register. The channels will return to the
commanded status after reaching operational VS levels
provided VCC UVLO is not breached. The SPI port remains
active during VS undervoltage within a valid VCC voltage.
Drivers are guaranteed to operate with automotive cranking
voltages down to 3 V on VS per the undervoltage shutdown
thresholds. Bit# 15 is cleared with a valid SPI frame and VS
within the operating limits.
Overvoltage shutdown
VS is continuously monitored for overvoltage conditions.
The threshold is set above automotive jump start conditions
allowing operation of the IC during jump start. The
minimum overvoltage threshold is 32 V. When VS goes
above the overvoltage threshold voltage, all outputs are
turned OFF. The fault bit (Bit #15) is latched in the Output
Data Register. Input and output registers maintain all
information. The channels will return to the commanded
status after reaching operational VS levels provided VCC
UVLO is not breached. The SPI port remains active during
VS overvoltage within a valid VCC voltage. Bit #15 is
cleared with any valid SPI frame and VS within the
operating limits.
OFF−Mode Open Load Diagnostics
Open load diagnostics are performed when the drivers are
off (provided the channel is programmed to perform the
operation via Bits #8 through #15). Open load diagnostics
are performed by connecting two tracking current sources
(IDIAGHSx and IDIAGLSx) to the corresponding outputs.
To support both operation modes (high−side and low−side)
and provide minimum delay due to external capacitances,
both Drain and Source pin voltages of the device are
monitored to generate the diagnostic information. Channel
diagnostic information is directed to the output data register.
Open load diagnostics are disabled during VS undervoltage
or overvoltage events or when EN is low.
Figure 27 shows the NCV7608 open load diagnostics
principles.
Figure 28 shows the internal circuitry used with the device
set up as a low−side driver.
Figure 29 shows the internal circuitry used with the device
set up as a high−side driver.