792
6384E–ATARM–05-Feb-10
AT91SAM9G20
Notes: 1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or 5 or 7
(Receive Start Selection), two periods of the MCK must be added to timings.
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or
RK) edge and the signal change. The Max access timing is the time between the TK edge and the signal stabilization. Figure
41-20 illustrates Min and Max accesses for SSC0. The same appliess for SSC1, SSC4, and SSC7, SSC10 and SSC13.
Table 41-41. SSC Timings
Symbol Parameter Conditions Min Max Units
Transmitter
SSC0TK edge to TF/TD (TK output, TF output)
MAX corner, VDDIO = 1.8V -3.2 ((2) 4.2 (2) ns
MAX corner, VDDIO = 3.3V -2.7 (2) 3.7 (2) ns
SSC1TK edge to TF/TD (TK input, TF output)
MAX corner, VDDIO = 1.8V -3.2 (2) 4.2 (2) ns
MAX corner, VDDIO = 3.3V -2.7 (2) 3.7 (2) ns
SSC2TF setup time before TK edge (TK output)
MAX corner, VDDIO = 1.8V 21.2 - tCPMCK ns
MAX corner, VDDIO = 3.3V 15.5 - tCPMCK ns
SSC3TF hold time after TK edge (TK output)
MAX corner, VDDIO = 1.8V tCPMCK - 13.4 ns
MAX corner, VDDIO = 3.3V tCPMCK - 9.5 ns
SSC4 (1) TK edge to TF/TD (TK output, TF input)
MAX corner, VDDIO = 1.8V -3.1(1)(2) 2 * tCPMCK +
4.3 (1)(2) ns
MAX corner, VDDIO = 3.3V -2.6(1)(2) 2 * tCPMCK +
3.8 (1)(2) ns
SSC5TF setup time before TK edge (TK input)
MAX corner, VDDIO = 1.8V 7.4 - tCPMCK ns
MAX corner, VDDIO = 3.3V 6.0 - tCPMCK ns
SSC6TF hold time after TK edge (TK input)
MAX corner, VDDIO = 1.8V tCPMCK - 0.7 ns
MAX corner, VDDIO = 3.3V tCPMCK - 2.0 ns
SSC7(1) TK edge to TF/TD (TK input, TF input)
MAX corner, VDDIO = 1.8V 11.6(1) 3 * tCPMCK +
17.0(1) ns
MAX corner, VDDIO = 3.3V 7.7(1) 3 * tCPMCK +
11.3(1) ns
Receiver
SSC8RF/RD setup time before RK edge (RK input)
MAX corner, VDDIO = 1.8V 7.4 - tCPMCK ns
MAX corner, VDDIO = 3.3V 6.2 - tCPMCK ns
SSC9RF/RD hold time after RK edge (RK input)
MAX corner, VDDIO = 1.8V tCPMCK +7.4 ns
MAX corner, VDDIO = 3.3V tCPMCK +6.1 ns
SSC10 RK edge to RF (RK input)
MAX corner, VDDIO = 1.8V 11.3(2) 22.3(2) ns
MAX corner, VDDIO = 3.3V 7.3(2) 16.5(2) ns
SSC11 RF/RD setup time before RK edge (RK output)
MAX corner, VDDIO = 1.8V 21.6 - tCPMCK ns
MAX corner, VDDIO = 3.3V 15.9 - tCPMCK ns
SSC12 RF/RD hold time after RK edge (RK output)
MAX corner, VDDIO = 1.8V tCPMCK - 10.5 ns
MAX corner, VDDIO = 3.3V tCPMCK - 6.5 ns
SSC13 RK edge to RF (RK output)
MAX corner, VDDIO = 1.8V -3.2(2) ns
MAX corner, VDDIO = 3.3V -2.8(2) ns