M36P0R9070E0ZACE - STMicroelectronics

PRELIMINARY DATA

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without noti ce.

Rev. 1

November 2005 1/26

M36P0R9070E0

512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory

128 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package

Features summary

■Multi-chip package

– 1die of 512 Mbit (32Mb x 16, Multiple Bank,

Multi-Level, Burst) Flash Memory

–1 die of 128Mbit (8Mb x16) PSRAM

■Supply voltage

–V

DDF = VCCP = VDDQ = 1.7 to 1.95V

–V

PPF = 9V for fast program (12V tolerant)

■Electronic signature

– Manufacturer Code: 20h

– Device Code: 8819

■Package

–ECOPACK®

Flash memory

■Synchronous / asynchronous read

– Synchronous Burst Read mode :

108MHz, 66MHz

– Asynchronous Page Read mode

– Random Access: 93ns

■Programming time

– 4µs typical W ord progr am time using Buff er

Enhanced Factory Program command

■Memory organization

– Multiple Bank Memory Array: 64 Mbit

Banks

– F our Extended Fl ash Arr a y (EFA) Blocks of

64 Kbits

■Dual operations

– program/erase in one Bank while re ad in

others

– No delay between read and write

operations

■Security

– 2112-bit user programmable OTP Cells

– 64-bit unique device number

■100,000 progr am/erase cycles per block

■Block locking

– All Blocks locked at power-up

– Any combination of Blocks can be locked

with zero latency

–WP

F for Block Lock-Down

– Absolute Write Protection with VPPF = VSS

■Common Flash Interface (CFI)

PSRAM

■Access time: 70ns

■ Asynchronous Page Read

– Page Size: 4, 8 or 16 Words

– Subsequent read within page: 20ns

■ Low power features

– Partial Array Self Refresh (PASR)

– Deep Power-Down mode (DPD)

■ Synchronous Burst Read/Write

TFBGA107 (ZAC)

FBGA

www.st.com

M36P0R9070E0

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Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Address inputs (A0-A24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.5 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6 Flash Chip Enable input (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.7 Flash Output Enable inputs (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.8 Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.9 Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.10 Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.11 PSRAM Chip Enable input (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.12 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.13 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.14 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.15 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.16 PSRAM Configuration Register Enable (CRP) . . . . . . . . . . . . . . . . . . . . . . . 11

2.17 Deep Power-Down input (DPDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.18 VDDF Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.19 VCCP Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.20 VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.21 VPPF Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.22 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

M36P0R9070E0

3/26

6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

M36P0R9070E0

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List of tables

Table 1. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Flash Memory DC Characteristics - Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Flash Memory DC Characteristics - Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1

Table 10. Stacked TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitch, packag e da ta. . . . . . 23

Table 11. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

M36P0R9070E0

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List of figures

Figure 1. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3. AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5. TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitc h, package outline. . . . . . . . . . . 22

1 Summar y description M36P0R9070E0

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1 Summary description

The M36P0R9070E0 combin es two memory devices in one Multi-Chip Package:

●512-Mbit Multiple Bank Flash memory (the M58PR512J).

●128 Mbit PSRAM (the M69KB128AA).

This datasheet should be read in con junction with the M58PR512J and M69KB128AA

datasheets, which are available from www.st.com.

Recommended operating conditions do not allow more than one memory to be active at t he

same time.

The memory is offered in a Stacked TFBGA107 package. It is supplied with all the bi ts erased

(set to ‘1’).

Table 1. Logic Diagram

AI10845

A0-A24

DQ0-DQ15

VDDQ

M36P0R9070E0

VSS

RPF

WPF

VDDF

DPDF

UBP

LBP

VPPF

VCCP

CRP

WAIT

M36P0R9070E0 1 Summary description

7/26

Table 2. Signal Names

Note: 1 A23-A24 are Addre ss Inputs for the Flash memory component only.

A0-A24(1) Address Inputs

DQ0-DQ15 Common Data Input/Output

VDDQ Common Flash and PSRAM Power Supply for I/O Buffers

VPPF Flash Memory Optional Supply Voltage for Fast Program & Erase

VDDF Flash Memory Power Supply

VCCP PSRAM Power Supply

VSS Ground

LLatch Enable input

K Burst Clock

WAIT Wait Output

NC Not Connected Internally

DU Do Not Use as Internal ly Connected

Flash Memory

EFChip Enable input

GFOutput Enable Input

WFWrite Enable input

RPFReset input

WPFWrite Protect input

DPDFDeep Power-Down

PSRAM

EPChip Enable Input

GPOutput Enable Input

WP Write Enable Input

CRP Configuration Register Enable Input

UBP Upper Byte Enable Input

LBP Lower Byte Enable Input

1 Summar y description M36P0R9070E0

8/26

Figure 1. TFBGA Connections (Top view thr ough package)

AI11098

DQ14

DQ0

A16

WAIT

DQ13

DQ8

HDQ7

A17

A22

BA21

87654321

A11

WPA13

A12

JDQ15

VSS

DQ6

DQ12

DQ4

DQ10

VSS

VPP

A18 VSS

DQ11

DQ1

A23

A24

A19

DQ9

A14

A20

VDDF

DQ3

DQ5

DQ2

DU DU DU DU

NC NC

NC VCCP DPDFVSS

VSS

VDDQ

LBP

EPA9

WPFA10 A15

UBPRPFWF

NC EF

VCCP VDDQ CRP

VSS VDDQ VDDF VSS VSS VSS VSS

M36P0R9070E0 2 Signal descriptions

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2 Signal descriptions

See Table 1., Logic Diagram and Table 2., Signal Names, for a brief overview of the signals

connected to this device.

2.1 Address inputs (A0-A24)

Addresses A0-A22 are common inputs for the Flash memory and PSRAM components.

Addresses A23 and A24 are inputs for Flash mem ory components only. The Address Inputs

select the cells in the memory array to access during Bus Read operations. During Bus Write

operations they control the commands sent to the Command Interface of the internal state

machine. The Flash memory is accessed th rough the Chip Enab le signal (EF) and through the

Write Enable signal (WF), while the PSRAM is accessed through the Chip Enable signal (EP)

and the Wr ite Enable signal (WP).

EF Low, and EP must not be Low at the same time.

2.2 Data input/output (DQ0-DQ15)

The Data I/O output the data stored at the selected address during a Bus Read operation or

input a command or the data to be programmed during a Bus Write operation.

F or the PSRAM com ponent, the u pper Byte Data Inputs/Outpu ts (DQ8-DQ15 ) carry the data to

or from the upper part of the selected address when Upper Byte Enable (UBP) is driven Low.

The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the lower part of the

selected address when Lower Byte Enable (LBP) is driven Low. When both UBP and LBP are

disabled, the Data Inputs/ Outputs are high impedance.

2.3 Latch Enable (L)

The Latch Enable pin is common to the Flash memory and PSRAM components.

For details of how the Latch Enable signal behave s, please refer to the datasheets of the

respective memory components: M69KB128AA for the PSRAM and M58PR512J for the Flash

memory.

2.4 Clock (K)

The Clock input pin is common to the Flash memory and PSRAM components.

For details of how the Clock signal behaves, please refer to t he datasheets of the re spectiv e

memory components: M69KB128AA for the PSRAM and M58PR512J for the Flash memory.

2 Signal descriptions M36P0R9070E0

10/26

2.5 Wait (WAIT)

WAIT is an output pin common to the Flash memory and PSRAM components. However the

WAIT signal does not behave in the same way for the PSRAM and the Flash mem ory.

For details of how it behaves, please refer to the M69KB128AA datasheet for the PSRAM and

to the M58PR512J datasheet for the Flash memory.

2.6 Flash Chip Enable input (EF)

The Flash Chip Enable input activates the control logic, input buffers, decoders and sense

amplifiers of t he Flas h memory component selected . Wh en Chip Enab le is Low, VIL, and Reset

is High, VIH, the device is in active mode. When Chip Enable is at VIH the corresponding Flash

memory are deselected, the outputs are high impedance and the power consumption is

reduced to the stan dby level.

It is not allow ed to ha v e EF at VIL and EP at VIL at t he same ti me. Only one me mory component

can be enabled at a time.

2.7 Flash Output Enable inputs (GF)

The Output Enable pins control the data outputs during Flash memory Bus Read operations.

2.8 Flash Write Enable (WF)

The Write Enable controls the Bus Write operation of the Flash memory Command Interface.

The data and address inputs are latched on the rising edge of Chip Enable or Write Enable

whichever occurs first.

2.9 Flash Write Protect (WPF)

Write Prote ct is an input th at gives an additional ha rdware prot ec tio n for each block. When

Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down

blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the

Loc ke d-Do wn b loc ks can be loc ked or unloc k ed. (See the Loc k Status Table in the M58PR512J

datasheet).

2.10 Flash Reset (RPF)

The Reset input provides a hardware reset of the Flash memories. When Reset is at VIL, the

memory is in Reset mode: the outputs are high impedance and the current consumption is

reduced to the Reset Supply Current IDD2. Ref er to Table 7., Flash Memory DC Characte ristics

- Currents, for the value of IDD2. After Reset all bloc ks are in the Locked state and the

Configur ation Register is reset. When Reset i s at VIH, the device is in normal operation. Exit ing

Reset mode the device enters Asynchronous Read mode, b ut a negative transition of Chip

Enable or Latch Enable is required to ensure valid data outputs.

M36P0R9070E0 2 Signal descriptions

11/26

The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to

VRPH (refer to Table 8., Flash Memory DC Characteristics - Voltages).

2.11 PSRAM Chip Enable input (EP)

The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted

(VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep

Power-down mode.

2.12 PSRAM Write Enable (W P)

Write Enable, WP

, controls the Bus Write operation of the PSRAM. When asserted (VIL), the

device is in Write mode and Write operations can be per formed either to the configuration

registers or to the memory array.

2.13 PSRAM Output Enable (GP)

Output Enable, GP

, provides a high speed tri-state control, allo wing fast read/write cycles to be

achieved with the common I/O data bus.

2.14 PSRAM Upper Byte Enable (UBP)

The Upper Byte En-able, UBP

, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-

DQ15) to or from the upper part of the selected address during a Write or Read operation.

2.15 PSRAM Lower Byte Enable (LBP)

The Lower Byte Enable, LBP

, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-

DQ7) to or from the lower part of the selected address during a Write or Read operation.

If both LBP and UBP are disabled (High) during an operation, the device will disable the data

bu s from receiving or transmitting data. Although the device will seem to be deselected, it

remains in an active mode as long as EP remain s Low.

2.16 PSRAM Configuration Register Enable (CRP)

When this signal is driven High, VIH, Write operations load either the value of the Refresh

Configuration Register (RCR) or the Bus configuration register (BCR).

2 Signal descriptions M36P0R9070E0

12/26

2.17 Deep Power-Down input (DPDF)

The Deep Power-Down input is used to place the device in a Deep Power-Down mode.When

the device is in Deep Power-Down mode, the memory cannot be modified and data is

protected.

For further details on how the Deep Power-Down input signal works, please refer to the

M58PR512J datasheet.

2.18 VDDF Supply Voltages

VDDF prov ides the po w er supply to the internal cores of the Flash memory. It is the main power

supply for all Flash memory operations (Read, Program and Erase).

2.19 VCCP Supply Voltage

VCCP pro vides th e power supply to th e int ernal core of the PSRAM device. It is the main po w er

supply for all PSRAM operations.

2.20 VDDQ Supply Voltage

VDDQ provides the power supply f or the Flash memory and PSRAM I/O pins. This allows all

Outputs to be powered independently of the Flash memory and SRAM core power supplies,

VDDF and VCCP

2.21 VPPF Program Supply Vo ltag e

VPPF is both a control inp ut and a po wer supply pin f or th e Flash memory. The tw o functions a re

selected by the voltage range applied to the pin.

If VPPF is kept in a low voltage r ange (0V to VDDQ) VPPF is seen as a control input. In this case

a voltage lower than VPPLK gives an absolute protection against Program or Erase, while VPPF

> VPP1 enables these functions (see Tables 7 and 8, Flash Memory DC Characte ristics f or the

relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in it s

v alue after the operation has started does n ot hav e any eff ect and Prog ram or Er ase oper ations

continue.

If VPPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be

stable until the Program/Erase algorithm is completed.

M36P0R9070E0 2 Signal descriptions

13/26

2.22 VSS Ground

VSS is the common ground reference for all voltage measurements in the Flash (core and I/O

Buffers) and PSRAM chips. It must be connected to the system ground.

Note: Each Flash memory device in a syste m should have their supply voltage (VDDF) and the

program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high

frequency, inher ently low inductance capacitors sh ould be as close as possible to the p ackage).

See Figure 4., AC Measurement Load Circuit. The PCB track widths should be sufficient to

carry the required VPPF program and erase currents.

3 Functional description M36P0R9070E0

14/26

3 Functional description

The PSRAM and Flash memory components ha ve separ ate pow er supplies but share the same

ground s. They are distinguished by two Chip Enable inputs: EF for Flash and EP for the

PSRAM.

Recommended operating conditions do not allow more than one device to be active at a time.

The most common example is a simultaneous read operations on the Flash memory and the

PSRAM which would result in a data bus contention. Therefore it is recommended to put the

other devices in the high impedance state when reading the selected device.

Figure 2. Functional Block Diagram

Ai11731

CRP

A0-A22

128Mbit

PSRAM

UBP

LBP

WAIT

KVDDQ

VSS

VCCP

512 Mbit

Flash

Memory

VDDF

RPF

WPF

VPPF

A23-A24

DQ0-DQ15

DPDF

M36P0R9070E0 3 Functional description

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Table 3. Main Operating Modes

Note: 1 X = Don't care

F can be tied to VIH if the v alid address has been previously latched

3 Depends on GF

4WAIT

F signal polarity is configured using the Set Configuration Register command. See the

M58PR512J datasheet for details.

Operation EF GFWFLFRPFWAITF(4) EPCRPGPWPLBP,UBPDQ15-DQ0

Flash Read VIL VIL VIH VIL(2) VIH PSRAM must be disabled.

Only one Flash me mory can be

enabled at a time.

Flash Da ta Ou t

Flash Write VIL VIH VIL VIL(2) VIH Flash Data In

Flash Address

Latch VIL XVIH VIL VIH Flash Data Out

or Hi-Z (3)

Flash Output

Disable VIL VIH VIH XVIH

Any PSRAM mode is allowed.

Flash memories must be disabled.

Hi-Z

Flash Standby VIH XXX

VIH Hi-Z Hi-Z

Flash Reset XXXX

VIL Hi-Z Hi-Z

Flash Deep

Power-Down VIH X X X

VIH Hi-Z Hi-Z

PSRAM Read

Flash memories must be disabled

VIL VIL VIL VIH VIL PSRAM data

out

PSRAM Write VIL VIL XVIL VIL PSRAM data in

PSRAM Read

Configuration

out

PSRAM

Standby Any Flash memory mode is allowed. Only

one Flash memory can be enabled at a

time

VIH VIL X X X Hi-Z

PSRAM Deep

Power-Down VIH XXX X Hi-Z

4 Maximum rating M36P0R9070E0

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4 Maximum rating

Stressing the device above the rating listed in th e Absolu te Maximum Ratings table may cause

permanent damage to the device. These are stress ratings only and operation of the device at

these or any other conditions above those indicated in the Operating se ctions of this

specification is not implied. Exposure to Absolute Maximum Rating conditions for extended

periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and

other relevant quality documents.

Table 4. Absolute Maximum Ratings

Symbol Parameter Value Unit

Min Max

TAAmbient Operating Temperature –30 85 °C

TBIAS Temperature Under Bias –30 85 °C

TSTG Storage Temperature –65 125 °C

VIO Input or Output Voltage –0.2 2.45 V

VDD Supply Voltage –0.2 2.45 V

VDDQ Input/Output Supply Voltage –0.2 2.45 V

VPP Program Voltage –1.0 12.6 V

IOOutput Short Circuit Current 100 mA

tVPPH Time for VPP at VPPH 100 hours

M36P0R9070E0 5 DC and AC parameters

17/26

5 DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics Tables that

follow, are derived from tests performed under the Measurement Conditions summarized in

Table 5., Operat ing and AC Measurement Conditions. Designers should check that the

operating conditions in their circuit match the operating co nditions when relying on the quoted

parameters.

Table 5. Operating and AC Measurement Conditions

Figure 3. AC Measurement I/O Waveform

Parameter Flash Memory PSRAM Unit

Min Max Min Max

VCCP Supply Voltage 1.7 1.95 1.7 1.95 V

VDDF Supply Voltage 1.7 1.95 1.7 1.95 V

VDDQ Supply Voltage 1.7 1.95 1.7 1.95 V

VPPF Supply Voltage (Factory environment) 8.5 9.5 – – V

VPPF Supply Voltage (Application environment) –0.4 VDDQ +0.4 ––V

Ambient Operating Temperatur e –30 85 –30 85 °C

Load Capacitance (CL)30 30 pF

Impedance Output (Z0)50 Ω

Output Circuit Protection Resistance (R) 50 Ω

Input Rise and Fall Times 3 ns

Input Pulse Voltages 0 to VDDQ 0 to VDDQ V

Input and Output Timing Ref. Voltages VDDQ/2 VDDQ/2 V

AI06161

VDDQ

VDDQ/2

5 DC and AC parameters M36P0R9070E0

18/26

Figure 4. AC Measurement Load Circuit

Table 6. Capacitance

1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 14 pF

COUT Output Capacitance VOUT = 0V 14 pF

AI06162a

VCCQ/2

DEVICE

UNDER

TEST Z0

OUT

M36P0R9070E0 5 DC and AC parameters

19/26

Table 7. Flash Memory DC Characteristics - Currents

Symbol Parameter Test Condition Typ Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VDDQ ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VDDQ ±1 µA

IDD1

Supply Current

Asynchronous Read (f=5MHz) EF = VIL, GF = VIH 25 30 mA

Supply Current

Page Read (f=13MHz) 11 15 mA

Supply Current

Synchronous Read (f=66MHz)

8 Word 22 32 mA

16 Word 19 26 mA

Continuous 25 34 mA

Supply Current

Synchronous Read (f = 108MHz)

8 Word 26 36 mA

16 Word 23 30 mA

Continuous 30 42 mA

IDD2 Supply Current (Reset) RPF = VSS ± 0.2V 512 Mbit 50 120 µA

IDD3 Supply Current (Standby) EF = VDDF ± 0.2V 512 Mbit 50 120 µA

IDD4 Supply Current (Automatic Standby) EF = VIL, GF = VIH 512 Mbit 50 120 µA

IDD5(1)

1. The DPD current is measured 40µs after entering the Deep Power Down mode.

Supply Current (Deep Power Down) 2 30 µA

IDD6 (2)

2. Sampled only, not 100% tested.

Supply Current (Program) VPPF = VPPH 35 50 mA

VPPF = VDDF 35 50 mA

Supply Current (Erase) VPPF = VPPH 35 50 mA

VPPF = VDDF 35 50 mA

Supply Current (Blank Check) VPPF = VPPH 35 50 mA

VPPF = VDDF 35 50 mA

IDD7 (2)(3)

3. VDDF Dual Operation current is the sum of read and program or erase currents.

Supply Current

(Dual Operations)

Program/Erase in one Bank,

Asynchronous Read in another Bank 60 80 mA

Program/Erase in one Bank,

Synchronous Read (Continuous

f=66MHz) in another Bank 65 92 mA

IDD8(2) Supply Current Program/ Erase

Suspended (Standby) EF = VDDF ± 0.2V 512 Mbit 50 120 µA

IPP1(2) VPPF Supply Current (Program) VPPF = VPPH 822mA

VPPF = VDDF 0.05 0.1 µA

VPPF Supply Current (Erase) VPPF = VPPH 822mA

VPPF = VDDF 0.05 0.1 µA

IPP2 VPPF Supply Current (Read) VPP F≤ VDDF 215µA

IPP3(2) VPPF Supply Current (Standb y,

Program/Erase Suspend) VPPF ≤ VDDF 0.2 5 µA

IPP4 VPPF Supply Current (Blank Check) VPPF = VPPH 0.05 0.1 mA

VPPF = VPP1 0.05 0.1 mA

5 DC and AC parameters M36P0R9070E0

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Table 8. Flash Memory DC Characteristics - Voltages

Symbol Parameter Test Condition Min Typ Max Unit

VIL Input Low Voltage 0 0.4 V

VIH Input High Voltage VDDQ –0.4 VDDQ + 0.4 V

VOL Output Low Voltage IOL = 100µA 0.1 V

VOH Output High Voltage IOH = –100µA VDDQ –0.1 V

VPP1 VPPF Program Voltag e-Logic Program, Erase 1.1 1.8 3.3 V

VPPH VPPF Program Voltage Factory Program, Erase 8.5 9.0 9.5 V

VPPLK Program or Erase Lockout 0.4 V

VLKO VDDF Lock Voltage 1V

VRPH RPF pin Extended High Voltage 3.3 V

VLKOQ VDDQ Lock Voltage 0.9 V

M36P0R9070E0 5 DC and AC parameters

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Table 9. PSRAM DC Characteristics

1. Input signals may overshoot to VDDQ+ 1.0V for periods of less than 2ns during transitions.

2. Output signals may undershoot to VSS – 1.0V for periods of less than 2ns during transitions.

3. BCR5-BCR4 = 01 (default settings).

4. This parameter is specified with all outputs disabled to avoid external loading effects. The user must add the current

required to drive output capacitance expected for the actual system.

5. ISB maximum value is measured at +85°C with PAR set to Full Array. In order to achieve low standby current, all inputs

must be driven either to VDDQ or VSSQ. ISB might be slightly higher for up to 500ms after Power-up, or when entering

Standby mode.

Symbol Parameter Refreshed

Array Test Conditions Min. Typ. Max. Unit

VOH(3) Output High Voltage IOH = –0.2mA 0.8VDDQ V

VOL(3) Output Low Voltage IOL = 0.2mA 0.2VDDQ V

VIH(1) Input High Voltage VDDQ − 0.4 VDDQ + 0.2 V

VIL(2) Input Low Voltage −0.2 0.4 V

ILI Input Leakage Current VIN = 0 to VDDQ 1µA

ILO Output Leakage Current GP = VIH or EP = VIH 1µA

ICC1(4) Asynchronous Read/Write

Random at tRC min VIN = 0V or VDDQ,

IOUT = 0mA, EP = VIL

70ns 25 mA

85ns 22 mA

ICC2(4) Asynchronous Page Read VIN = 0V or VDDQ

IOUT = 0mA, EP = VIL

70ns 15 mA

85ns 12 mA

ICC3(4) Burst, Initial Read/Write

Access VIN = 0V or VDDQ

IOUT = 0mA, EP = VIL

104MHz 35 mA

80MHz 30 mA

66MHz 25 mA

ICC4R(4) Continuous Burst Read VIN = 0V or VDDQ

IOUT = 0mA, EP = VIL

104MHz 30 mA

80MHz 25 mA

66MHz 20 mA

ICC4W(4

)Continuous Burst Write VIN = 0V or VDDQ

IOUT = 0mA, EP = VIL

104MHz 35 mA

80MHz 30 mA

66MHz 25 mA

IPASR(4)

Partial Array

Refresh

Standby

Current

Full Array

VIN = 0V or VDDQ

EP = VDDQ

200 µA

1/2 Array 170 µA

1/4 Array 155 µA

1/8 Array 150 µA

None 140 µA

ISB(5) Standby Current VIN = 0V or VDDQ

EP = VDDQ 200 µA

ICCPD Deep-Power Down Current VIN = 0V or VDDQ,

VCCP

, VDDQ = 1.95V; TA= +85°C 310µA

6 Package mechanical M36P0R9070E0

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6 Package mechanical

In order to meet environmental requirements, ST offers these devices in ECOPACK®

pac kages. The se packages have a Lead-free second-level interconnect. The category of

Second-Level Inte rconnect is marked on the pac kage a nd on the in ner bo x label, in compliance

with JEDEC Standard JESD97.

The maximum ratings relat ed to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are a vailable at: www.st.com.

Figure 5. TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitch, package outline

1. Drawing is not to scale.

BGA-Z85

ddd

BALL "B1"

M36P0R9070E0 6 Package mechanical

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Table 10. Stacked TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitch, pa ckage data

Symbol millimeters inches

Typ Min Max Typ Min Max

A1.200.047

A1 0.20 0.008

A2 0.85 0.033

b 0.35 0.30 0.40 0.014 0.012 0.016

D 8.00 7.90 8.10 0.315 0.311 0.319

D1 6.40 0.252

ddd 0.10 0.004

E 11.00 10.90 11.10 0.433 0.429 0.437

E1 8.80 0.346

e 0.80 0.031

FD 0.80 0.031

FE 1.10 0.043

SE 0.40 0.016

7 Part numbering M36P0R9070E0

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7 Part numbering

Table 11. Ordering Information Scheme

Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of

available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact the STMicroelectronics Sales Office nearest to you.

M36 P 0 R 9 0 7 0 E 0 ZAC E

Example:

Device Type

M36 = Multi-Chip Package (Multiple Flash + PSRAM)

Flash 1 Architecture

P = Multi-Level, Multiple Bank, Large Buffer

Flash 2 Architecture

0 = No Die

Operatin g Voltage

R = VDDF = VCCP = VDDQ = 1.7 to 1.95V

Flash 1 Density

9 = 512 Mbits

Flash 2 Density

0 = No Die

RAM 1 Density

7 = 128 Mbits

RAM 0 Density

0 = No Die

Parameter Blocks Location

E = Even Block Flash Memory Configuration

Prod uct Version

0 = 90nm Flash technology, 93ns speed; PSRAM

Package

ZAC= stacked TFBGA107 C stacked footprint.

Option

Blank = Standard Pack ing

E = ECOPACK® Package, Standard packing

F = ECOPACK® Package, Tape & Reel pack ing

M36P0R9070E0 8 Revision history

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8 Revision history

Table 12. Document revision history

Date Revision Changes

28-Nov-2005 1 Initial release.

M36P0R9070E0

26/26

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