Philips Semiconductors Advanced BiCMOS Products Application note Thermal considerations for advanced logic families (Futurebus+, ABT and MULTIBYTE) management of thermal characteristics becomes a growing concern because not only are the SMD packages much smaller, but the thermal energy is concentrated more densely on the printed wiring board. For these reasons, designers and manufacturers of surface mount assemblies must be aware of all the variables affecting TJ. INTRODUCTION Thermal characteristics of integrated circuit packages have been and increasingly will be a major consideration to both producers and users of electronics products. This is because an increase in junction temperature (TJ) can adversely effect the long term operating life of an IC. The advantages realized by miniaturization often have trade-offs in terms of increased junction temperatures. Some of the variables affecting TJ are controlled by the IC manufacturer and others are controlled by the system designer. Depending on the environment in which the IC is placed, the user could control well over 75% of the current that flows through the device. Power dissipation for the ABT (Advanced BiCMOS Technology), MULTIBYTE and Futurebus+ devices can be estimated using the same equation with the exception of Futurebus+ transceivers. Due to BTL OPEN-COLLECTOR outputs, BTL output swings and the large current driven on the BTL side (B side) of the transceivers the equation must be altered. 1 2 FOUTi s i1 V CC 3 I I CCL I CCH s CCL n L I CCn 3 2n 2. Input voltage levels 3. Output loading (capacitive and resistive) 5. Duty cycle Each of these five factors are addressed in the estimating equation except duty cycle. Duty cycle can be addressed by "weighting" terms 2, 5, 6, 7 and 8 appropriately. Conditions under which measurements were taken and upon which the Power Dissipation Equation is based are: 6 CLIFOUTiKPi VROH s h i1 i1 7 (V OL) (V OH V OL) 1. Frequency of operation (output switching frequency) 4 5 (V CC V OH) (V OH V OL) There are five major factors controlled by the user which contribute to increased BiCMOS power dissipation. 4. VCC level POWER DISSIPATION With the ever increasing use of Surface Mount Device (SMD) technology, P D V CC C PV CC AN241 D i 8 CLIFOUTi (VCCR VOL) s l i1 i1 U i Power Dissipation Equation VCC = 5V; 25C; FOUT = 1, 10, 20, 30, 40, and 50MHz; 50% duty cycle; CL = 0, 15, 50, 100, and 200pF; also 1, 2, 4, and 8 outputs switching. The first current term is due to ICC with the device unloaded. It is caused by the internal switching of the device. FOUTi s C PV CC i1 This term represents the ICC current with absolutely no load. This measurement was taken without the output pins connected to the board. The CP for a device is calculated by: I (@50MHz) I CC(@1MHz) C P CC V CC(49MHz)s The second term is current due to ICC with the outputs unloaded. This ICC is caused by switching the bipolar outputs. (I CCL I CCH) s 2n The ICCL and ICCH are the typical values found in the corresponding product data sheets. In the case of a 50% duty cycle an average of ICCL and ICCH will flow through the device. "n" is the number of outputs on the device. The third term is ICCL due to the outputs being held Low. The ICCH current is in the A I CCL L n "L" is the number of outputs held Low. The fourth term is through current due to holding the CMOS inputs at 3.4V rather than at the rail voltages. This term becomes insignificant as load and frequency increase. I CCn 3 ICC is the through current when holding the input High of a device to 3.4V. This value is typically 300A to 500A. "n3" is the number of inputs at 3.4V. The fifth term is current through the upper structure of the device. It is caused by the external capacitive load and the output "s" is the number of outputs switching. CP will be different for each product type. June, 1992 range so if an output is held or forced High then there is no appreciable ICC increase. 1 Philips Semiconductors Advanced BiCMOS Products Application note Thermal considerations for advanced logic families (Futurebus+, ABT and MULTIBYTE) frequency. If a capacitive load exists then this term can become very significant. VCC VCC I PATH I PATH CL CL CLiFOUTi s (V OH V OL) CLiFOUTiKPi S (V OH V OL) i1 VOH-VOL is the voltage swing of the output. CL is the output load (this can vary from output to output). FOUT is the output frequency which can also vary from output to output. i1 This current is not ICC, but rather current that is "sinked" from an external source. The eighth and final term is due to an external load connected to VCC. VCC I PATH KP is a factor which best estimates the feedthrough current and variances in the "VOH-VOL" factor as CL changes. KP = f(CL) = -2.5E- 5CL2+4.3E-3CL+1.4 (CL is expressed in unitless terms, e.g. "15" for 15pF...). The sixth term is current through the upper structure due to an external resistive load to ground. This term includes both switching outputs and static High outputs. RD This term includes both switching and static Low outputs. (VCCR VOL) I VCC I PATH U i1 As the output frequency increases the measured current approaches that of static High outputs. VROH h i1 D i RD is an external pull-down resistor. A different value load could be applied to each output. The seventh current term is determined by the output capacitive load and the output frequency on the lower structure of the device. If this load exists then this term is also significant. All variables are the same as with the fifth term with the exception that this is current flowing through the lower structure of the IC. June, 1992 Futurebus+ transceivers' power dissipation can be estimated in the same way as ABT devices, excepting terms 3, 5, 6 and 8 in the equation. An ICCH term needs to be added to term 3. Term 3 would then read "ICCLL/n+ ICCHH/n". "H" is the number of outputs held static High. Since BTL outputs are open-collector, terms 5 and 6 do not apply and are discarded. Term 8 needs to be adjusted--replace "(VCC-VOL)" with "(2.1V-VOL)". (If the level of the pull-up voltage is not 2.1V then the actual pull-up voltage would be substituted). ABT CP VALUES Many of the ABT products have been characterized for their CP values. The following table shows the products that have been tested along with their corresponding CP numbers. Over time CP for all ABT and MULTIBYTE products will be characterized. Refer to the individual product data sheets for their values if the values are not noted below. 2 74ABT125 6.0pF 74ABT126 6.5pF 74ABT240 7.0pF 74ABT240-1 7.0pF 74ABT244 4.5pF 74ABT244-1 5.5pF 74ABT540 7.0pF 74ABT543 11.0pF 74ABT544 11.0pF 74ABT620 9.0pF 74ABT640 8.5pF 74ABT646 11.0pF 74ABT648 11.5pF 74ABT651 11.5pF 74ABT652 11.5pF 74ABT657 9.0pF 74ABT821 16.0pF 74ABT823 17.0pF 74ABT827 6.0pF 74ABT833 7.5pF 74ABT841 9.0pF 74ABT843 9.5pF 74ABT861 7.0pF 74ABT863 7.5pF 74ABT899 11.0pF 74ABT2952 16.0pF 74ABT2953 16.0pF i As with term seven, this is current that flows through the lower structure of the IC. This current too is not ICC. RD AN241 THERMAL RESISTANCE The ability of a package to conduct heat from the chip to the environment is expressed in terms of thermal resistance. The term normally used is Theta JA (JA). JA is often separated into two components: thermal resistance from the junction to case, and the thermal resistance from the case to ambient. JA represents the total resistance to heat flow from the chip to ambient and is expressed as follows: JC + CA = JA Detailed JA and JC graphs will be included in a later section of this note. For the ease of the user a table with JA and JC values for average die sizes is included here. Philips Semiconductors Advanced BiCMOS Products Application note Thermal considerations for advanced logic families (Futurebus+, ABT and MULTIBYTE) JA AND JC CALCULATIONS FOR ABT, MULTIBYTE, AND FUTUREBUS+ DIP # Still 300 pins air lfpm 14 82 63 16 82 63 20 74 57 24 65 50 28 61 47 52 - - 68 - - 84 - - 100 - - JA SO pkg PLCC/PQFP Still 300 Still 300 air lfpm air lfpm 117 98 - - 110 92 - - 91 74 - - 77 63 - - 71 58 69 50 - - 79 57 - - 48 35 - - 39 28 - - 61 43 Preliminary JA (new packages) SSOP SQFP # Still 200 Still pins air lfpm air *20 143 119 - *24 135 110 - *100 - - 68 # pins 14 16 20 24 28 52 68 84 100 DIP pkg 38 38 32 36 31 - - - - JC SO pkg 36 35 29 26 26 - - - - PLCC/PQFP - - - - 34 23 18 14 15 NOTES: * Preliminary data only * (for ABT use 1.8mm x 1.8mm (70mil x 70mil) average die size) * (for MULTIBYTE and Futurebus+ transceivers use 3.0mm x 3.5mm (118mil x 138mil) average die size) * (for 68/84-pin Futurebus+ use 3.8mm x 3.7mm (149mil x 146mil) average die size) * (for 100-pin Futurebus+ use 6.0mm x 6.0mm (235mil x 235mil) average die size) JUNCTION TEMPERATURE (TJ) Junction temperature (TJ) is the temperature of a powered IC at the substrate diode. Signetics uses a technique known as the temperature sensitive parameter (TSP) method to measure the junction temperature of an IC. This method uses the linear relationship between forward voltage and temperature (at a constant forward current) of June, 1992 a diode to measure junction temperature. The change in junction temperature can be measured for a known power dissipation which then allows for the thermal resistance to be calculated using the expression shown for JA: DT J (T T amb) q JA J PD PD where Tamb is the temperature of the ambient. For detailed information on the measurement techniques and the tools used, please refer to Signetics' Reliability Management Group Publication "IC Package Thermal Resistance Characteristics". Once the value of JA has been found then TJ can be calculated for varying PDs. TJ = PD x JA + Tamb For Signetics' Futurebus+, ABT, and MULTIBYTE the following criterion is used to warn customers about excessive TJ. If the junction temperature (TJ) could exceed 125C but not 150C then a warning to the customer recommending thermal mounting must appear on the data sheet. If the TJ could exceed 150C but not 175C then it is necessary to warn the customer and advise specific methods (to be found in the product data sheet) to reduce the TJ to 125C. TJ may be reduced either by thermal mounting techniques or by the use of forced air. If TJ could exceed 175C then the product release will not occur and a redesign will be initiated or limit changes will be made in order to lower the TJ below the 175C limit. AN241 package and the substrate, the number and length of traces on the board, thermally conductive epoxies, and external cooling. PACKAGE CONSIDERATIONS Following is a brief discussion on various package factors and their effect on thermal resistance. These items are inherent to the package design, and therefore are fixed by Signetics. Die size has a large effect on thermal resistance. Smaller die sizes result in higher thermal resistances, given that other package parameters remain constant. This effect is reflected in the graphical data presented in this note. Die size is a function of device type and complexity. Die attach methods used by Signetics have little effect on thermal resistance due to the thinness (typically less than 1 mil), the good thermal conductivity and the low power dissipation of the ICs (typically less than 2 watts). Die attach methods and material can have large effects on device reliability and die stress. These items along with high thermal conductivity control limit the selection of materials and processes. The copper leadframes of plastic packages require a compliant die attach. To meet this requirement, Signetics uses high thermal conductivity adhesives. Leadframe material is one of the more important factors. The higher the conductivity, the lower the thermal resistance because of the heat spreading effect of the leadframe. For this reason all current Signetics plastic packages use high thermal conductivity copper alloy leadframes. With the advent of multiple-byte products (MULTIBYTE) it may become possible to switch forty outputs simultaneously. When this occurs the system designer must be aware of the risks/dangers of rising TJ values. Eventually compromises must be made in order to keep TJ below damaging values. Leadframe design is important especially for plastic packages; large pad and pad support structures improve thermal resistance. Leadframe design is mainly controlled by die size and pad position layout, however, thermal dissipation is maximized whenever possible. FACTORS AFFECTING JA Bond wires, because of their small size, (1.0 to 1.3 mil diameter) do not provide a significant thermal path in Signetics' packages and thus have little effect on thermal resistance. There are several factors which affect the thermal resistance of an IC package. Effective thermal management demands a sound understanding of these factors. Major package variables include the leadframe design and the plastic used to encapsulate the device. Other variables such as the die size and die attach methods also affect thermal resistance. Other factors that have a significant impact on the JA include the substrate upon which the IC is mounted, the layout density, the air-gap between the 3 Package body material could have a large effect on thermal resistance, but package requirements such as reliability, manufacturing, etc. control the selection of these materials. Until new materials are developed there is no real opportunity for decreasing thermal resistance by increasing package body thermal conductivity while maintaining our high reliability standards. Philips Semiconductors Advanced BiCMOS Products Application note Thermal considerations for advanced logic families (Futurebus+, ABT and MULTIBYTE) THERMAL RESISTANCE MEASUREMENTS EXAMPLE OF ABT TJ CALCULATION 1. Calculate Current Consumption: Thermal resistance values are presented as a function of die size for each package. All data was derived from tests carried out on devices run at a constant power dissipation (actual dissipation is given with each graph). Whether power dissipation is higher or lower, it will only slightly affect thermal resistance. The general trend is for decreasing thermal resistance with increasing power. This is common to all packages. For example the ABT244's CP is 4.5pF. Let VCC = 5V; operating temperature = 25C; FOUT = 50MHz for 4 outputs switching; hold 2 inputs Low and 2 inputs High (at 3.4V); CL = 100pF; 500 pull-down; no pull-up. 1 Thermal resistance can be affected by slight variation in internal leadframe design. For example a larger die pad gives slightly lower thermal resistance for the same size die. The data presented represents the typical Signetics leadframe/die combinations with large die on large pads and small die on small pads. There are many transition areas where a die could be placed differently depending on pad layout, aspect ratio, etc. The effect of leadframe design is within the 15% accuracy of these graphs. Data is available with improved accuracy (7.5%). For exact die/leadframe/power dissipation combinations, contact Philips Components-Signetics, Reliability Management Group Publications, MS 35, 811 E. Arques Avenue, Sunnyvale, CA 94088-3409 or call (408) 991-2000. Data is also available in the form of a computer program (SIGTHERM) which runs on IBM or compatible PCs in BASIC. SIGTHERM provides estimates for JA and JC using exact die/leadframe/power dissipation combinations resulting in more accurate (7.5%) data than in the graphs in this note. SIGTHERM also gives JA estimates at different air flow rates between 100-800 LFPM. The program requires the user to input package type, die size, power dissipation and leadframe code. Contact Philips Components-Signetics Reliability Management Group Publications, MS 35, for more information on SIGTHERM. 5V 50MHz 4 4.5pF i+1 + 4.5mA 5V(17.625mA) = 88.1mW The fifth and sixth terms are multiplied by the voltage drop across the upper structure of the device, VCC-VOH. This is approximately 1V. The seventh and eighth terms are multiplied by the voltage drop across the lower structure of the device, VOL. 3 0.2V(76mA) = 15.2mW 4 ) 0.5mA 4 ) 24mA 2 ) .5mA(2) 24mA2(8) 8 + 6.125mA ) 6mA ) 1mA + 13.125mA These unloaded terms contribute only 9% of the total ICC current. + 5 (4V * 0.2V) When calculating the total power dissipation of the device, the first four terms are multiplied by VCC, which in this example is 5V. 1V(168.1mA) = 168.1mW + 2 AN241 6 4V 100pF50MHz1.58 ) 500W 4 6 i+1 i+1 where: KP = -2.5E-5(1002) + 4.3E-3(100) + 1.4 = 1.58 The total estimated power dissipation of an ABT244 with 4 outputs switching, at 25C, with VCC = 5V, with 2 outputs held static Low, and 2 inputs at 3.4V, with 100pF capacitive loads, 500 pull-downs, and 50MHz switching frequency is: 271.4mW 3. Determine JA The JA for a 20-pin SOL package using the average die size for ABT is 91C/W @ 0.7W. 4. Determine JA @ 271mW PD Using the AVERAGE EFFECT of POWER DISSIPATION on JA graph calculate the percentage change in power = (.271W - .7W)/.7W = -.61 (-61% change) then check the graph and see that JA increases by 8.5%. So JA increases to 91 + 91 x .085 = 6 4 (5V * 02V) 98.7C/W. 100pF50MHz ) (4V * 0.2V) R i+1 i+1 5. Assume 200 LFPM Air Flow + 76mA ) 0 + 76mA Calculate the effects of air flow by referring to These terms are not ICC currents, but rather the graph AVERAGE EFFECT of AIR FLOW currents "sinked" by the lower structure of the on JA. The JA is decreased by 14% leaving device. a JA of 98.7 - (.14 x 98.7) = 84.9C/W. In this example terms five and six contribute over 90% of the total ICC current . This part of ICC is entirely due to external loading. 7 8 Term Predicted Measured 6. Final Calculations for TJ for the ABT244 1&2 10.63mA 10.2mA 3 6mA 6mA 4 1mA 1.5mA 5 120.1mA 117.8mA TJ = (PD x JA) + Tamb = (.271W x 84.9C/W) + 70C = 93C. Referring to the warnings in the JUNCTION TEMPERATURE section, a 93C TJ would constitute absolutely no junction temperature worries. 6 48mA 53mA Junction temperature can be estimated using the following equation: 7 76mA -- 8 0mA -- TJ = (JA x PD) + Tamb Total 1-6 185.7mA 188.4mA EXAMPLES OF THERMAL CALCULATIONS Where: TJ = Junction Temperature (C) JA = Thermal Resistance Junction-to-Ambient PD = Power Dissipation at a TJ Tamb = Temperature of Ambient (C) June, 1992 For this example the equation estimate is within 1% of the actual ICC current!! This is not a claim of 1% accuracy, but the equation is quite accurate. (Terms 7 and 8 are not included in the comparison.) 2. Finding PD (V x I) 4 Philips Semiconductors Advanced BiCMOS Products Application note Thermal considerations for advanced logic families (Futurebus+, ABT and MULTIBYTE) EXAMPLE OF FUTUREBUS+ TRANSCEIVER TJ FOR BTL SIDE ("A" side can be treated like ABT) AN241 3. Determine JA + 8 7(2.1V-1.0V)/16.5 = 466.7mA 1. Calculate Current Consumption 2. Finding PD (V x I) For example let the FB2031's CP be 16pF. Let VCC = 5V; operating temperature = 25C; FOUT = 50MHz for 5 outputs switching; hold 2 inputs Low and 2 inputs High (at 3.4V); CL = 100pF; no pull-down; 16.5 pull-up. The first four current terms are multiplied by VCC. The FB2031 is packaged in the 52-pin PQFP. Using an average die size of 118 x 138 yields a JA of 79C/W @ 1W power dissipation (see JA graph). 4. Determine JA @ 721.9mW PD Using the AVERAGE EFFECT of POWER DISSIPATION on JA graph calculate the percentage change in power = (0.7219W - 1W)/1W = -.28 (-28% change) then check the graph and see that JA increases by 3.4%. So JA increases to 79 + 79 x .034 = 81.7C/W. 5V(20mA + 9.44mA + 15.1mA + 1mA) = 227.7mW 1 16pF(5V(5)50MHz) = 20mA Term seven is multiplied by 1V (VOL). + Term eight is also multiplied 1V (VOL). 1V(27.5mA) = 27.5mW 2 (17mA + 17mA)/2(9) x 5 = 9.44mA 1V(466.7mA) = 466.7mW + 3 17mA/9 x 2 + 17mA/9 x 2 = 15.1mA + 4 .5mA x 2 = 1mA + 7 1.1V(5)100pF50MHz = 27.5mA 5. Assume 200 LFPM Air Flow The total estimated power dissipation of an FB2031 with 5 outputs switching, at 25C, with VCC = 5V, with 2 outputs held static Low, and 2 inputs at 3.4V, with 100pF capacitive loads, no pull-downs, 16.5 pull-ups and 50MHz switching frequency is: Calculate the effects of air flow by referring to the graph AVERAGE EFFECT of AIR FLOW on JA. The JA is decreased by 22.5% leaving a JA of 81.7 - (.225 x 81.7) = 63.3C/W. 227.7 + 27.5 + 466.7 = 721.9mW 6. Final Calculations for TJ for the FB2031 Term eight contributed over 65% of the power dissipated by the FB2031 in this example. The power dissipated by the IC with no external loading totals only 32% of the power. TJ = (PD x JA) + Tamb = (0.7219W x 63.3C/W) + 70C = 115.1C. Referring to the warnings in the JUNCTION TEMPERATURE section, a 115.1C TJ would constitute no temperature worries. MODIFYING JA FOR POWER DISSIPATION AND AIRFLOW 10 0 8 -5 TEST POWER RANGE .3 TO 3 WATTS 6 SO Philips PCB(1.12" x 0.75" x 0.059") SOL Philips PCB(1.58" x 0.75" x 0.059") PLCC & PQFP Signetics PCB(2.24" x 2.24" x 0.062"") DIP Textool ZIF Socket with 0.040" Stand-off -10 4 -15 2 % Change in JA -20 % Change in JA -25 0 -2 -30 S O SOL -35 DIP -40 PLCC, PQFP -4 -6 -8 -10 -60 June, 1992 -45 -40 -20 0 20 40 60 80 100 120 0 100 200 300 400 500 600 700 800 % Change in Power Dissipation % Change in Power Dissipation Average Effect of Power Dissipation on JA Average Effect of Air Flow on JA 5 900 1000 Philips Semiconductors Advanced BiCMOS Products Application note Thermal considerations for advanced logic families (Futurebus+, ABT and MULTIBYTE) AN241 TYPICAL THERMAL RESISTANCE (JA) in C/W Typical JA Data SO-141 Typical JA Data SO-161 140 120 130 115 Typical JA Data SOL-202 100 95 90 JA JA JA 120 110 110 105 85 80 75 100 100 0 2 4 6 8 10 70 0 DIE SIZE (SQ MILS x 1000) 2 4 6 8 10 DIE SIZE (SQ MILS x 1000) Typical JA Data SOL-242 80 78 78 76 74 JA 76 JA 72 70 74 68 66 72 64 62 70 60 0 5 10 15 20 25 30 DIE SIZE (SQ MILS x 1000) 0 10 30 40 50 DIE SIZE (SQ MILS x 1000) NOTES 1. Power Dissipation Test Ambiant Test Fixture Accuracy 2. Power Dissipation Test Ambiant Test Fixture Accuracy June, 1992 20 0.5W Still Air Philips PCB (1.12" x 0.75" x 0.059") 15% 0.7W Still Air Philips PCB (1.58" x 0.75" x 0.059") 15% 6 5 10 15 20 25 DIE SIZE (SQ MILS x 1000) Typical JA Data SOL-282 80 0 30 Philips Semiconductors Advanced BiCMOS Products Application note Thermal considerations for advanced logic families (Futurebus+, ABT and MULTIBYTE) AN241 TYPICAL THERMAL RESISTANCE (JA) in C/W Typical JA Data DIP-14 & 16 Typical JA Data DIP-20 100 95 70 85 PD = 0.5W 90 JA Typical JA Data DIP-24 90 PD = 0.75W 80 85 JA 75 80 70 75 65 70 60 65 55 60 JA 60 55 50 0 5 10 15 20 25 DIE SIZE (SQ MILS x 1000) PD = 1.0W 65 50 0 5 10 15 20 25 30 35 DIE SIZE (SQ MILS x 1000) 40 0 5 10 15 Typical JA Data DIP-28 70 PD = 1.0W 65 NOTE Test Ambiant Test Fixture Accuracy JA 60 55 50 0 5 10 15 20 25 30 35 40 DIE SIZE (SQ MILS x 1000) June, 1992 7 20 25 30 35 DIE SIZE (SQ MILS x 1000) Still Air Textool ZIF Socket .040" Stand-Off) 15% 40 Philips Semiconductors Advanced BiCMOS Products Application note Thermal considerations for advanced logic families (Futurebus+, ABT and MULTIBYTE) AN241 TYPICAL THERMAL RESISTANCE (JA) in C/W Typical JA Data PLCC-28 Typical JA Data PLCC-68 75 Typical JA Data PLCC-84 50 48 PD = 0.75W 70 40 JA JA 38 PD = 1.0W 46 JA PD = 1.5W 36 65 44 34 42 32 60 55 40 0 10 20 30 40 50 60 30 10 DIE SIZE (SQ MILS x 1000) 20 30 40 50 60 70 80 90 100 20 DIE SIZE (SQ MILS x 1000) Typical JA Data PQFP-52 Typical JA Data PQFP-100 90 75 PD = 1.0W 85 PD = 1.0W 70 JA 80 65 75 60 70 55 0 5 10 15 20 25 30 35 40 DIE SIZE (SQ MILS x 1000) NOTES: Test Ambiant Test Fixture Accuracy 10 15 20 25 30 35 40 45 50 55 60 DIE SIZE (SQ MILS x 1000) Still Air Signetics PCB (2.24" x 2.24" x 0.062") 15% Data for the 20/24-pin SSOP is preliminary. Graphs are not yet available. Please see the table, "JA AND JC CALCULATIONS FOR ABT, MULTIBYTE, AND FUTUREBUS+" for the preliminary values. June, 1992 8 30 40 50 60 70 80 90 DIE SIZE (SQ MILS x 1000) 100 Philips Semiconductors Advanced BiCMOS Products Application note Thermal considerations for advanced logic families (Futurebus+, ABT and MULTIBYTE) AN241 MODIFYING JC FOR POWER DISSIPATION 10 8 TEST POWER RANGE .3 TO 3 WATTS 6 4 2 % Change in JC 0 -2 -4 -6 -8 -10 -60 -40 -20 0 20 40 60 80 100 120 % Change in Power Dissipation Average Effect of Power Dissipation on JC TYPICAL THERMAL RESISTANCE (JC) in C/W Typical JC Data SO-16 Typical JC Data SO-14 40 Typical JC Data SOL-20 35 40 PD = 0.5W 38 PD = 0.5W 38 PD = 0.7W 30 JC 36 JC 34 36 JC 34 25 32 32 30 30 0 2 4 6 8 10 20 0 DIE SIZE (SQ MILS x 1000) 2 4 6 8 10 DIE SIZE (SQ MILS x 1000) Typical JC Data SOL-24 0 5 10 15 20 25 DIE SIZE (SQ MILS x 1000) Typical JC Data SOL-28 30 30 28 PD = 0.7W PD = 0.7W 25 JC 26 NOTE: Test Fixture Accuracy JC 24 20 22 20 15 0 5 10 15 20 25 DIE SIZE (SQ MILS x 1000) June, 1992 30 0 10 20 30 40 DIE SIZE (SQ MILS x 1000) 9 50 Infinite Heat Sink 15% 30 Philips Semiconductors Advanced BiCMOS Products Application note Thermal considerations for advanced logic families (Futurebus+, ABT and MULTIBYTE) AN241 TYPICAL THERMAL RESISTANCE (JC) in C/W Typical JC Data DIP-14 & 16 Typical JC Data DIP-20 50 45 JC Typical JC Data DIP-24 40 40 PD = 0.75W PD = 0.5W PD = 1.0W 35 40 35 JC JC 30 30 25 25 35 30 25 20 0 5 10 15 20 25 20 0 DIE SIZE (SQ MILS x 1000) 5 10 15 20 25 30 35 40 0 DIE SIZE (SQ MILS x 1000) Typical JC Data DIP-28 Typical JC Data PLCC-28 25 30 35 40 Typical JC Data PLCC-68 PD = 0.75W 35 PD = 1.0W 18 32 17 31 JC 30 JC 30 16 15 25 29 14 28 13 27 20 12 26 11 25 15 0 5 10 15 20 25 30 35 40 DIE SIZE (SQ MILS x 1000) 10 0 10 20 30 40 50 DIE SIZE (SQ MILS x 1000) 60 10 20 30 Typical JC Data PLCC-84 PD = 1.5W 14 NOTE: Test Fixture Accuracy 13 12 11 10 20 30 40 50 60 70 80 90 100 DIE SIZE (SQ MILS x 1000) 10 40 50 60 70 80 90 100 DIE SIZE (SQ MILS x 1000) 15 June, 1992 20 19 PD = 1.0W 33 JC 15 20 34 JC 10 DIE SIZE (SQ MILS x 1000) 40 35 5 Infinite Heat Sink 15% Philips Semiconductors Advanced BiCMOS Products Application note Thermal considerations for advanced logic families (Futurebus+, ABT and MULTIBYTE) AN241 TYPICAL THERMAL RESISTANCE (JC) in C/W Typical JC Data PQFP-100 Typical JC Data PQFP-52 30 25 PD = 1.0W PD = 1.0W 25 20 JC 15 15 10 0 5 10 15 20 25 30 35 40 DIE SIZE (SQ MILS x 1000) SYSTEM CONSIDERATIONS The manner in which an IC package is mounted and positioned in its surrounding environment will have significant effects on operating junction temperatures. These conditions are under the control of the system designer and are worthy of serious consideration in PC board layout and system ventilation and airflow features. Forced-air cooling will significantly reduce JA. The figure entitled "AVERAGE EFFECT OF AIR FLOW ON JA" provides curves resulting from Signetics evolution of the effect of air flow on each of the fundamental package families. These data are for approximate linear flow across the long dimension of the package. Air flow parallel to the long dimension of the package is generally a few percent more effective than air flow perpendicular to the long dimension of the package. In actual board layouts, other components can provide air flow blocking and flow turbulence, which may reflect the net reduction of JA of a specific component. These issues should be carefully evaluated when using the data presented. External heat sinks applied to an IC package can improve thermal resistance by increasing June, 1992 Infinite Heat Sink 15% Data for the 20/24-pin SSOP is preliminary. Graphs are not yet available. Please see the table, "JA AND JC CALCULATIONS FOR ABT, MULTIBYTE, AND FUTUREBUS+" for the preliminary values. JC 20 NOTES: Test Fixture Accuracy 10 15 20 25 30 35 40 45 50 55 60 DIE SIZE (SQ MILS x 1000) heat flow to the ambient environment. Heat sink performance will vary by size, material, design, and system air flow. Heat sinks can provide a substantial improvement. Package mounting can affect thermal resistance. The data given herein relates to specific test environments; however, the general data holds true for other applications. Surface mount packages dissipate significant amounts of heat through the leads. Improving heat flow from package leads to ambient will decrease thermal resistance. The following factors have been investigated. The metal (copper) traces on PC boards conduct heat away from the package and dissipate it to the ambient; thus the larger the trace area the lower the thermal resistance. Package stand-off has a small effect on JA. Boards with higher thermal conductivity (ceramic) may show the most pronounced benefit. The use of thermally conductive adhesive under SO packages can lower thermal resistance by providing a direct heat flow path from the package to board. Naturally 11 high thermal conductivity board material and/or cool board temperatures amplify this effect. High thermal conductive board material will decrease thermal resistance. Data from Philips indicates that a change in board material from epoxy laminate to ceramic reduces thermal resistance. CONCLUSION Thermal management remains a major concern of producers and users of ICs. With the advent of SMD technology, a thorough understanding of the thermal characteristics of both the devices and the systems is very important. The smaller SMD package does have a higher JA than its standard DIP counterpart -- even with copper leadframes. The increased JA is the major trade-off one must accept for package miniaturization. When the user considers all of the variables that affect the IC junction temperature, he is then prepared to take the maximum advantage of the tools, materials and data that are available.