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24
23
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15
14
13
LOUT–
SHUTDOWN
PVDD
UP
DOWN
CLK
BYPASS
PVDD
VAUX
PC-BEEP
ROUT–
GND
GND
LOUT+
SE/BTL
LIN
LLINEIN
LHPIN
VDD
RHPIN
RLINEIN
RIN
HP/LINE
ROUT+
PWP PACKAGE
(TOP VIEW)
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
2.8-W STEREO AUDIO POWER AMPLIFIERWITH DIGITAL VOLUME CONTROL
•Internal Memory Restores Volume SettingAfter Shutdown or Power Down•Digital Volume Control From 20 dB to -40 dB•2.8-W/Ch Output Power Into 3- ΩLoad•Stereo Input MUX•Compatible With PC 99 Desktop Line-Out Into10-k ΩLoad•Compatible With PC 99 Portable Into 8- ΩLoad•PC-Beep Input•Depop Circuitry•Fully Differential Input•Low Supply Current and Shutdown Current•Surface-Mount Power Packaging 24-PinTSSOP PowerPAD™
DESCRIPTION
The TPA0252 is a stereo audio power amplifier in a 24-pin TSSOP thermally-enhanced package capable ofdelivering 2.8 W of continuous RMS power per channel into 3- Ωloads. This device minimizes the number ofexternal components needed, which simplifies the design and frees up board space for other features. Whendriving 1 W into 8- Ωspeakers, the TPA0252 has less than 0.3% THD+N across its specified frequency range.The integrated depop circuitry virtually eliminates transients that cause noise in the speakers.
Amplifier gain is controlled by two terminals, UP and DOWN. There are 31 discrete steps covering the range of20 dB (maximum volume setting) to –40 dB (minimum volume setting) in 2 dB steps. By pressing either buttonmomentarily, the volume steps up or down 2 dB. If a button is held down, the device starts stepping throughvolume settings at a rate determined by the capacitor on the CLK terminal.
An internal input MUX, controlled by the HP/ LINE pin, allows two sets of stereo inputs to the amplifier. Innotebook applications, where internal speakers are driven as bridge-tied loads (BTL) and the line outputs (oftenheadphone drive) are required to be single-ended (SE), the TPA0252 automatically switches into SE mode whenthe SE/ BTL input is activated. This effectively reduces the gain by 6 dB.
The TPA0252 includes a VAUX terminal that is used to power the volume-setting registers when the device is inSHUTDOWN, and even if the main V
DD
power supply is removed. As long as the VAUX terminal is held above 3V, the registers are maintained. If the VAUX terminal is allowed to go below 3 V, then the data in the registers islost, and the default gain of –10 dB is loaded into the registers.
The TPA0252 consumes only 9 mA of supply current during normal operation. A miserly shutdown modereduces the supply current to 150 µA.
The PowerPAD™ package (PWP) delivers a level of thermal performance that was previously achievable only inTO-220-type packages. Thermal impedances of approximately 35 °C/W are truly realized in multilayer PCBapplications. This allows the TPA0252 to operate at full power into 8- Ωloads at ambient temperatures of 85 °C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ROUT+
-
+
-
+
R
MUX
32-Step
Volume
Control
PC
Beep
MUX
Control Depop
Circuitry Power
Management
-
+
-
+
L
MUX
32-Step
Volume
Control
RHPIN
RLINEIN
DOWN
RIN
PC-BEEP
SE/BTL
LHPIN
LLINEIN
LIN
ROUT-
PVDD
VDD
BYPASS
SHUTDOWN
GND
LOUT+
LOUT-
HP/LINE
32-Step
Volume
Control
32-Step
Volume
Control
UP
40 k40 k
VDD
VDD
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGED DEVICET
A
TSSOP
(1)
(PWP)
-40 °C to 85 °C TPA0252PWP
(1) The PWP package is available taped and reeled. To order a taped and reeled part, add the suffix Rto the part number (e.g., TPA0252PWPR).
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ABSOLUTE MAXIMUM RATINGS
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME NO.
BYPASS 7 Tap to voltage divider for internal mid-supply bias generatorIf a 47-nF capacitor is attached, the TPA0252 generates an internal clock. An external clock can overrideCLK 6 I
the internal clock input to this terminal.A momentary pulse on this terminal decreases the volume level by 2 dB. Holding the terminal low for aDOWN 5 I period of time steps the amplifier through the volume levels at a rate determined by the capacitor on theCLK terminal.GND 12, 24 I Ground connection for circuitry. Connected to thermal padInput MUX control. When terminal is high, the LHPIN and RHPIN inputs are selected. When terminal isHP/ LINE 14 I
low, LLINEIN and RLINEIN inputs are selected.LHPIN 19 I Left-channel headphone input, selected when HP/ LINE is held highLIN 21 I Common left input for fully differential input. AC ground for single-ended inputsLLINEIN 20 I Left-channel line negative input, selected when HP/ LINE is held lowLOUT+ 23 O Left-channel positive output in BTL mode and positive in SE modeLOUT– 1 O Left-channel negative output in BTL mode and high impedance in SE modeThe input for PC beep mode. PC-BEEP is enabled when a > 1.5-V (peak-to-peak) square wave is input toPC-BEEP 10 I
PC-BEEP.PV
DD
3, 8 I Power supply for output stageRHPIN 17 I Right channel headphone input, selected when HP/ LINE is held highRIN 15 I Common right input for fully differential input. AC ground for single-ended inputsRLINEIN 16 I Right-channel line input, selected when HP/ LINE is held lowROUT+ 13 O Right-channel positive output in BTL mode and positive in SE modeROUT– 11 O Right-channel negative output in BTL mode and high impedance in SE modeInput and output MUX control. When this terminal is held high SE outputs are selected. When thisSE/ BTL 22 I
terminal is held low BTL outputs are selected.When held low, this terminal places the entire device, except PC-BEEP detect circuitry, in shutdownSHUTDOWN 2 I
mode.
A momentary pulse on this terminal increases the volume level by 2 dB. Holding the terminal low for aUP 4 I period of time steps the amplifier through the volume levels at a rate determined by the capacitor on theCLK terminal.
Volume control memory supply. Connect to system auxiliary that stays active when device is poweredVAUX 9 I
down.V
DD
18 I Analog V
DD
input supply. This terminal needs to be isolated from PV
DD
to achieve highest performance.Thermal Pad Connect to ground. Must be soldered down in all applications to properly secure device on PC board.
over operating free-air temperature range (unless otherwise noted)
(1)
Supply voltage, V
DD
6 VInput voltage, V
I
-0.3 V to V
DD
+0.3 VContinuous total power dissipation internally limited (see Dissipation Rating Table)Operating free-air temperature range, T
A
-40 °C to 85 °COperating junction temperature range, T
J
-40 °C to 150 °CStorage temperature range, T
stg
-65 °C to 85 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
OPERATING CHARACTERISTICS
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
DISSIPATION RATING TABLE
PACKAGE T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °C
PWP 2.7 W
(1)
21.8 mW/ °C 1.7 W 1.4 W
(1) See the Texas Instruments document, PowerPAD™Thermally Enhanced Package Application Report(literature number SLMA002), for more information on the PowerPAD™ package. The thermal datameasured on a PCB layout based on the information in the section entitled Texas InstrumentsRecommended Board for PowerPAD™ on page 33 of the before mentioned document.
MIN MAX UNIT
Supply voltage, V
DD
4.5 5.5 VVolume control memory supply voltage, V
AUX
3 5.5 VCLK 4.5SE/ BTL, HP/ LINE 0.8 ×V
DDHigh-level input voltage, V
IH
VUP, DOWN 4SHUTDOWN 2SE/ BTL, HP/ LINE 0.6 ×V
DD
Low-level input voltage, V
IL
SHUTDOWN 0.8 VUP, DOWN, CLK 0.5Operating free-air temperature, T
A
-40 85 °C
at specified free-air temperature, V
DD
= 5 V, T
A
= 25 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|V
OS
| Output offset voltage (measured differentially) V
I
= 0, A
V
= 2 V/V 35 mVSupply ripple rejection ratio V
DD
= 4.9 V to 5.1 V 67 dB|I
IH
| High-level input current SE/ BTL, HP/ LINE, SHUTDOWN, UP, DOWN V
DD
= 5.5 V, V
I
= V
DD
1 µASE/ BTL, HP/ LINE, SHUTDOWN 1 µA|I
IL
| Low-level input current V
DD
= 5.5 V, V
I
= 0 VUP, DOWN 125 µABTL mode 9 15I
DD
Supply current mASE mode 4.5 7.5I
DD(SD)
Supply current, shutdown mode 150 300 µAI
DD(VAUX)
Supply current, VAUX pin (see Figure 29 ) VAUX = 5 V, V
DD
= 0 V 0.7 nA
V
DD
= 5 V, T
A
= 25 °C, R
L
= 4 Ω, Gain = 20 dB, BTL mode (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THD = 10% 2.8P
O
Output power R
L
= 3 Ω, f = 1 kHz WTHD = 1% 2.3THD + N Total harmonic distortion plus noise P
O
= 1 W, f = 20 Hz to 15 kHz 0.3%B
OM
Maximum output power bandwidth THD = 5% >15 kHzBTL mode 65f = 1 kHz,k
SVR
Supply ripple rejection ratio dBC
B
= 0.47 µF
SE mode, Gain = 14 dB 60BTL mode, Gain = 6 dB 17C
B
= 0.47 µF,V
n
Noise output voltage µV
RMSf = 20 Hz to 20 kHz
SE mode, Gain = 0 dB 44
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TYPICAL CHARACTERISTICS
0.01%
−40 −30 −20 −10 0
THD+N −Total Harmonic Distortion + Noise
A - Voltage Gain - dB
1%
0.1%
10 20
V
PO = 1 W for AV ≥ 6 dB
VO = 1 VRMS for AV ≤ 4 dB
RL = 8 Ω
BTL
0.1%
0.01%0.5 0.75 1 1.25 1.5 1.75 2
1%
10%
2.25 2.5 2.75 3
PO - Output Power - W
AV = 20 to 0 dB
f = 1 kHz
BTL
THD+N -Total Harmonic Distortion + Noise
RL = 8 ΩRL = 3 Ω
RL = 4 Ω
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
Table of Graphs
FIGURE
vs Output power 1, 4, 6, 8, 10THD+N Total harmonic distortion plus noise vs Voltage gain 2vs Frequency 3, 5, 7, 9, 11, 12V
n
Output noise voltage vs Frequency 13Supply ripple rejection ratio vs Frequency 14, 15Crosstalk vs Frequency 16, 17, 18Shutdown attenuation vs Frequency 19SNR Signal-to-noise ratio vs Frequency 20Closed loop response 21, 22P
O
Output power vs Load resistance 23, 24vs Output power 25, 26P
D
Power dissipation
vs Ambient temperature 27R
I
Input resistance vs Gain 28I
DD(VAUX)
Supply current vs V
AUX
29
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISEvs vsOUTPUT POWER VOLTAGE GAIN
Figure 1. Figure 2.
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0.1%
0.01%
0.01 0.1
1%
10%
1 10
f = 20 Hz
f = 1 kHz
PO - Output Power - W
RL = 3 Ω
AV = 20 to 0 dB
BTL
THD+N -Total Harmonic Distortion + Noise
f = 20 kHz
0.01%
10%
20 100 1k 10k 20k
THD+N -Total Harmonic Distortion + Noise
f - Frequency - Hz
1%
0.1%
RL = 3 Ω
AV = 20 to 0 dB
BTL
PO = 1.75 W
PO = 0.5 W
PO = 1 W
0.1%
0.01%20 100
1%
10%
1k 10k
f - Frequency - Hz
RL = 4 Ω
AV = 20 to 0 dB
BTL
THD+N -Total Harmonic Distortion + Noise
PO= 0.25 W
20k
PO= 1 W
PO=1.5 W
0.1%
0.01%
0.01 0.1
1%
10%
1 10
f = 20 Hz
f = 1 kHz
PO - Output Power - W
THD+N -Total Harmonic Distortion + Noise
f = 20 kHz
RL = 4 Ω
AV = 20 to 0 dB
BTL
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISEvs vsFREQUENCY OUTPUT POWER
Figure 3. Figure 4.
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISEvs vsFREQUENCY OUTPUT POWER
Figure 5. Figure 6.
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0.1%
0.01%
0.01 0.1
1%
10%
1 10
f = 20 Hz
f = 1 kHz
PO - Output Power - W
THD+N -Total Harmonic Distortion + Noise
f = 20 kHz
RL = 8 Ω
AV = 20 to 0 dB
BTL
0.1%
0.01%
20
1%
10%
10k
f - Frequency - Hz
THD+N -Total Harmonic Distortion + Noise
PO = 25 mW
20k
RL = 32 Ω
AV = 14 to 0 dB
SE
100 1k
0.001%
PO = 50 mW PO = 75 mW
0.1%
0.01%
0.01 0.1
1%
10%
1
f = 20 Hz
f = 1 kHz
PO - Output Power - W
THD+N -Total Harmonic Distortion + Noise
f = 20 kHz
RL = 32 Ω
AV = 14 to 0 dB
SE
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISEvs vsFREQUENCY OUTPUT POWER
Figure 7. Figure 8.
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISEvs vsFREQUENCY OUTPUT POWER
Figure 9. Figure 10.
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THD+N -Total Harmonic Distortion + Noise
f = 20 kHz
VO - Output Voltage - VRMS
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0.001%
0.01%
0.1%
1%
10%
RL = 10 kΩ
AV = 14 to 0 dB
SE
f = 1 kHz
f = 20 Hz
0.001%
10%
20 100 1k 10k 20k
THD+N -Total Harmonic Distortion + Noise
f - Frequency - Hz
1%
0.1%
VO = 1 VRMS
0.01%
RL = 10 kΩ
AV = 14 to 0 dB
SE
120
00 100
140
160
1k 10k
f - Frequency - Hz
VDD = 5 V
BW = 22 Hz to 22 kHz
RL = 4 Ω
AV = 20 dB
20k
AV = 6 dB
- Output Noise Voltage - VµVnRMS
20
40
60
80
100
-100
-120 20 100
-80
1k 10k
RL = 8 Ω
CB = 0.47 µF
BTL
AV = 6 dB
-60
-40
-20
0
f - Frequency - Hz 20k
AV = 20 dB
Supply Ripple Rejection Ratio - dB
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISEvs vsFREQUENCY OUTPUT VOLTAGE
Figure 11. Figure 12.
OUTPUT NOISE VOLTAGE SUPPLY RIPPLE REJECTION RATIOvs vsFREQUENCY FREQUENCY
Figure 13. Figure 14.
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-100
-120 20 100
-80
1k 10k
RL = 32 Ω
CB = 0.47 µF
SE
AV = 6 dB
-60
-40
-20
0
f - Frequency - Hz 20k
AV = 14 dB
Supply Ripple Rejection Ratio - dB
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
SUPPLY RIPPLE REJECTION RATIO CROSSTALKvs vsFREQUENCY FREQUENCY
Figure 15. Figure 16.
CROSSTALK CROSSTALKvs vsFREQUENCY FREQUENCY
Figure 17. Figure 18.
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-10
20
10 100 1k 10k 100k
Gain - dB
f - Frequency - Hz
15
10
5
25
30
-5
0
180°
90°
0°
-90°
-180°
1M
Phase
RL = 8 Ω
AV = 20 dB
BTL Gain
Phase
-10
20
10 100 1k 10k 100k
Gain - dB
f - Frequency - Hz
15
10
5
25
30
-5
0
180°
90°
0°
-90°
-180°
1M
RL = 8 Ω
AV = 6 dB
BTL
Gain
Phase
Phase
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
SHUTDOWN ATTENUATION SIGNAL-TO-NOISE RATIOvs vsFREQUENCY FREQUENCY
Figure 19. Figure 20.
CLOSED LOOP RESPONSE CLOSED LOOP RESPONSE
Figure 21. Figure 22.
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2
1.5
00 8 16 24 32 40
2.5
3
3.5
48 56 64
RL - Load Resistance - Ω
AV = 20 to 0 dB
BTL
- Output Power - WPO
1% THD+N
10% THD+N
1
0.5
750
00 8 16
1000
1250
1500
24 32
RL - Load Resistance - Ω
AV = 14 to 0 dB
SE
- Output Power - mWPO
1% THD+N
10% THD+N
500
250
40 48 56 64
0.6
0.4
0.2
00 1
- Power Dissipation - W
1
1.2
1.4
1.5 2.5
0.8
PO - Output Power - W
PD
4 Ω
8 Ω
f = 1 kHz
BTL
Each Channel
3 Ω
1.6
1.8
0.5 2
0.1
0.05
00 0.2
- Power Dissipation - W
0.2
0.25
0.3
0.3 0.8
0.15
PO - Output Power - W
PD
8 Ω
32 Ωf = 1 kHz
SE
Each Channel
4 Ω
0.35
0.4
0.1 0.70.4 0.5 0.6
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
OUTPUT POWER OUTPUT POWERvs vsLOAD RESISTANCE LOAD RESISTANCE
Figure 23. Figure 24.
POWER DISSIPATION POWER DISSIPATIONvs vsOUTPUT POWER OUTPUT POWER
Figure 25. Figure 26.
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40
30
20
10
-40 -20
- Input Resistance - k
60
70
80
-10 10
50
AV - Gain - dB
RI
90
-30 0
Ω
20
1
0
-40 0
- Power Dissipation - W
3
4
5
20 160
2
TA - Ambient Temperature - °C
PD
6
7
-20 10040 60 80 120 140
ΘJA3
ΘJA1,2
ΘJA4 ΘJA1 = 45.9°C/W
ΘJA2 = 45.2°C/W
ΘJA3 = 31.2°C/W
ΘJA4 = 18.6°C/W
0.6
0.4
0.2
0.00 2
- Supply Current - nA
1.0
1.2
1.4
3 5
0.8
VAUX - V
IDD(VAUX)
1.6
1 41.5 2.5 4.50.5 3.5 5.5
125°C
25°C
-40°C
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
POWER DISSIPATION INPUT RESISTANCEvs vsAMBIENT TEMPERATURE GAIN
Figure 27. Figure 28.
SUPPLY CURRENT
vs
V
AUX
Figure 29.
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APPLICATION INFORMATION
Component Selection
ROUT+ 13
R
MUX
RHPIN
RLINEIN
+
-
16
17
CIRHP
0.47 µF
Right
Head-
phone
Input
Signal CIRLINE
0.47 µF
Right
Line
Input
Signal
CRIN
0.47 µF
15 RIN
ROUT- 11
+
-1 kΩ
COUTR
330 µF
100 kΩ
L
MUX
LHPIN
LLINEIN20
19
CILHP
0.47 µF
Left
Head-
phone
Input
Signal CILLINE
0.47 µF
Left
Line
Input
Signal
CLIN
0.47 µF
21 LIN
1 kΩ
COUTL
330 µF
VDD
100 kΩ
Depop
Circuitry
Power
Management
PVDD 8
VDD 18
BYPASS 7
SHUT-
DOWN 5
GND
LOUT+ 23
+
-
LOUT- 1
+
-
CBYP
0.47 µF
12, 24
To
System
Control
CSR
0.1 µF
VDD
CSR
0.1 µF
VDD
See Note A
PC-
Beep
PC-BEEP
SE/BTL
10
CPCB
0.47 µF
PC-BEEP
Input
Signal
4Gain/
MUX
Control
UP
CLK
5
6
CCLK
47 nF
VDD
100 kΩ
32-Step
Volume
Control
32-Step
Volume
Control
32-Step
Volume
Control
32-Step
Volume
Control
DOWN
22
UpDown
100 kΩHP/LINE
Gain
Memery VAUX 9
0.47 µF
VDD
System VAUX
14
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
Figure 30 and Figure 31 are schematic diagrams of typical notebook computer application circuits.
A. A 0.47 µF ceramic capacitor must be placed as close as possible to the IC. For filtering lower-frequency noisesignals, a larger electrolytic capacitor of 10 µF or greater must be placed near the audio power amplifier.
Figure 30. Typical TPA0252 Application Circuit Using Single-Ended Inputs and Input MUX
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CCLK
47 nF
SE/BTL
ROUT+ 13
R
MUX
RHPIN
RLINEIN
+
-
16
17
CIRIN-
0.47 µF
15 RIN
ROUT- 11
+
-1 kΩ
COUTR
330 µF
100 kΩ
L
MUX
LHPIN
LLINEIN20
19
CILIN-
0.47 µF
21 LIN
1 kΩ
COUTL
330 µF
VDD
100 kΩ
Depop
Circuitry
Power
Management
PVDD 3
VDD 18
BYPASS 7
SHUT-
DOWN 2
GND
LOUT+ 23
+
-
LOUT- 1
+
-
CBYP
0.47 µF
12, 24
To
System
Control
CSR
0.1 µF
VDD
CSR
0.1 µF
VDD
See Note A
PC-
Beep
PC-BEEP10
CPCB
0.47 µF
PC-BEEP
Input Signal
Gain/
MUX
Control
UP
CLK
5
6
4
CIRIN+
0.47 µF
22
CILIN+
0.47 µF
32-Step
Volume
Control
32-Step
Volume
Control
32-Step
Volume
Control
32-Step
Volume
Control
VDD
100 kΩ
UpDown
100 kΩ
DOWN
CLHP-
0.47 µF
Gain
Memory VAUX 9
0.47 µF
VDD
System
VAUX
HP/LINE
14
NC
Right
Positive
Differential
Input Signal
Right
Negative
Differential
Input Signal
Left
Positive
Differential
Input Signal
Left
Negative
Differential
Input Signal
NC
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
Application Information (continued)
A. A 0.47 µF ceramic capacitor must be placed as close as possible to the IC. For filtering lower-frequency noisesignals, a larger electrolytic capacitor of 10 µF or greater must be placed near the audio power amplifier.
Figure 31. Typical TPA0252 Application Circuit Using Differential Inputs
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UP/DOWN VOLUME CONTROL
Changing Volume
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
Application Information (continued)
The default volume is set at mute mode. The volume is increased in 2-dB steps by pulling the UP terminal low.The volume is decreased in 2-dB steps by pulling the DOWN terminal low. If power is removed, the device resetsto mute mode.
Volume Settings
VOLUME CONTROL
BTL (dB) SE (dB)
20 1418 1216 1014 812 610 48 26 04 -22 -40 -6-2 -8-4 -10-6 -12-8 -14-10 -16-12 -18-14 -20-16 -22-18 -24-20 -26-22 -28-24 -30-26 -32-28 -34-30 -36-32 -38-34 -40-36 -42-38 -44-40 -46-85 -91
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Changing Volume When Using the Internal Clock
fCLK 4.710–6
CCLK
(1)
CLK
VOLUME
40 cycles 20 cycles 12 cycles 4 cycles per step
4 cycles
UP
8 cycles
Changing Volume When Using the External Clock (Microprocessor Mode)
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
If using the internal clock, the maximum clock frequency is 500 Hz and the recommended frequency is 100 Hzusing a 47-nF capacitor. Use Equation 1 to calculate the clock frequency if using a capacitor to generate theclock.
When the desired volume-control signal is pulled low for four clock cycles, the volume increments by one step,followed by a short delay. This delay decreases the longer the line is held low, eventually reaching a delay ofzero. The delay allows the user to pull the UP or DOWN terminal low once for one volume change, or hold downto ramp several volume changes. The delay is optimally configured for push button volume control.
Holding either UP or DOWN low continuously causes the volume to change at an exponentially increasing rate.When f
CLK
= 100 Hz, the first change in the volume occurs approximately 40 ms after either pin is initially pulledlow. If the pin stays low for approximately 400 more ms, the volume changes again. The next change occurs 200ms after this change. The fourth change occurs 120 ms after the third change. The fifth volume change occurs80 ms after the fourth change. Thereafter, the volume changes at 1/4 the rate of the clock (every 40 ms).
Each cycle is registered on the rising clock edge and the volume is changed after the rising edge.
Figure 32 shows increasing volume using UP, however, the volume is decreased using DOWN with the sametiming.
Figure 32. Internal Clock Timing Diagram
The user may remove the capacitor and run the external clock directly into the clock pin to override the internalclock generator. The maximum clock frequency is 10 kHz if using an external clock; however, a clock frequencyless than 200 Hz is recommended in normal operation so the gain does not change too quickly causing a pop atthe output. A 5-V, 50% duty-cycle clock must be used because the trip levels are 0.5 V and 4.5 V. Therecommended way to adjust the volume is to use a gated clock and hold UP or DOWN low and cycle the clockpin four times to adjust the volume. The volume change is clocked in at the rising edge, so CLK should be heldlow when not changing volume. No delay is added when using an external clock, so it is very important to inputonly four clock cycles per volume change. Additional clock cycles per volume change are added to the nextvolume change. For example, if five clock cycles are input while UP is held low the first volume change, thevolume change occurs after the third clock cycle the next time UP is held low. The figure below shows howvolume increases with UP when an external clock is used. The sample and hold times for UP and DOWN are100 ns. The same timing applies if using an external clock and decreasing the volume with DOWN.
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CLK
VOLUME
4 cycles per step
UP
V
AUX
VDD
System
VAUX
CVAUX
VAUX
9
INPUT RESISTANCE
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
Figure 33. External Clock (4 Cycles Per Volume Change)
VAUX is used to keep power to the volume control memory. As long as the voltage at the VAUX pin is greaterthan 3 V, the device remembers what volume setting it was in, even when shut-down or powered down. Theamplifier then returns to that volume setting after being powered up. If VAUX is pulled low, the device resets to avolume setting of -10 dB in BTL and -16 dB in SE mode. If VAUX is pulled below ground, the device could bedamaged. Even if VAUX is connected to just one voltage, it must be connected through a diode so VAUX is notpulled below ground. The recommended circuit to keep VAUX high when power down is shown below.
To ensure proper operation, the V
AUX
voltage must not drop below 1.5 V. If the voltage falls below 1.5 V, thestability of the TPA0252 could be compromised. However, this does not damage the device; normal functionalityresumes once the V
AUX
voltage is at or above 1.5 V.
Figure 34. Recommended System VAUX Circuit
The diodes in Figure 34 need to have a low threshold voltage and low leakage current. This circuit allows VAUXto remain high even when V
DD
and system V
AUX
are removed. The formula for calculating how long the volume isremembered if V
DD
and system V
AUX
is removed or pulled low is shown below. The diode used in the examplehas a forward voltage, V
F
of 0.7 V and 25 nA of leakage current, I
R
.•t
decay
= C
VAUX
×((V
DD
or system V
AUX
)-V
F
- VAUXmin) / (2 ×I
R
+ I
DD(VAUX)
)•t
decay
= 0.47 µF ×(5V - 0.7 V - 3V)/(25 nA ×2 + 0.7 nA)•t
decay
= 12 seconds
The gain is set by varying the input resistance of the amplifier, which can range from its smallest value to oversix times that value. As a result, if a single capacitor is used in the input high pass filter, the –3 dB or cut-offfrequency also changes by over six times. Connecting an additional resistor from the input pin of the amplifier toground, as shown in Figure 35 , reduces the cutoff-frequency variation.
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C
R
IN Ri
Rf
Input Signal
ƒ–3 dB 1
2CRRi
(2)
Input Capacitor, C
i
fc(highpass) 1
2ZiCi
-3 dB
fc
(3)
Ci1
2Zifc
(4)
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
Figure 35. Resistor on Input for Cut-Off Frequency
The input resistance at each gain setting is given in the graph for Input Impedance vs Gain in the TypicalCharacteristics section.
The –3-dB frequency can be calculated using Equation 2 .
To increase filter accuracy, increase the value of the capacitor and decrease the value of the resistor to ground.In addition, the order of the filter can be increased.
In the typical application an input capacitor, C
i
, is required to allow the amplifier to bias the input signal to theproper dc level for optimum operation. In this case, C
i
and the input impedance of the amplifier, Z
i
, form ahigh-pass filter with the corner frequency determined in Equation 3 .
The value of C
i
is important to consider as it directly affects the bass (low frequency) performance of the circuit.Consider the example where Z
i
is 15 k Ω(from Figure 28 ) and the specification calls for a flat bass responsedown to 40 Hz. Equation 3 is reconfigured as Equation 4 .
In this example, C
i
is 0.27 µF, so one would likely choose a value in the range of 0.27 µF to 1 µF. A furtherconsideration for this capacitor is the leakage path from the input source through the input network (C
i
) and thefeedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier thatreduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramiccapacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor faces theamplifier input in most applications as the dc level there is held at V
DD
/2, which is likely higher than the source dclevel. Note that it is important to confirm the capacitor polarity in the application.
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POWER SUPPLY DECOUPLING, C
(S)
MIDRAIL BYPASS CAPACITOR, C
(BYP)
OUTPUT COUPLING CAPACITOR, C
(C)
fc(high) 1
2RLC(C)
−3 dB
fc
(5)
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
This high-performance CMOS audio amplifier requires adequate power-supply decoupling to minimize outputtotal harmonic distortion (THD). Power-supply decoupling also prevents oscillations with long lead lengthsbetween the amplifier and the speaker. Optimum decoupling is achieved by using two capacitors of differenttypes that target different types of noise on the power-supply leads. To filter high-frequency transients, spikes, ordigital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF, placedas close as possible to the device V
DD
lead, works best. For filtering low-frequency noise signals, an aluminumelectrolytic capacitor of 10 µF or greater placed near the audio power amplifier is recommended.
The midrail bypass capacitor, C
(BYP)
, is the most critical capacitor and serves several important functions. Duringstartup or recovery from shutdown mode, C
(BYP)
determines the rate at which the amplifier starts up. The secondfunction is to reduce power-supply noise coupling into the output drive signal. This noise is from the midrailgeneration circuit internal to the amplifier, and appears as degraded PSRR and THD+N.
Bypass capacitor (C
(BYP)
) values of 0.47-µF to 1-µF, and ceramic or tantalum low-ESR capacitors arerecommended for best THD and noise performance.
In a typical single-supply SE configuration, an output coupling capacitor (C
(C)
) is required to block the dc bias atthe output of the amplifier to prevent dc currents in the load. As with the input coupling capacitor, the outputcoupling capacitor and impedance of the load form a high-pass filter governed by Equation 5 .
The main disadvantage, from a performance standpoint, is that load impedances are typically small, driving thelow-frequency corner higher, degrading the bass response. Large values of C
(C)
are required to pass lowfrequencies into the load. Consider the example where a C
(C)
of 330 µF is chosen and loads include 3 Ω, 4 Ω, 8Ω, 32 Ω, 10 k Ω, and 47 k Ω. Table 1 summarizes the frequency response characteristics of each configuration.
Table 1. Common Load Impedances Vs Low FrequencyOutput Characteristics in SE Mode
R
L
C
(C)
LOWEST FREQUENCY
3Ω330 µF 161 Hz4Ω330 µF 120 Hz8Ω330 µF 60 Hz32 Ω330 µF 15 Hz10,000 Ω330 µF 0.05 Hz47,000 Ω330 µF 0.01 Hz
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USING LOW-ESR CAPACITORS
BRIDGED-TIED LOAD VS SINGLE-ENDED MODE
Power V(rms)2
RL
V(rms) VO(PP)
2 2
(6)
RL2x VO(PP)
VO(PP)
−VO(PP)
VDD
VDD
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
As Table 1 indicates, most of the bass response is attenuated into a 4- Ωload, an 8- Ωload is adequate,headphone response is good, and drive into line level inputs (a home stereo for example) is exceptional.
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across thisresistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of thisresistance the more the real capacitor behaves like an ideal capacitor.
Figure 36 shows a Class-AB audio power amplifier (APA) in a BTL configuration. The TPA0252 amplifier consistsof two Class-AB amplifiers driving both ends of the load. There are several potential benefits to this differentialdrive configuration, but, initially consider power to the load. The differential drive to the speaker means that asone side is slewing up, the other side is slewing down, and vice versa. This in effect doubles the voltage swingon the load as compared to a ground referenced load. Substituting 2 ×V
O(PP)
into the power equation, wherevoltage is squared, yields 4 ×the output power from the same supply rail and load impedance (see Equation 6 ).
Figure 36. Bridge-Tied Load Configuration
In a typical computer sound channel operating at 5 V, bridging raises the power into an 8- Ωspeaker from asingled-ended (SE, ground reference) limit of 250 mW to 1 W. In sound power, this is a 6-dB improvement —loudness that can be heard. In addition to increased power there are frequency-response concerns. Consider thesingle-supply SE configuration shown in Figure 37 . A coupling capacitor is required to block the dc offset voltagefrom reaching the load. These capacitors can be quite large (approximately 33 µF to 1000 µF), so they tend to beexpensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting the low-frequencyperformance of the system. This frequency-limiting effect is due to the high-pass filter network created with thespeaker impedance and the coupling capacitance, and is calculated with Equation 7 .
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f(c) 1
2RLC(C)
(7)
RL
C(C) VO(PP)
VO(PP)
VDD
−3 dB
fc
Single-Ended Operation
BTL AMPLIFIER EFFICIENCY
V(LRMS)
VOIDD
IDD(avg)
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
For example, a 68-µF capacitor with an 8- Ωspeaker would attenuate low frequencies below 293 Hz. The BTLconfiguration cancels the dc offsets, eliminating the need for blocking capacitors. Low-frequency performance isthen limited only by the input network and speaker response. Cost and PCB space are also minimized byeliminating the bulky coupling capacitor.
Figure 37. Single-Ended Configuration and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increaseddissipation is understandable, since the BTL configuration produces 4 ×the output power of the SE configuration.Internal dissipation versus output power is discussed further in the Crest Factor and Thermal Considerationssection.
In SE mode (see Figure 37 ), the load is driven from the primary amplifier output for each channel (LOUT+ andROUT+).
The amplifier switches to single-ended operation when the SE/ BTL terminal is held high. This puts the negativeoutputs in a high-impedance state, and reduces the amplifier's gain by 6 dB.
Class-AB amplifiers are inefficient, primarily because of voltage drop across the output-stage transistors. The twocomponents of the internal voltage drop are the headroom or dc voltage drop that varies inversely to outputpower, and the sine wave nature of the output. The total voltage drop can be calculated by subtracting the RMSvalue of the output voltage from V
DD
. The internal voltage drop multiplied by the RMS value of the supply current(I
DD
rms) determines the internal power dissipation of the amplifier.
An easy-to-use equation to calculate efficiency begins as the ratio of power from the power supply to the powerdelivered to the load. To accurately calculate the RMS and average values of power in the load and in theamplifier, the current and voltage waveforms must be understood (see Figure 38 ).
Figure 38. Voltage and Current Waveforms for BTL Amplifiers
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Efficiency of a BTL amplifier PL
PSUP
Where:
PLVLrms2
RL, andVLRMS VP
2
, therefore, PLVP2
2RL
and PSUP VDD IDDavg and IDDavg 1
0
VP
RLsin(t) dt 1
VP
RL[cos(t)]
02VP
RL
Therefore,
PSUP 2 VDD VP
RL
substituting PL and PSUP into equation 7,
Efficiency of a BTL amplifier
VP2
2 RL
2 VDD VP
RL
VP
4 VDD
VP2 PLRL
Where:
(8)
PL = Power delivered to load
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
BTL
2 PLRL
4 VDD
Therefore,
VP = Peak voltage on BTL load
IDDavg = Average current drawn from the power supply
VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
(9)
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are verydifferent between SE and BTL configurations. In an SE application, the current waveform is a half-wave rectifiedshape, whereas in BTL it is a full-wave rectified waveform. Therefore, RMS conversion factors are different. Keepin mind that for most of the waveform both the push and pull transistors are not on at the same time, whichsupports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform.Equation 8 and Equation 9 are the basis for calculating amplifier efficiency.
Table 2 employs Equation 9 to calculate efficiencies for four different output-power levels. Note that the efficiencyof the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting ina nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at fulloutput power is less than in the half-power range. Calculating the efficiency for a specific system is the key toproper power supply design. For a stereo 1-W audio system with 8- Ωloads and a 5-V supply, the maximum drawon the power supply is almost 3.25 W.
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Crest Factor and Thermal Considerations
PdB 10Log PW
Pref
10Log 4 W
1 W 6 dB
(10)
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
Table 2. Efficiency vs Output Power in 5-V, 8- ΩBTL Systems
EFFICIENCYOUTPUT POWER (W) PEAK VOLTAGE (V) INTERNAL DISSIPATION (W)(%)
0.25 31.4 2.00 0.550.50 44.4 2.83 0.621.00 62.8 4.00 0.591.25 70.2 4.47
(1)
0.53
(1) High peak voltages cause the THD to increase.
A final point to remember about Class-AB amplifiers (either SE or BTL) is how to manipulate the terms in theefficiency equation to utmost advantage when possible. Note that in Equation 9 , V
DD
is in the denominator. Thisindicates that as V
DD
goes down, efficiency goes up.
Class-AB power amplifiers dissipate a significant amount of heat in the package under normal operatingconditions. A typical music CD requires 12 dB to 15 dB of dynamic range, or headroom, above the averagepower output, to pass the loudest portions of the signal without distortion. In other words, music typically has acrest factor between 12 dB and 15 dB. When determining the optimal ambient operating temperature, the internaldissipated power at the average output power level must be used. From the data sheet, one can see that whenthe device is operating from a 5-V supply into a 3- Ωspeaker that 4-W peaks are available. Use Equation 10 toconvert watts to dB.
Subtracting the headroom restriction to obtain the average listening level without distortion yields:6 dB - 15 dB = -9 dB (15-dB crest factor)6 dB - 12 dB = -6 dB (12-dB crest factor)6 dB - 9 dB = -3 dB (9-dB crest factor)6 dB - 6 dB = 0 dB (6-dB crest factor)6 dB - 3 dB = 3 dB (3-dB crest factor)
Converting dB back into watts:P
W
= 10
PdB/10
×P
ref= 63 mW (18-dB crest factor)= 125 mW (15-dB crest factor)= 250 mW (9-dB crest factor)= 500 mW (6-dB crest factor)= 1000 mW (3-dB crest factor)= 2000 mW (0-dB crest factor)
This is valuable information to consider when estimating the heat-dissipation requirements for the amplifiersystem. Comparing the worst case, 2 W of continuous power output with a 3-dB crest factor, against 12-dB and15-dB applications, drastically affects maximum ambient temperature ratings for the system. Using the powerdissipation curves for a 5-V, 3- Ωsystem, the internal dissipation and maximum ambient temperatures are shownin the table below.
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PDmax
2V2
DD
2RL
(11)
θJA 1
Derating Factor 1
0.022 45°CW
(12)
TAMax TJMax θJA PD
150 45(0.6 2)96°C(15-dB crest factor)
(13)
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
Table 3. TPA0252 Power Rating, 5-V, 3- Ω, Stereo
PEAK OUTPUT POWER POWER DISSIPATION MAXIMUM AMBIENTAVERAGE OUTPUT POWER(W) (W/Channel) TEMPERATURE
(1)
4 2 W (3 dB) 1.7 -3 °C4 1000 mW (6 dB) 1.6 6 °C4 500 mW (9 dB) 1.3 24 °C4 250 mW (12 dB) 1.0 51 °C4 125 mW (15 dB) 0.9 78 °C4 63 mW (18 dB) 0.6 85 °C
(1)
(1) Package limited to 85 °C ambient
Table 4. TPA0252 Power Rating, 5-V, 8- Ω, Stereo
PEAK OUTPUT POWER POWER DISSIPATION MAXIMUM AMBIENTAVERAGE OUTPUT POWER(W) (W/Channel) TEMPERATURE
2.5 1250 mW (3-dB crest factor) 0.53 85 °C
(1)
2.5 1000 mW (4-dB crest factor) 0.59 85 °C
(1)
2.5 500 mW (7-dB crest factor) 0.62 85 °C
(1)
2.5 250 mW (10-dB crest factor) 0.55 85 °C
(1)
(1) Package limited to 85 °C ambient
The maximum dissipated power (P
Dmax
) is reached at a much lower output power level for a 3- Ωload than for an8- Ωload. As a result, the formula in Equation 11 for calculating P
Dmax
may be used for a 3- Ωapplication:
However, in the case of an 8- Ωload, the P
Dmax
occurs at a point well above the normal operating power level.The amplifier may therefore be operated at a higher ambient temperature than required by the P
Dmax
formula foran 8- Ωload, but do not exceed the maximum ambient temperature of 85 °.
The maximum ambient temperature depends on the heatsinking ability of the PCB system. The derating factorfor the PWP package is shown in the dissipation rating table. Converting this to θ
JA
:
To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs areper-channel, so the dissipated heat is doubled for two-channel operation. Given θ
JA
, the maximum allowablejunction temperature, and the total internal dissipation, the maximum ambient temperature can be calculatedusing Equation 13 . The maximum recommended junction temperature for the device is 150 °C. The internaldissipation figures are taken from the Power Dissipation vs Output Power graphs.
NOTE:
Internal dissipation of 0.6 W is estimated for a 2-W system with 15-dB crest factor perchannel.
Due to package limitiations, the actual T
AMAX
is 85 °C.
The power rating tables show that for some applications, no airflow is required to keep junction temperatures inthe specified range. The internal thermal protection turns the device off at junction temperatures higher than150 °C to prevent damage to the IC. The power rating tables in this section were calculated for maximumlistening volume without distortion. When the output level is reduced the numbers in the table changesignificantly. Also, using 8- Ωspeakers dramatically increases the thermal performance by increasing amplifierefficiency.
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PC-BEEP OPERATION
CPCB 1
2ƒPCB (100 k)
(14)
SE/ BTL Operation
ROUT+ 13
R
MUX
RHPIN
RLINEIN
+
-
16
17
15 RIN
ROUT- 11
+
-1 kΩ
COUTR
330 µF
100 kΩ
SE/BTL 22
100 kΩ
VDD
32-Step
Volume
Control
32-Step
Volume
Control
14
HP/LINE
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
The PC-BEEP input allows a system beep to be sent directly from a computer through the amplifier to thespeakers with few external components. The input is activated automatically. When the PC-BEEP input is active,both LINEIN and HPIN inputs are deselected, and both the left and right channels are driven in BTL mode withthe signal from PC-BEEP. The gain from the PC-BEEP input to the speakers is fixed at 0.3 V/V and isindependent of the volume setting. When the PC-BEEP input is deselected, the amplifier returns to the previousoperating mode and volume setting. Furthermore, if the amplifier is in shutdown mode, activating PC-BEEP takesthe device out of shutdown, outputs the PC-BEEP signal, then returns the amplifier to shutdown mode.
The preferred input signal is a square wave or pulse train. To be accurately detected, the signal must have aminimum of 1.5-V
pp
amplitude, rise and fall times of less than 0.1 µs and a minimum of eight rising edges. Whenthe signal is no longer detected, the amplifier returns to its previous operating mode and volume setting.
To ac-couple the PC-BEEP input, choose a coupling-capacitor value to satisfy Equation 14 .
The PC-BEEP input can also be dc-coupled to avoid using this coupling capacitor. The pin normally rests atmidrail when no signal is present.
The ability of the TPA0252 to easily switch between BTL and SE modes is one of its most important cost savingfeatures. This feature eliminates the requirement for an additional headphone amplifier in applications whereinternal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated.Internal to the TPA0252, two separate amplifiers drive OUT+ and OUT–. The SE/ BTL input (terminal 22) controlsthe operation of the follower amplifier that drives LOUT– and ROUT– (terminals 1 and 11). When SE/ BTL is heldlow, the amplifier is on and the TPA0252 is in the BTL mode. When SE/ BTL is held high, the OUT– amplifiersare in a high output impedance state, which configures the TPA0252 as an SE driver from LOUT+ and ROUT+(terminals 23 and 13). I
DD
is reduced by approximately one-half in SE mode. Control of the SE/ BTL input can befrom a logic-level CMOS source or, more typically, from a resistor divider network as shown in Figure 39 .
Figure 39. TPA0252 Resistor Divider Network Circuit
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Input MUX Operation
ROUT+ 13
R
MUX
RHPIN
RLINEIN
+
−
16
17
15 RIN
ROUT− 11
+
−
SE/BTL 22
32-Step
Volume
Control
32-Step
Volume
Control
14
HP/LINE
CIRHP
0.47 µF
Right
Head−phone
Input Signal
CIRLINE
0.47 µF
Right Line
Input Signal
CRIN
0.47 µF
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
Using a readily available 1/8-in. (3.5 mm) stereo headphone jack, the control switch is closed when no plug isinserted. When closed, the 100-k Ω/1-k Ωdivider pulls the SE/ BTL input low. When a plug is inserted, the 1-k Ωresistor is disconnected and the SE/ BTL input is pulled high. When the input goes high, the OUT– amplifier isshut down causing the speaker to mute (virtually open-circuits the speaker). The OUT+ amplifier then drivesthrough the output capacitor (C
OUT
) into the headphone jack.
Figure 40. TPA0252 Example Input MUX Circuit
The TPA0252 offers the capability for the designer to use separate headphone inputs (RHPIN, LHPIN) and lineinputs (RLINEIN, LLINEIN). The inputs can be different if the input signal is single-ended. If using a differentialinput signal, the inputs must be the same because the inputs share a common RIN, LIN. Although the typicalapplication in Figure 30 shows the input mux control signal HP/LINE tied to SE/BTL, that configuration is notrequired. The input mux can be used to select between two inputs that are used in both SE and BTL modes.
If using the TPA0232 with a single-ended input, the RIN and LIN terminals must be tied through a capacitor toground, as shown in Figure 40 . RIN and LIN must not be tied to bypass or an offset occurs on the output causingthe device to pop when turning on and off.
Input coupling capacitors can be eliminated when using differential inputs, but are used to obtain maximumoutput power. If the input capacitors are eliminated, the dc offset must match the voltage on BYPASS or theoutput power is limited.
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Shutdown Modes
TPA0252
SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004
The TPA0252 employs a shutdown mode of operation designed to reduce supply current, I
DD
, to the absoluteminimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal is heldhigh during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to muteand the amplifier to enter a low-current state, I
DD
= 150 µA. SHUTDOWN must never be left unconnectedbecause amplifier operation would be unpredictable.
Shutdown and Mute Mode Functions
INPUTS
(1)
AMPLIFIER STATE
SE/ BTL HP/ LINE SHUTDOWN INPUT OUTPUT
Low Low High L/R Line BTLX X Low X MuteLow High High L/R HP BTLHigh Low High L/R Line SEHigh High High L/R HP SE
(1) Inputs must never be left unconnected.
27
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPA0252PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA0252PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA0252PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA0252PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
www.ti.com 5-Oct-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPA0252PWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA0252PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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