MCM44100B•MCM4L4100B
12 MOTOROLA DRAM
DEVICE INITIALIZATION
On power–up, an initial pause of 100 microseconds is
required for the internal substrate generator to establish the
correct bias voltage. This must be followed by a minimum of
eight active cycles of the row address strobe (clock) to
initialize all dynamic nodes within the RAM. During an
extended inactive state (greater than 16 milliseconds or 128
milliseconds in case of low power device, with the device
powered up), a wakeup sequence of eight active cycles is
necessary to ensure proper operation.
ADDRESSING THE RAM
The eleven address pins on the device are time multi-
plexed at the beginning of a memory cycle by two clocks,
row address strobe (RAS) and column address strobe
(CAS), into two separate 11–bit address fields. A total of
twenty–two address bits, eleven rows and eleven columns,
will decode one of the 4,194,304 bit locations in the device.
RAS active transition is followed by CAS active transition
(active = VIL, tRCD minimum) for all read or write cycles. The
delay between RAS and CAS active transitions, referred to
as the multiplex window, gives a system designer flexibility
in setting up the external addresses into the RAM.
The external CAS signal is ignored until an internal RAS
signal is available. This “gate” feature on the external CAS
clock enables the internal CAS line as soon as the row
address hold time (tRAH) specification is met (and defines
tRCD minimum). The multiplex window can be used to
absorb skew delays in switching the address bus from row
to column addresses and in generating the CAS clock.
There are three other variations in addressing the 4M
RAM: RAS–only refresh cycle, CAS before RAS refresh
cycle, and page mode.
READ CYCLE
The DRAM may be read with four different cycles: “nor-
mal” random read cycle, page mode read cycle, read–write
cycle, and page mode read–write cycle. The normal read
cycle is outlined here, while the other cycles are discussed
in separate sections.
The normal read cycle begins as described in ADDRESS-
ING THE RAM, with RAS and CAS active transitions latch-
ing the desired bit location. The write (W) input level must be
high (VIH), tRCS (minimum) before the CAS active transition,
to enable read mode.
Both the RAS and CAS clocks trigger a sequence of
events that are controlled by several delayed internal clocks.
The internal clocks are linked in such a manner that the read
access time of the device is independent of the address mul-
tiplex window; however, CAS must be active before or at
tRCD maximum to guarantee valid data out (Q) at tRAC
(access time from RAS active transition). If the tRCD maxi-
mum is exceeded, read access time is determined by the
CAS clock active transition (tCAC).
The RAS and CAS clocks must remain active for mini-
mum times of tRAS and tCAS, respectively, to complete the
read cycle. W must remain high throughout the cycle, and
for time tRRH or tRCH after RAS or CAS inactive transition,
respectively, to maintain the data at that bit location. Once
RAS transitions to inactive, it must remain inactive for a
minimum time of tRP to precharge the internal device cir-
cuitry for the next active cycle. Q is valid, but not latched, as
long as the CAS clock is active. When the CAS clock transi-
tions to inactive, the output will switch to High–Z (three–
state).
WRITE CYCLE
The user can write to the DRAM with any of four cycles:
early write, late write, page mode early write, and page
mode read–write. Early and late write modes are discussed
here, while page mode write operations are covered
elsewhere.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of W to active
(VIL). Early and late write modes are distinguished by the
active transition of W, with respect to CAS. Minimum active
time tRAS and tCAS, and precharge time tRP apply to write
mode, as in the read mode.
An early write cycle is characterized by W active transition
at minimum time tWCS before CAS active transition. Data
in (D) is referenced to CAS in an early write cycle. RAS
and CAS clocks must stay active for tRWL and tCWL,
respectively, after the start of the early write operation to
complete the cycle.
Q remains in three–state condition throughout an early
write cycle because W active transition precedes or coin-
cides with CAS active transition, keeping data–out buffers
disabled. This feature can be utilized on systems with a
common I/O bus, provided all writes are performed with
early write cycles, to prevent bus contention.
A late write cycle occurs when W active transition is made
after CAS active transition. W active transition could be
delayed for almost 10 microseconds after CAS active tran-
sition, (tRCD + tCWD + tRWL + 2tT) ≤ tRAS, if other timing
minimums (tRCD, tRWL, and tT) are maintained. D is refer-
enced to W active transition in a late write cycle. Output
buffers are enabled by CAS active transition but Q may be
indeterminate (see note 17 of the AC Operating Conditions
table). RAS and CAS must remain active for tRWL and tCWL,
respectively, after W active transition to complete the write
cycle.
READ–WRITE CYCLE
A read–write cycle performs a read and then a write at the
same address, during the same cycle. This cycle is basically
a late write cycle, as discussed in the WRITE CYCLE sec-
tion, except W must remain high for tCWD minimum after
the CAS active transition, to guarantee valid Q before writing
the bit.
PAGE MODE CYCLES
Page mode allows fast successive data operations at all
2048 column locations on a selected row of the 4M dynamic
RAM. Read access time in page mode (tCAC) is typically half
the regular RAS clock access time, tRAC. Page mode opera-
tion consists of keeping RAS active while toggling CAS be-
tween VIH and VIL. The row is latched by RAS active
transition, while each CAS active transition allows selection
of a new column location on the row.
A page mode cycle is initiated by a normal read, write, or
read–write cycle, as described in prior sections. Once the
timing requirements for the first cycle are met, CAS transi-
tions to inactive for minimum of tCP, while RAS remains low
(VIL). The second CAS active transition while RAS is low
initiates the first page mode cycle (tPC or tPRWC). Either a