Data Sheet Conexant - Preliminary Doc. No. 101252A
Proprietary Information and Specifications Are Subject to Change March 13, 2001
CX74005
VGA + I/Q Demodulator Rx ASIC for Portable Phone Applications
The CX74005 Application-Specific Integrated Circuit (ASIC) is a Variable Gain
Amplifier (VGA) and I/Q demodulator, intended for use in Code Division Multiple
Access (CDMA) portable phones in both cellular and Personal Communications
System (PCS) bands. As a trimode IC, it can be used in CDMA mode or Advanced
Mobile Phone System (AMPS) mode.
The device incorporates a VGA and the In-Phase and Quadrature (I/Q)
demodulator stages. The intermediate frequencies (IF) are combined through
separate buffers at the input of the VGA depending on the selected mode. The
VGA has a gain control range greater than 90 dB.
There are two Very High Frequency (VHF) oscillators that operate with external
tank circuits. They provide signals to the Local Oscillator (LO) for the I/Q
demodulator in the cellular and PCS bands.
The noise figure, gain, and third order Input Intercept Point (IIP3) of the CX74005
are optimized to meet the system requirements for AMPS and CDMA modes as per
TIA/EIA-98-B, ANSI J-STD-018 (PCS), CDMA2000. Employing silicon bipolar
technology, the ASIC is designed for high performance, a high level of integration
and low cost.
The device package and pinout are shown in Figure 1. A block diagram of the
CX74005 is shown in Figure 2.
Features
• Supports CDMA/AMPS/PCS1900 modes
• Three battery cell operation
(2.7 V < VCC < 3.3 V).
• IF inputs and I/Q outputs
• On-chip 100 to 640 MHz oscillators
• Low power operation: <25 mA
• 32-pin Land Grid Array (LGA) 5 x 5 mm package
Applications
• Tri-mode handsets
• CDMA and AMPS modes in the cellular band:
− AMPS
− CDMA-US
− CDMA-Japan
• CDMA mode in the PCS band:
− PCS-US
− PCS-Korea
CNXT044
GND
CELL/PCS
VCO_VCC
VCO_GND
CELL_TANK1-
CELL_TANK1+
NC
PCS_TANK-
25
24
23
22
21
20
19
18
17
PCS_TANK+
DIV2/DIV4
PLL+
SLEEP
PLL-
GND
IF_GND
32
31
30
26
29
28
27
GND
SIF
I+
GND
I-
Q+
Q-
10
11
12
16
13
14
15
GND
NC
VGA_PCS_IN+
VGA_PCS_IN-
VGA_CDMA_IN+
VGA_CDMA_IN-
IF_VCC
VGA_GC
1
2
3
4
5
6
7
8
9
FM/CDMA VGA_AMPS
Figure 1. Rx ASIC Pinout – 32-Pin LGA Package
(Top View)
CX74005 Rx ASIC
2 Conexant - Preliminary 101252A
Proprietary Information and Specifications Are Subject to Change March 13, 2001
÷ 2,4
I
Q
CX74005
Rx ASIC
PLL
3
24
19,20
6,7
29
30
27
28
C1431
12,139,1016
21,22
VGA_GC
2
2
2
17
FM/CDMA
CELL/PCS
SLEEP
VGA_CDMA
VGA_AMPS
VGA_PCS
2
2
2
DIV2/DIV4
11
Figure 2. CX74005 Rx ASIC Block Diagram
Technical Description
Variable Gain Amplifier (VGA). The high dynamic range
required by CDMA handsets is achieved by the VGA, which is
common to all modes. The VGA has a minimum dynamic range
of 90 dB with a control voltage of 0.5 to 2.5 volts. The
appropriate signal path is switched internal to the device. This
eliminates off-chip switching needed to operate this common
VGA in cellular AMPS, CDMA, and PCS modes.
I/Q Demodulator. The local oscillator signals are generated on-
chip. The I/Q demodulator is internally connected to the VGA
output. It is designed to have a very low amplitude and phase
imbalance. The I and Q outputs are differential. The DC offsets
between the differential outputs and between I and Q channels
are designed to be extremely low to facilitate compatibility with
baseband interfaces.
VHF Oscillators. There are two on-chip oscillators, one for the
cellular and one for the PCS bands. These Voltage Controlled
Oscillators (VCOs) work with external tank circuits and varactor
diodes. The outputs of the differential oscillators are buffered
and the output is used to drive the prescaler of an external
Phase Locked Loop (PLL). The VCOs typically operate at twice
the IF frequency and can operate at up to four times the IF
frequency.
The local oscillators for the I/Q demodulators are derived by an
on-chip frequency divider. The logic signal to select the divider
ratio (2 or 4) is available on Pin 11 (DIV2/DIV4).
Mode Control. The operation of the chip is controlled by signals
at Pin 3 (CELL/PCS), Pin 2 (FM/CDMA), Pin 16 (SLEEP), and
the DIV2/DIV4 select commands at Pin 11. All the switching is
done internally. The supply voltage should be present at all the
VCC pins for normal operation. The signals needed to select
each mode is shown in Table 1.
Electrical and Mechanical Specifications
Signal pin assignments and functional pin descriptions are
described in Table 2. The absolute maximum ratings of the
CX74005 are provided in Table 3. The recommended operating
conditions are specified in Table 4. Electrical specifications are
provided in Table 5.
Typical performance characteristics are illustrated in Figures 3
through 32. Figure 33 provides the package dimensions for the
32-pin LGA and tape and reel dimensions are shown in
Figure 34.
Rx ASIC CX74005
101252A Conexant - Preliminary 3
March 13, 2001 Proprietary Information and Specifications Are Subject to Change
ESD Sensitivity
The CX74005 is a Class 1 device. The following extreme
Electrostatic Discharge (ESD) precautions are required
according to the Human Body Model (HBM):
• Protective outer garments.
• Handle device in ESD safeguarded work area.
• Transport device in ESD shielded containers.
• Monitor and test all ESD protection equipment.
The HBM ESD withstand threshold value, with respect to
ground, is ±1.5 kV. The HBM ESD withstand threshold value,
with respect to VDD (the positive power supply terminal) is also
±1.5 kV.
Table 1. Mode Control Select Signa l Switching
Pin AMPS CDMA PCS
3 (CELL/PCS) 0 0 1
2 (FM/CDMA) 0 1 x
16 (SLEEP) 1 1 1
Key: 0 = Low
1 = High
x = N/A
Note: DIV 2 is used in the evaluation board.
CX74005 Rx ASIC
4 Conexant - Preliminary 101252A
Proprietary Information and Specifications Are Subject to Change March 13, 2001
Table 2. CX74005 Pin Assignments and Signal Descriptions
Pin # Name Description
1 GND Ground
2 FM/CDMA Cellular band mode select: 0 = AMPS, 1 = CDMA
3 CELL/PCS Band selec t: 0 = Cel lular; 1 = PCS
4 VCO_VCC Voltage suppl y pin to the VCO buffer s. A bypass capacit or should be placed close to the device from pi n 4 to pin
5. The tr ace should be short and connect ed immediatel y to the ground plane for best performanc e.
5 VCO_GND Ground return from the VCO buffers .
6 CELL_TANK1– Differential tank c onnection for the cellular band VCO. Care should be taken during t he layout of the external t ank
circuit to prevent parasitic oscillations.
7 CELL_TANK_1+ Differential tank c onnection for the cellular band VCO. Care should be taken during t he layout of the external t ank
circuit to prevent parasitic oscillations.
8 NC No connection
9 PCS_TANK– Differential tank c onnection for the PCS band VCO. Care should be taken duri ng the layout of the external tank
circuit to prevent parasitic oscillations.
10 PCS_TANK+ Di fferent ial tank connection for the PCS band VCO. Care should be taken during t he layout of the external tank
circuit to prevent parasitic oscillations.
11 DIV2/DI V4 Select s the divide ratio of the VCO to the LO port of the I /Q demodulator : 0 = divide by 2, 1 = divi de by 4.
12 PLL+ Differential buffered VCO out put
13 PLL– Differential buff ered VCO output
14 GND Ground
15 IF_GND Ground
16 SLEEP Acti vates sleep mode: 0 = Sleep, 1 = Enable
17 VGA_GC The VGA gain cont rol signal. A DC c ontrol voltage s hould be applied t o this pin to var y the gain of the VGA.
18 IF_VCC Voltage s upply to VGA and I/Q demodulat or stages. Supply should be well regulated and bypas sed to prevent
modulation of the signal by the supply rippl e.
19 VGA_CDMA_IN– CDMA differential VGA input
20 VGA_CDMA_IN+ CDMA different ial VGA input
21 VGA_PCS_IN- PCS differential VGA input.
22 VGA_PCS_IN+ PCS different ial VGA input.
23 GND Ground
24 VGA_AMPS AMPS VGA input
25 GND Ground
26 GND Ground
27 Q– Q channel di fferent ial output
28 Q+ Q channel differenti al output
29 I– I channel differential output
30 I+ I channel differential output
31 GND Ground
32 GND Ground
Rx ASIC CX74005
101252A Conexant - Preliminary 5
March 13, 2001 Proprietary Information and Specifications Are Subject to Change
Table 3. Absolute Maximum Ratings
Parameter Minimum Maximum Units
Supply voltage (V CC) –0.3 +5.5 V
Input v oltage range –0.3 VCC V
Power dis sipati on 600 mW
Ambient operating temper ature –30 +80 °C
Storage t emperature –40 +125 °C
Table 4. Recommended Operating Conditions
Parameter Minimum Typical Maximum Units
Supply voltage ( VCC) 2.7 3.0 3.3 V
Operating temperature –30 +25 +80 °C
Impedance of logic inputs 50 kΩ
Logic 0 0.0 0.5 V
Logic 1 VCC – 0.5 VCC V
Table 5. CX74005 Rx ASIC Electrical Specifications (1 of 2)
(TA = 25°
°°
° C, VCC = 3.0 V)
Parameter Test Condition Min Typical Max Units
Rx VGA - I/Q Demodulator
Frequency range 50 300 MHz
Input im pedance:
AMPS input (single ended)
CDMA input (differ ential)
PCS input (differ ential)
1000
1000
1000
Ω
Ω
Ω
Voltage gain:
Maximum (AMPS)
Minimum (AMPS)
Maximum (CDMA)
Minimum (CDMA)
Maximum (PCS)
Minimum (PCS)
VGA_GC (V)
2.5
0.5
2.5
0.5
2.5
0.5
55
–45
52.5
–46
50
–46
dB
dB
dB
dB
dB
dB
Voltage gain slope 49 dB/V
Voltage gain slope linearit y (over any 6 dB s egment) –3 +3 dB
VGA + I/Q IIP3:
@ Maximum v oltage gain (AMPS)
@ Maximum v oltage gain (CDMA)
@ Maximum v oltage gain (PCS)
VGA_GC (V)
2.5
2.5
2.5
–50.5
–48.5
–47
dBm
dBm
dBm
Input 1 dB c ompression @ minimum gain –10 dBm
VGA + I/Q noise figure:
@ Maximum gain (AMPS)
@ Maximum gain (CDMA)
@ Maximum gain (PCS)
@ Minimum gain
8
5.5
5.5
–50
dB
dB
dB
dB
CX74005 Rx ASIC
6 Conexant - Preliminary 101252A
Proprietary Information and Specifications Are Subject to Change March 13, 2001
Table 5. CX74005 Rx ASIC Electrical Specifications (2 of 2)
(TA = 25°
°°
° C, VCC = 3.0 V)
Parameter Test Condition Min Typical Max Units
Rx VGA - I/Q Demodulator (continued)
Output level:
AMPS
CDMA
PCS
2.75
2.50
2.50
mVrms
mVrms
mVrms
Maximum out put level 1.4 Vp-p
Gain var iation over fr equency:
AMPS (0.1-12.2 kHz)
CDMA (1-630 k Hz)
PCS (1-630 k Hz)
0.1
0.1
0.1
0.3
0.3
0.3
dB
dB
dB
I+, I–, and Q+, Q– DC offset 1 6 mVrms
I/Q gai n mismatch 0.2 0.3 dB
I/Q phase mismatch 2 4 deg
Output load impedance ( differ ential) 10 kΩ
Output im pedance (differential) 500 Ω
Total s upply current (incl udes I/Q mixers, LO buffers, and dividers) 15 mA
Oscillator
Frequency range 100 640 MHz
Phase noise (fc = 200 MHz, unl oaded Q = 20) @ 100 kHz offset –117 dBc/Hz
Second harmoni c dis torti on (application dependent ) –30 –26 dBc
Output level to PLL (diff erential) 300 mVp-p
Output im pedance to PLL (differ ential) 300 Ω
Total s upply c urrent ( including external tank circuit s) 10 mA
Rx ASIC CX74005
101252A Conexant - Preliminary 7
March 13, 2001 Proprietary Information and Specifications Are Subject to Change
-60
-50
-40
-30
-20
-10
0
10
00.511.522.53
Control Voltage (Volts)
IIP3 (dBm)
IIP3-3.0V
OIP3-3.0V
IIP3-2.7V
OIP3-2.7V
IIP3-3.3V
OIP3-3.3V
Figure 3. AMPS IIP3 and OIP3 vs. Control Voltage @ 25 C
-60
-50
-40
-30
-20
-10
0
10
00.511.522.53
Contr ol Voltag e (Volt s )
IIP3 (dBm)
IIP3-2.7V
OIP3-2.7V
IIP3-3.0V
OIP3-3.0V
IIP3-3.3V
OIP3-3.3V
Figure 5. AMPS IIP3 and OIP3 @ –30 ˚C
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
00.511.522.53
Contr ol Voltag e (Volt s )
IIP3 (dBm)
IIP3-2.7V
OIP3-2.7V
IIP3-3.0V
OIP3-3.0V
IIP3-3.3V
Figure 7. AMPS IIP3 and OIP3 vs. Control Voltage @ 85 C
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
0 0.5 1 1.5 2 2.5 3
Con t rol Vo lt age (Volt s)
Voltage Gain (dB)
2.7V
3.0V
3.3V
Figure 4. AMPS VGA vs. Control Voltage @ 25 ˚C
-35
-25
-15
-5
5
15
25
35
45
55
65
00.511.522.53
Control Voltage (Volts)
Voltage Gain (dB)
2.7V
3.0V
3.3V
Figure 6. AMPS VGA vs. Control Voltage @ –30 ˚C
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
00.511.522.53
Control Votlage (Volts)
Voltage Gain (dB)
2.7V
3.0V
3.3V
Figure 8. AMPS VGA vs. Control Voltage @ 85 °C
CX74005 Rx ASIC
8 Conexant - Preliminary 101252A
Proprietary Information and Specifications Are Subject to Change March 13, 2001
7
8
9
10
11
12
2 2.12.22.32.42.52.6
Control V oltage (Volts)
NF (dB)
2.7V
3.0V
3.3V
Figure 9. AMPS Noise Figure vs. Control Voltage @ 25 °C
8
8.5
9
9.5
10
10.5
11
2 2.1 2.2 2.3 2.4 2.5 2.6
Control Voltage (Volts)
NF (dB)
Figure 11. AMPS VGA Noise Figure vs. Control Voltage @ 85 °C at
VCC=3 Volts
-50
-40
-30
-20
-10
0
10
0.5 1 1.5 2 2.5 3
Control Voltage (Volts)
IIP3 (dBm)
IIP3-2.7V
OIP3-2.7V
IIP3-3.0V
OIP3-3.0V
IIP3-3.3V
OIP3-3.3V
Figure 13. CDMA IIP3 vs. Control Voltage @ 25 °C
30
35
40
45
50
55
60
2 2.1 2.2 2.3 2.4 2.5 2.6
Contr ol Voltage (Volts )
2.7V
3.0V
3.3V
Figure 10. AMPS Gain Noise Figure vs. Control Voltage @ 25 °C
30
35
40
45
50
55
60
2 2.1 2.2 2.3 2.4 2.5 2.6
Control Voltage (Volts)
Voltage Gain (dB)
Figure 12. AMPS VGA vs. Control Voltage @ 85 °C
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
0.511.522.53
Control Voltage (Volts)
Voltage Gain (dB)
2.7V
3.0V
3.3V
Figure 14. CDMA Gain vs. Control Voltage @ 25 °C
Rx ASIC CX74005
101252A Conexant - Preliminary 9
March 13, 2001 Proprietary Information and Specifications Are Subject to Change
-55
-45
-35
-25
-15
-5
5
0.4 0.85 1.3 1.75 2.2 2.65
Contr ol Voltag e (Volt s )
IIP3 (dBm)
IIP3-2.7V
IIP3-3.0V
IIP3-3.3V
OIP3-2.7V
OIP3-3.0V
OIP3-3.3V
Figure 15. CDMA IIP3 and OIP3 vs. Control Voltage @ –30 °C
-50
-40
-30
-20
-10
0
10
00.511.522.53
Contr ol Voltag e (Volt s )
IIP3 (dBm)
IIP3-2.7V
OIP3-2.7V
OIP3-3.0V
IIP3-3.0V
IIP3-3.3V
OIP3-3.3V
Figure 17. CDMA IIP3 and OIP3 vs. Control Voltage @ 85 °C
4
5
6
7
8
9
10
11
12
13
2 2.1 2.2 2.3 2.4 2.5 2.6
Control Voltage (Volts)
NF (dB)
2.7V
3.0V
3.3V
Figure 19. CDMA Noise Figure vs. Control Voltage @ 25 °C
-55
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
0.4 0.85 1.3 1.75 2.2 2.65
Control Volt age ( Vl t s)
Voltage Gain (dB)
2.7V
3.0V
3.3V
Figure 16. CDMA VGA vs. Control Voltage @ –30 °C
-55
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
00.511.522.53
Control Voltage (Volts)
Votlage Gain (dB)
2.7V
3.0V
3.3V
Figure 18. CDMA VGA vs. Control Voltage @ 85 °C
20
25
30
35
40
45
50
55
2 2.1 2.2 2.3 2.4 2.5 2.6
Control Voltage (Volts)
Voltage Gain (dB)
2.7V
3.0V
3.3V
Figure 20. CDMA VGA vs. Control Voltage @ 25 °C
CX74005 Rx ASIC
10 Conexant - Preliminary 101252A
Proprietary Information and Specifications Are Subject to Change March 13, 2001
6
7
8
9
10
11
12
13
2 2.1 2.2 2.3 2.4 2.5 2.6
Contr ol Voltag e (Volt s )
NF (dB)
Figure 21. CDMA VGA Noise Figure vs. Control Voltage @ 85 °C
-50
-40
-30
-20
-10
0
10
0 0.5 1 1.5 2 2.5 3
Control Voltage (Volts)
IIP3 (dBm)
IIP3-2.7V
OIP3-2.7V
IIP3-3.0V
OIP3-3.0V
IIP3-3.3V
Figure 23. PCS IIP3 and OIP3 vs. Control Voltage @ 25 °C7
-60
-50
-40
-30
-20
-10
0
10
00.511.522.53
Control Voltage (Volts)
IIP3 (dBm)
IIP3-2.7v
OIP3-2.7v
IIP3-3.0v
OIP3-3.0v
IIP3-3.3V
OIP3-3.3V
Figure 25. PCS IIP3 vs. Control Voltage @ –30 °C
25
30
35
40
45
50
55
2 2.1 2.2 2.3 2.4 2.5 2.6
Control Voltage (Volts)
Voltage Gain (dB)
Figure 22. CDMA VGA vs. Control Voltage @ 85 °C
-50
-40
-30
-20
-10
0
10
20
30
40
50
0 0.5 1 1.5 2 2.5 3
Con trol Voltage (Volts)
Voltage Gain (dB)
2.7V
3.0V
3.3V
Figure 24. PCS VGA vs. Control Voltage @ 25 °C
-55
-45
-35
-25
-15
-5
5
15
25
35
45
55
00.511.522.53
Control Votlage (Volts)
Voltage Gain (dB)
2.7V
3.0V
3.3V
Figure 26. PCS VGA vs. Control Voltage @ –30 °C
Rx ASIC CX74005
101252A Conexant - Preliminary 11
March 13, 2001 Proprietary Information and Specifications Are Subject to Change
-55
-45
-35
-25
-15
-5
5
15
00.511.522.53
Contr ol Voltag e (Volt s )
IIP3 (dBm)
IIP3-2.7V
OIP3-2.7V
IIP3-3.0V
OIP3-3.0V
IIP3-3.3V
OIP3-3.3V
Figure 27. PCS IIP3 and OIP3 vs. Control Voltage @ 85 °C
4
5
6
7
8
9
10
11
12
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7
Contr ol Voltag e (Volt s )
NF (dB)
2.7V
3.0V
3.3V
Figure 29. PCS Noise Figure vs. Control Voltage @ 25 °C
5
6
7
8
9
10
11
12
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7
Contrl Vol tage (Volts)
NF (dB)
Figure 31. PCS VGA vs. Control Voltage @ 85 °C
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
0.5 1 1.5 2 2.5 3
Control Voltage (Volts)
Voltage Gain (dB)
2.7V
3.0V
3.3V
Figure 28. PCS VGA vs. Control Voltage @ 85 °C
20
25
30
35
40
45
50
55
2 2.12.22.32.42.52.62.7
Control Vol tage (Volts)
Voltage Gain (dB)
2.7V
3.0V
3.3V
Figure 30. PCS VGA vs. Control Voltage @ 25 °C
20
25
30
35
40
45
50
55
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7
Control Vol t age (Volts)
Voltage Gain (dB)
Figure 32. PCS VGA vs. Control Voltage @ 85 °C
CX74005 Rx ASIC
12 Conexant - Preliminary 101252A
Proprietary Information and Specifications Are Subject to Change March 13, 2001
C1285
5.04 ± 0.05
5.04 ± 0.05
0.30 ± 0.05
1.20 ± 0.10
Pin #1
4.200
0.500
0.500
Solder Mask
2.480
To Metal Pad Edge
2.350
Package Edge
Detail A
Mold
Substrate
All measurements are in millimeters
2.480
To Metal Pad Edge
2.350
0.300 0.150 Pin #1 mark
Exposed Metal
Exposed Metal
Solder Mask
Pin #1
0.38 ± 0.05
0.300 ± 0.02
0.400 ± 0.05
2.000
0.040 Ref.
Figure 33. Rx ASIC Package Dimensions – 32-Pin LGA Package
8.00 ± 0.10
5.51 ± 0.10 1.78 ± 0.10 5.49 ± 0.10
0.292 ± 0.02
8
o
maximum 5
o
maximum
4.00 ± 0.10 1.50 ± 0.10 1.75 ± 0.10
12.00 +0.30/–0.10
5.50 ± 0.10
1.50 ± 0.25
C1327
Notes:
1. Carrier tape material: black conductive polycarbonate
2. Cover tape material: transparent conductive PSA
3. Cover tape size: 9.3 mm width
4. Tolerance: .XX = ±0.10
5. All measurements are in millimeters
Figure 34. 32-Pin LGA Tape and Reel Dimensions
Rx ASIC CX74005
101252A Conexant - Preliminary 13
March 13, 2001 Proprietary Information and Specifications Are Subject to Change
Ordering Information
Model Name Manufacturing Part
Number Product Revision
Rx ASIC CX74005
© 2001, 2002, Skyworks Sol utions, Inc. All Rights Reserved.
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4311 Jamboree Rd.
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