GLS36VF1601G-70-4I-EKE - Greenliant Systems

Data Sheet

www.greenliant.com

16 Mbit (x8/x16) Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FEATURES:

• Organized as 1M x16 or 2M x8

• Dual Bank Architecture for Concurrent

Read/Write Operation

– 16 Mbit Bottom Sector Protection

- GLS36VF1601G: 4 Mbit + 12 Mbit

– 16 Mbit Top Sector Protection

- GLS36VF1602G: 12 Mbit + 4 Mbit

• Single 2.7-3.6V for Read and Write Operations

• Superior Reliability

– Endurance: 100,000 cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 6 mA typical

– Standby Current: 4 µA typical

– Auto Low Power Mode: 4 µA typical

• Hardware Sector Protection/WP# Input Pin

– Protects the 4 outermost sectors (8 KWord)

in the smaller bank by driving WP# low and

unprotects by driving WP# high

• Hardware Reset Pin (RST#)

– Resets the internal state machine to reading

array data

• Byte# Pin

– Selects 8-bit or 16-bit mode

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Chip-Erase Capability

• Block-Erase Capability

– Uniform 32 KWord blocks

• Erase-Suspend / Erase-Resume Capabilities

• Security ID Feature

– Greenliant: 128 bits

– User: 256 Byte

• Fast Read Access Time

– 70 ns

• Latched Address and Data

• Fast Erase and Program (typical):

– Sector-Erase Time: 18 ms

– Block-Erase Time: 18 ms

– Chip-Erase Time: 35 ms

– Program Time: 7 µs

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

– Ready/Busy# pin

• CMOS I/O Compatibility

• Conforms to Common Flash Memory Interface (CFI)

• JEDEC Standards

– Flash EEPROM Pinouts and command sets

• Packages Available

– 48-ball TFBGA (6mm x 8mm)

– 48-lead TSOP (12mm x 20mm)

– 56-ball LFBGA (8mm x 10mm)

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The GLS36VF1601G and GLS36VF1602G are 1M x16 or

2M x8 CMOS Concurrent Read/Write Flash Memory man-

ufactured with high performance SuperFlash memory tech-

nology. The split-gate cell design and thick oxide tunneling

injector attain better reliability and manufacturability com-

pared with alternate approaches. The devices write (Pro-

gram or Erase) with a 2.7-3.6V power supply and conform

to JEDEC standard pinouts for x8/x16 memories.

Featuring high performance Program, the GLS36VF160xG

provide a typical Program time of 7 µsec and use Toggle

Bit, Data# Polling, or RY/BY# to detect the completion of

the Program or Erase operation. To protect against inad-

vertent write, the devices have on-chip hardware and Soft-

ware Data Protection schemes. Designed, manufactured,

and tested for a wide spectrum of applications, these

devices are offered with a guaranteed endurance of 10,000

cycles. Data retention is rated at greater than 100 years.

These devices are suited for applications that require con-

venient and economical updating of program, configura-

tion, or data memory. For all system applications, the

GLS36VF160xG significantly improve performance and

reliability, while lowering power consumption. These

devices inherently use less energy during Erase and Pro-

gram than alternative flash technologies, because the total

energy consumed is a function of the applied voltage, cur-

rent, and time of application. For any given voltage range,

GLS36VF1601E / 1602E16Mb (x8/x16) Concurrent SuperFlash

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

the SuperFlash technology uses less current to program

and has a shorter erase time; therefore, the total energy

consumed during any Erase or Program operation is less

than alternative flash technologies.

SuperFlash technology provides fixed Erase and Program

times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose

Erase and Program times increase with accumulated

Erase/Program cycles.

To meet high-density, surface-mount requirements, the

GLS36VF1601G and GLS36VF1602G devices are offered

in 48-ball TFBGA, 48-lead TSOP, and 56-ball LFBGA

packages. See Figures 6, 7, and 8 for pin assignments.

Device Operation

Memory operation functions are initiated using standard

microprocessor write sequences. A command is written by

asserting WE# low while keeping CE# low. The address

bus is latched on the falling edge of WE# or CE#, which-

ever occurs last. The data bus is latched on the rising edge

of WE# or CE#, whichever occurs first.

Auto Low Power Mode

These devices also have the Auto Lower Power mode

which puts them in a near-standby mode within 500 ns

after data has been accessed with a valid Read operation.

This reduces the typical IDD active Read current to 4 µA.

While CE# is low, the devices exit Auto Low Power mode

with any address transition or control signal transition used

to initiate another Read cycle, with no access time penalty.

Concurrent Read/Write Operation

The dual bank architecture of these devices allows the

Concurrent Read/Write operation whereby the user can

read from one bank while programming or erasing in the

other bank. For example, reading system code in one bank

while updating data in the other bank. See Table 1 below

for more information.

Note: For the purposes of this table, write means to perform Block-

or Sector-Erase or Program operations as applicable to the

appropriate bank.

The Read operation of the GLS36VF160xG is controlled

by CE# and OE#, both of which have to be low for the

system to obtain data from the outputs. CE# is used for

device selection. When CE# is high, the chip is deselected

and only standby power is consumed. OE# is the output

control and is used to gate data from the output pins. The

data bus is in a high impedance state when either CE# or

OE# is high. Refer to Figure 9, the Read cycle timing dia-

gram, for further details.

Program Operation

These devices are programmed on a word-by-word or

byte-by-byte basis depending on the state of the BYTE#

pin. Before programming, ensure that the sector which is

being programmed is fully erased.

The Program operation is accomplished in three steps:

1. Initiate Software Data Protection using the three-

byte load sequence.

2. Load address and data.

During the Program operation, the addresses are

latched on the falling edge of either CE# or WE#,

whichever occurs last. The data is latched on the

rising edge of either CE# or WE#, whichever

occurs first.

3. Initiate the internal Program operation after the ris-

ing edge of the fourth WE# or CE#, whichever

occurs first. The Program operation, once initi-

ated, will be completed typically within 7 µs.

See Figures 10 and 11 for WE# and CE# controlled Pro-

gram operation timing diagrams and Figure 25 for flow-

charts. During the Program operation, the only valid reads

are Data# Polling and Toggle Bit. During the internal Pro-

gram operation, the host is free to perform additional tasks.

Any commands issued during an internal Program opera-

tion are ignored.

TABLE 1: Concurrent Read/Write State

Bank 1 Bank 2

Read No Operation

Read Write

Write Read

Write No Operation

No Operation Read

No Operation Write

TABLE 1: Concurrent Read/Write State

Bank 1 Bank 2

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Sector-Erase/Block-Erase Operation

The Sector- or Block- Erase operation allows the system to

erase the device on a sector-by-sector (or block-by-block)

basis. The GLS36VF160xG offer both Sector-Erase and

Block-Erase operations.

The sector architecture is based on a uniform sector size of

2 KWord. The Sector-Erase operation is initiated by execut-

ing a six-byte command sequence with a Sector-Erase

command (50H) and sector address (SA) in the last bus

cycle.

The Block-Erase mode is based on a uniform block size of

32 KWord. Block-Erase is initiated by executing a six-byte

command sequence with Block-Erase command (30H) and

block address (BA) in the last bus cycle. The sector or block

address is latched on the falling edge of the sixth WE#

pulse, while the command (50H or 30H) is latched on the

rising edge of the sixth WE# pulse. The internal Erase oper-

ation begins after the sixth WE# pulse.

Any commands issued during the Sector- or Block-Erase

operation are ignored except Erase-Suspend and Erase-

Resume. See Figures 15 and 16 for timing waveforms.

Chip-Erase Operation

The GLS36VF1601G and GLS36VF1602G provide a

Chip-Erase operation, which erases the entire memory

array to the ‘1’ state. This operation is useful when the

entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command

(10H) at address 555H in the last byte sequence. The

Erase operation begins with the rising edge of the sixth

WE# or CE#, whichever occurs first. During the Erase

operation, the only valid Read is Toggle Bit or Data# Poll-

ing. Any commands issued during the Chip-Erase opera-

tion are ignored. See Table 6 for the command sequence,

Figure 14 for timing diagram, and Figure 29 for the flow-

chart. When WP# is low, any attempt to Chip-Erase will be

ignored.

Erase-Suspend/Erase-Resume Operations

The Erase-Suspend operation temporarily suspends a

Sector- or Block-Erase operation thus allowing data to be

read or programmed into any sector or block that is not

engaged in an Erase operation. The operation is executed

by issuing a one-byte command sequence with Erase-Sus-

pend command (B0H). The device automatically enters

read mode no more than 10 µs after the Erase-Suspend

command had been issued. (TES maximum latency equals

10 µs.) Valid data can be read from any sector or block that

is not suspended from an Erase operation. Reading at

address location within erase-suspended sectors/blocks

will output DQ2 toggling and DQ6 at ‘1’. While in Erase-

Suspend mode, a Program operation is allowed except for

the sector or block selected for Erase-Suspend.

To resume a suspended Sector-Erase or Block-Erase

operation, the system must issue an Erase-Resume com-

mand. The operation is executed by issuing a one-byte

command sequence with Erase Resume command (30H)

at any address in the one-byte sequence.

Write Operation Status Detection

To optimize the system Write cycle time, the

GLS36VF160xG provide two software means to detect the

completion of a Write (Program or Erase) cycle The soft-

ware detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE#, which initi-

ates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asyn-

chronous with the system. Therefore, Data# Polling or

Toggle Bit maybe be read concurrent with the completion

of the write cycle. If this occurs, the system may possibly

get an incorrect result from the status detection process.

For example, valid data may appear to conflict with either

DQ7 or DQ6. To prevent false results, upon detection of

failures, the software routine should loop to read the

accessed location an additional two times. If both reads

are valid, then the device has completed the Write cycle,

otherwise the failure is valid.

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Ready/Busy# (RY/BY#)

The GLS36VF160xG include a Ready/Busy# (RY/BY#)

output signal. RY/BY# is an open drain output pin that indi-

cates whether an Erase or Program operation is in prog-

ress. Since RY/BY# is an open drain output, it allows

several devices to be tied in parallel to VDD via an external

pull-up resistor. After the rising edge of the final WE# pulse

in the command sequence, the RY/BY# status is valid.

When RY/BY# is actively pulled low, it indicates that an

Erase or Program operation is in progress. When RY/BY#

is high (Ready), the devices may be read or left in standby

mode.

Byte/Word (BYTE#)

The device includes a BYTE# pin to control whether the

device data I/O pins operate x8 or x16. If the BYTE# pin is

at logic “1” (VIH) the device is in x16 data configuration: all

data I/0 pins DQ0-DQ15 are active and controlled by CE#

and OE#.

If the BYTE# pin is at logic ‘0’, the device is in x8 data con-

figuration -- only data I/O pins DQ0-DQ7 are active and con-

trolled by CE# and OE#. The remaining data pins DQ8-

DQ14 are at Hi-Z, while pin DQ15 is used as the address

input A-1 for the Least Significant Bit of the address bus.

Data# Polling (DQ7)

When the GLS36VF160xG are in an internal Program

operation, any attempt to read DQ7 will produce the com-

plement of true data. Once the Program operation is com-

pleted, DQ7 will produce valid data.

During internal Erase operation, any attempt to read DQ7

will produce a ‘0’. Once the internal Erase operation is com-

pleted, DQ7 will produce a ‘1’. The Data# Polling is valid

after the rising edge of fourth WE# (or CE#) pulse for Pro-

gram operation. For Sector-, Block-, or Chip-Erase, the

Data# Polling is valid after the rising edge of sixth WE# (or

CE#) pulse. See Figure 12 for Data# Polling (DQ7) timing

diagram and Figure 26 for a flowchart.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating ‘1’s

and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When the internal

Program or Erase operation is completed, the DQ6 bit will

stop toggling, and the device is then ready for the next

operation. For Sector-, Block-, or Chip-Erase, the toggle bit

(DQ6) is valid after the rising edge of sixth WE# (or CE#)

pulse. DQ6 will be set to ‘1’ if a Read operation is attempted

on an Erase-Suspended Sector or Block. If Program oper-

ation is initiated in a sector/block not selected in Erase-Sus-

pend mode, DQ6 will toggle.

An additional Toggle Bit is available on DQ2, which can be

used in conjunction with DQ6 to check whether a particular

sector or block is being actively erased or erase-sus-

pended. Table 2 shows detailed bit status information. The

Toggle Bit (DQ2) is valid after the rising edge of the last

WE# (or CE#) pulse of Write operation. See Figure 13 for

Toggle Bit timing diagram and Figure 26 for a flowchart.

Note: DQ7, DQ6, and DQ2 require a valid address when reading

status information. The address must be in the bank where

the operation is in progress in order to read the operation sta-

tus. If the address is pointing to a different bank (not busy),

the device will output array data.

TABLE 2: Write Operation Status

Status DQ7DQ6DQ2RY/BY#

Normal

Operation

Standard

Program

DQ7# Toggle No Toggle 0

Standard

Erase

0 Toggle Toggle 0

Erase-

Suspend

Mode

Read From

Erase

Suspended

Sector/Block

1 1 Toggle 1

Read From

Non-Erase

Suspended

Sector/Block

Data Data Data 1

Program DQ7# Toggle N/A 0

T2.1 1342

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Data Protection

The GLS36VF160xG provide both hardware and software

features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5

ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Write operation. This prevents inadver-

tent writes during power-up or power-down.

Hardware Block Protection

The GLS36VF1601G and GLS36VF1602G provide hard-

ware block protection which protects the outermost 8

KWord in the smaller bank. The block is protected when

WP# is held low. See Figures 2, 3, 4, and 5 for Block-Pro-

tection location.

Block protection is disabled by driving WP# high. This

allows data to be erased or programmed into the protected

sectors. WP# must be held high prior to issuing the Write

command and remain stable until after the entire Write

operation has completed. If WP# is left floating, it is inter-

nally held high via a pull-up resistor, and the Boot Block is

unprotected, enabling Program and Erase operations on

that block.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the

devices to read array data. When the RST# pin is held low

for at least TRP, any in-progress operation will terminate

and return to Read mode (see). When no internal Program/

Erase operation is in progress, a minimum period of TRHR

is required after RST# is driven high before a valid Read

can take place. See Figures 22 and 21 for more informa-

tion.

The interrupted Erase or Program operation must be re-ini-

tiated after the device resumes normal operation mode to

ensure data integrity.

Software Data Protection (SDP)

The GLS36VF160xG devices implement the JEDEC

approved Software Data Protection (SDP) scheme for all

data alteration operations, such as Program and Erase.

These devices are shipped with the Software Data Protec-

tion permanently enabled. See Table 6 for the specific soft-

ware command codes.

All Program operations require the inclusion of the three-

byte sequence. The three-byte load sequence is used to

initiate the Program operation, providing optimal protection

from inadvertent Write operations. SDP for Erase opera-

tions is similar to Program, but a six-byte load sequence is

required for Erase operations.

During SDP command sequence, invalid commands will

abort the device to read mode within TRC. The contents of

DQ15-DQ8 can be VIL or VIH, but no other value, during any

SDP command sequence.

Common Flash Memory Interface (CFI)

These devices contain Common Flash Memory Interface

(CFI) information that describes the characteristics of the

device. In order to enter the CFI Query mode, the system

must write a three-byte sequence, using the CFI Query

command, to address BKx555H in the last byte sequence.

The system can also use the one-byte sequence with

address BKx55H and Data Bus 98H to enter this mode.

See Figure 18 for CFI Entry and Read timing diagram.

Once the device enters the CFI Query mode, the system

can read CFI data at the addresses given in Tables 7

through 9.

The system must write the CFI Exit command to return to

Read mode from the CFI Query mode.

Security ID

The GLS36VF160xG offer a 136-word Security ID space.

The Secure ID space is divided into two segments — one

128-bit, factory-programmed, segment and one 256-Byte,

user programmed segment. The first segment is pro-

grammed and locked at Greenliant and contains a 128 bit

Unique ID which uniquely identifies the device. The user

segment is left un-programmed for the customer to program

as desired.

The user segment of the Security ID can be programmed

using the Security ID Program command. End-of-Write sta-

tus is checked by reading the toggle bits. Data# Polling is

not used for Security ID End-of-Write detection.

Once the programming is complete, lock the Sec ID by

issuing the User Sec ID Program Lock-Out command.

Locking the Sec ID disables any corruption of this space.

Note that regardless of whether or not the Sec ID is locked,

the Sec ID segments can not be erased.

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

The Secure ID space can be queried by executing a three-

byte command sequence with Query Sec ID command

(88H) at address 555H in the last byte sequence. See Fig-

ure 20 for timing diagram. To exit this mode, the Exit Sec ID

command should be executed. Refer to Table 6 for more

details.

Product Identification

The Product Identification mode identifies the devices as

GLS36VF1601G or GLS36VF1602G and the manufac-

turer as Greenliant. For details, see Table 3 for software

operation, Figure 17 for the Software ID Entry and Read

timing diagram, and Figure 27 for the Software ID Entry

command sequence flowchart.

The addresses A19 and A18 indicate a bank address.

When the addressed bank is switched to Product Identifi-

cation mode, it is possible to read another address from the

same bank without issuing a new Software ID Entry com-

mand.

Note: BK = Bank Address (A19-A18)

Product Identification Mode Exit/CFI Mode Exit

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. The exit is

accomplished by issuing the Software ID Exit command

sequence, which returns the device to the Read mode.

This command may also be used to reset the device to the

Read mode after any inadvertent transient condition that

causes the device to behave abnormally. Please note that

the Software ID Exit/CFI Exit command is ignored during an

internal Program or Erase operation. See Table 6 for the

software command code, Figure 19 for timing waveform

and Figure 28 for a flowchart.

FIGURE 1: Functional Block Diagram

TABLE 3: Product Identification

Address Data

Manufacturer’s ID BK0000H 00BFH

Device ID

GLS36VF1601G BK0001H 7343H

GLS36VF1602G BK0001H 7344H

T3.0 1342

1342 B01.0

SuperFlash Memory

12 Mbit Bank

I/O Buffers

SuperFlash Memory

4 Mbit Bank

Memory

Address

DQ15/A-1 - DQ0

CE#

WP#

WE#

OE#

Control

Logic

RST#

BYTE#

RY/BY#

Address

Buffers

(8 KWord Sector Protection)

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 2: GLS36VF1601G, 1M x16 Concurrent SuperFlash Dual-Bank Memory Organization

FFFFFH

F8000H Block 31

F7FFFH

F0000H Block 30

EFFFFH

E8000H Block 29

E7FFFH

E0000H Block 28

DFFFFH

D8000H Block 27

D7FFFH

D0000H Block 26

CFFFFH

C8000H Block 25

C7FFFH

C0000H Block 24

Bank 2

BFFFFH

B8000H Block 23

B7FFFH

B0000H Block 22

AFFFFH

A8000H Block 21

A7FFFH

A0000H Block 20

9FFFFH

98000H Block 19

97FFFH

90000H Block 18

8FFFFH

88000H Block 17

87FFFH

80000H Block 16

7FFFFH

78000H Block 15

77FFFH

70000H Block 14

6FFFFH

68000H Block 13

67FFFH

60000H Block 12

5FFFFH

58000H Block 11

57FFFH

50000H Block 10

4FFFFH

48000H Block 9

47FFFH

40000H Block 8

3FFFFH

38000H Block 7

37FFFH

30000H Block 6

2FFFFH

28000H Block 5

27FFFH

20000H Block 4

1FFFFH

18000H Block 3

17FFFH

10000H Block 2

0FFFFH

08000H Block 1

07FFFH

02000H

01FFFH

00000H

Block 0

Bank 1

Bottom Sector Protection; 32 KWord Blocks; 2 KWord Sectors

8 KWord Sector Protection

(4-2 KWord Sectors) 1342 F01.0

Note: The address input range in x16 mode (BYTE#=VIH) is A19-

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 3: GLS36VF1601G, 2M x8 Concurrent SuperFlash Dual-Bank Memory Organization

1FFFFFH

1F0000H Block 31

1EFFFFH

1E0000H Block 30

1DFFFFH

1D0000H Block 29

1CFFFFH

1C0000H Block 28

1BFFFFH

1B0000H Block 27

1AFFFFH

1A0000H Block 26

19FFFFH

190000H Block 25

18FFFFH

180000H Block 24

Bank 2

17FFFFH

170000H Block 23

16FFFFH

160000H Block 22

15FFFFH

150000H Block 21

14FFFFH

140000H Block 20

13FFFFH

130000H Block 19

12FFFFH

120000H Block 18

11FFFFH

110000H Block 17

10FFFFH

100000H Block 16

0FFFFFH

0F0000H Block 15

0EFFFFH

0E0000H Block 14

0DFFFFH

0D0000H Block 13

0CFFFFH

0C0000H Block 12

0BFFFFH

0B0000H Block 11

0AFFFFH

0A0000H Block 10

09FFFFH

090000H Block 9

08FFFFH

080000H Block 8

07FFFFH

070000H Block 7

06FFFFH

060000H Block 6

05FFFFH

050000H Block 5

04FFFFH

040000H Block 4

03FFFFH

030000H Block 3

02FFFFH

020000H Block 2

01FFFFH

010000H Block 1

00FFFFH

004000H

003FFFH

000000H

Block 0

Bank 1

Bottom Sector Protection; 64 KByte Blocks; 4 KByte Sectors

6 KByte Sector Protection

(4-4 KByte Sectors) 1342 F02.0

Note: The address input range in x8 mode (BYTE#=VIL)

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 4: GLS36VF1602G, 1M x16 Concurrent SuperFlash Dual-Bank Memory Organization

Top Block Protection; 32 KWord Blocks; 2 KWord Sectors

FFFFFH

FE000H

FDFFFH

F8000H

Block 31

F7FFFH

F0000H Block 30

EFFFFH

E8000H Block 29

E7FFFH

E0000H Block 28

DFFFFH

D8000H Block 27

D7FFFH

D0000H Block 26

CFFFFH

C8000H Block 25

C7FFFH

C0000H Block 24

BFFFFH

B8000H Block 23

B7FFFH

B0000H Block 22

AFFFFH

A8000H Block 21

A7FFFH

A0000H Block 20

9FFFFH

98000H Block 19

97FFFH

90000H Block 18

8FFFFH

88000H Block 17

87FFFH

80000H Block 16

7FFFFH

78000H Block 15

77FFFH

70000H Block 14

6FFFFH

68000H Block 13

67FFFH

60000H Block 12

5FFFFH

58000H Block 11

57FFFH

50000H Block 10

4FFFFH

48000H Block 9

47FFFH

40000H Block 8

Bank 2

3FFFFH

38000H Block 7

37FFFH

30000H Block 6

2FFFFH

28000H Block 5

27FFFH

20000H Block 4

1FFFFH

18000H Block 3

17FFFH

10000H Block 2

0FFFFH

08000H Block 1

07FFFH

00000H Block 0

Bank 1

KWord Block Protection

(4 - 2 KWord Sectors)

1342 F03.0

Note: The address input range in x16 mode (BYTE#=VIH) is

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 5: GLS36VF1602G, 2M x8 Concurrent SuperFlash Dual-Bank Memory Organization

Top Block Protection; 64 KByte Blocks; 4 KByte Sectors

Block 31

Block 30

Block 29

Block 28

Block 27

Block 26

Block 25

Block 24

Block 23

Block 22

Block 21

Block 20

Block 19

Block 18

Block 17

Block 16

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 8

Bank 2

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

Bank 1

6 KByte Block Protection

(4 - 4 KByte Sectors)

1342 F04

1FBFFFH

1F0000H

1FFFFFH

1FC000H

1EFFFFH

1E0000H

1DFFFFH

1D0000H

1CFFFFH

1C0000H

1BFFFFH

1B0000H

1AFFFFH

1A0000H

19FFFFH

190000H

18FFFFH

180000H

17FFFFH

170000H

16FFFFH

160000H

15FFFFH

150000H

14FFFFH

140000H

13FFFFH

130000H

12FFFFH

120000H

11FFFFH

110000H

10FFFFH

100000H

0FFFFFH

0F0000H

0EFFFFH

0E0000H

0DFFFFH

0D0000H

0CFFFFH

0C0000H

0BFFFFH

0B0000H

0AFFFFH

0A0000H

09FFFFH

090000H

08FFFFH

080000H

07FFFFH

070000H

06FFFFH

060000H

05FFFFH

050000H

04FFFFH

040000H

03FFFFH

030000H

02FFFFH

020000H

01FFFFH

010000H

00FFFFH

000000H

Note: The address input range in x8 mode (BYTE#=VIL) is

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 6: Pin Assignments for 48-ball TFBGA (6mm x 8mm)

FIGURE 7: Pin Assignments for 48-lead TSOP (12mm x 20mm)

A13

WE#

RY/BY#

A12

RST#

WP#

A17

A14

A10

A18

A15

A11

A19

A16

DQ7

DQ5

DQ2

DQ0

BYTE#

DQ14

DQ12

DQ10

DQ8

CE#

NOTE*

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

1342 48-tfbga P1.0

TOP VIEW (balls facing down)

A B C D E F G H

Note* = DQ

-1

1342 48-tsop P02.0

Standard Pinout

Top View

Die Up

A15

A14

A13

A12

A11

A10

A19

WE#

RST#

WP#

RY/BY#

A18

A17

A16

BYTE#

VSS

DQ15/A

-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VDD

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 8: Pin Assignments for 56-lead LFBGA (8mm x 10mm)

TABLE 4: Pin Description

Symbol Name Functions

A19-A0Address Inputs To provide memory addresses. During Sector-Erase and Hardware Sector Protection,

A19-A11 address lines will select the sector. During Block-Erase A19-A15 address

lines will select the block.

DQ14-DQ0Data Input/Output To output data during Read cycles and receive input data during Write cycles

Data is internally latched during a Write cycle. The outputs are in tri-state when

OE# or CE# is high.

DQ15/A-1 Data Input/Output

and LBS Address

DQ15 is used as data I/O pin when in x16 mode (BYTE# = “1”)

A-1 is used as the LSB address pin when in x8 mode (BYTE# = “0”)

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers

WE# Write Enable To control the Write operations

RST# Hardware Reset To reset and return the device to Read mode

RY/BY# Ready/Busy# To output the status of a Program or Erase operation

RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required

to allow RY/BY# to transition high indicating the device is ready to read.

WP# Write Protect To protect and unprotect top or bottom 8 KWord (4 outermost sectors) from Erase or

Program operation.

BYTE# Word/Byte Configuration To select 8-bit or 16-bit mode.

VDD Power Supply To provide 2.7-3.6V power supply voltage

VSS Ground

NC No Connection Unconnected pins

T4.0 1342

1342 56-lfbga P1.0

A11

WE#

WP#

A15

A12

A19

RST#

A13

RY/BY#

A18

A14

A10

A17

A16

DQ6

DQ1

VSS

BYTE#

DQ15/A-1

DQ13

DQ4

DQ3

DQ9

OE#

CE#

VSS

DQ7

DQ12

VDD

DQ10

DQ0

DQ14

DQ5

DQ11

DQ2

DQ8

A B C D E F G H

TOP VIEW (balls facing down)

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

TABLE 5: Operation Modes Selection

Mode1CE# OE# WE# DQ7-DQ0

DQ15-DQ8

AddressBYTE# = VIH BYTE# = VIL

Read VIL VIL VIH DOUT DOUT DQ14-DQ8 = High Z AIN

Program VIL VIH VIL DIN DIN DQ15 = A-1 AIN

Erase VIL VIH VIL X2X High Z Sector or Block

address,

555H for Chip-Erase

Standby VIHC X X High Z High Z High Z X

Write Inhibit X VIL X High Z / DOUT High Z / DOUT High Z X

XXV

IH High Z / DOUT High Z / DOUT High Z X

Product

Identification

Software

Mode

VIL VIL VIH Manufacturer’s ID

(BFH)

Manufacturer’s ID

(00H)

High Z See Table 6

Device ID3Device ID3High Z

T5.2 1342

1. RST# = VIH for all described operation modes

2. X can be VIL or VIH, but no other value.

3. Device ID = GLS36VF1601G = 7343H,

GLS36VF1602G = 7344H

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

TABLE 6: Software Command Sequence

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Program 555H AAH 2AAH 55H 555H A0H WA3Data

Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX450H

Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX430H

Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Erase-Suspend XXXXH B0H

Erase-Resume XXXXH 30H

Query Sec ID5555H AAH 2AAH 55H 555H 88H

User Security ID

Program

555H AAH 2AAH 55H 555H A5H SIWA6Data

User Security ID

Program Lock-out7

555H AAH 2AAH 55H 555H 85H XXH 0000H

Software ID Entry8555H AAH 2AAH 55H BKX9

555H

90H

CFI Query Entry 555H AAH 2AAH 55H BKX9

555H

98H

CFI Query Entry BKX9

55H

98H

Software ID Exit/

CFI Exit/

Sec ID Exit10,11

555H AAH 2AAH 55H 555H F0H

Software ID Exit/

CFI Exit/

Sec ID Exit10,11

XXH F0H

T6.0 1342

1. Address format A10-A0 (Hex), Addresses A19-A11 can be VIL or VIH, but no other value, for the command sequence when in x16 mode.

When in x8 mode, Addresses A19-A12, Address A-1 and DQ14-DQ8 can be VIL or VIH, but no other value, for the command sequence.

2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence

3. WA = Program word/byte address

4. SAX for Sector-Erase; uses A19-A11 address lines

BAX for Block-Erase; uses A19-A15 address lines

5. For GLS36VF1601G,

Greenliant ID is read with A3 = 0 (Address range = 00000H to 00007H),

User ID is read with A3 = 1 (Address range = = 00008H to 00087H).

Lock Status is read with A7-A0 = 000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.

For GLS36VF1602G,

Greenliant ID is read with A3 = 0 (Address range = C0000H to C0007H),

User ID is read with A3 = 1 (Address range = = C0008H to C0087H).

Lock Status is read with A7-A0 = C00FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.

6. SIWA = User Security ID Program word/byte address

For GLS36VF1601G, valid Word-Addresses for User Sec ID are from 00008H to 00087H.

For GLS36VF1602G, valid Word-Addresses for User Sec ID are from C0008H to C0087H.

All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode.

7. The User Security ID Program Lock-out command must be executed in x16 mode (BYTE#=VIH).

8. The device does not remain in Software Product Identification mode if powered down.

9. A19 and A18 = BKX (Bank Address): address of the bank that is switched to Software ID/CFI Mode

With A17-A1 = 0;Greenliant Manufacturer’s ID = 00BFH, is read with A0 = 0

GLS36VF1601G Device ID = 7343H, is read with A0 = 1

GLS36VF1602G Device ID = 7344H, is read with A0 = 1

10. Both Software ID Exit operations are equivalent

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the

User Sec ID mode again (the programmed “0” bits cannot be reversed to “1”).

For GLS36VF1601G, valid Word-Addresses for User Sec ID are from 00008H to 00087H.

For GLS36VF1602G, valid Word-Addresses for User Sec ID are from C0008H to C0087H.

TABLE 7: CFI Query Identification String1

1. Refer to CFI publication 100 for more details.

Address

x16 Mode

Address

x8 Mode Data2

2. In x8 mode, only the lower byte of data is output.

Description

10H 20H 0051H Query Unique ASCII string “QRY”

11H 22H 0052H

12H 24H 0059H

13H 26H 0002H Primary OEM command set

14H 28H 0000H

15H 2AH 0000H Address for Primary Extended Table

16H 2CH 0000H

17H 2EH 0000H Alternate OEM command set (00H = none exists)

18H 30H 0000H

19H 32H 0000H Address for Alternate OEM extended Table (00H = none exits)

1AH 34H 0000H

T7.0 1342

TABLE 8: System Interface Information

Address

x16 Mode

Address

x8 Mode Data1

1. In x8 mode, only the lower byte of data is output.

Description

1BH 36H 0027H VDD Min (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH 38H 0036H VDD Max (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH 3AH 0000H VPP min (00H = no VPP pin)

1EH 3CH 0000H VPP max (00H = no VPP pin)

1FH 3EH 0004H Typical time out for Program 2N µs (24 = 16 µs)

20H 40H 0000H Typical time out for min size buffer program 2N µs (00H = not supported)

21H 42H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)

22H 44H 0006H Typical time out for Chip-Erase 2N ms (26 = 64 ms)

23H 46H 0001H Maximum time out for Program 2N times typical (21 x 24 = 32 µs)

24H 48H 0000H Maximum time out for buffer program 2N times typical

25H 4AH 0001H Maximum time out for individual Sector-/Block-Erase 2N times typical (21 x 24 = 32 ms)

26H 4CH 0001H Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)

T8.0 1342

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

TABLE 9: Device Geometry Information

Address

x16 Mode

Address

x8 Mode Data1Description

27H 4EH 0015H Device size = 2N Bytes (15H = 21; 221 = 2 MByte)

28H 50H 0002H Flash Device Interface description; 0002H = x8/x16 asynchronous interface

29H 52H 0000H

2AH 54H 0000H Maximum number of bytes in multi-byte write = 2N (00H = not supported)

2BH 56H 0000H

2CH 58H 0002H Number of Erase Sector/Block sizes supported by device

2DH 5AH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH 5CH 0001H y = 511 + 1 = 512 sectors (01FFH = 512)

2FH 5EH 0010H

30H 60H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)

31H 62H 001FH Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H 64H 0000H y = 31 + 1 = 32 blocks (001FH = 31)

33H 66H 0000H

34H 68H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

T9.1 1342

1. In x8 mode, only the lower byte of data is output.

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Operating Range:

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

AC Conditions of Test

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 23 and 24

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

TABLE 10: DC Operating Characteristics VDD = 2.7-3.6V

Symbol Parameter

Limits

Test ConditionsFreq Min Max Units

IDD1Active VDD Current

Read 5 MHz 15 mA CE#=VIL, WE#=OE#=VIH

1 MHz 4 mA

Program and Erase 30 mA CE#=WE#=VIL, OE#=VIH

Concurrent Read/Write 5 MHz 45 mA CE#=VIL, OE#=VIH

1 MHz 35 mA

ISB Standby VDD Current 20 µA CE#, RST#=VDD±0.3V

IALP Auto Low Power VDD Current 20 µA CE#=0.1V, VDD=VDD Max

WE#=VDD-0.1V

Address inputs=0.1V or VDD-0.1V

IRT Reset VDD Current 20 µA RST#=GND

ILI Input Leakage Current 1 µA VIN =GND to VDD, VDD=VDD Max

ILIW Input Leakage Current

on WP# pin and RST# pin

10 µA WP#=GND to VDD, VDD=VDD Max

RST#=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 1 µA VOUT =GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7 VDD VDD+0.3 V VDD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 VDD+0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T10.1 1342

1. Address input = VILT/VIHT, VDD=VDD Max (See Figure 23)

TABLE 11: Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Write Operation 100 µs

T11.0 1342

TABLE 12: Capacitance (TA = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 10 pF

CIN1Input Capacitance VIN = 0V 10 pF

T12.0 1342

TABLE 13: Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T13.0 1342

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

AC CHARACTERISTICS

TABLE 14: Read Cycle Timing Parameters VDD = 2.7-3.6V

Symbol Parameter Min Max Units

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1CE# High to High-Z Output 16 ns

TOHZ1OE# High to High-Z Output 16 ns

TOH1Output Hold from Address Change 0 ns

TRP1RST# Pulse Width 500 ns

TRHR1RST# High before Read 50 ns

TRY1,2

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

This parameter does not apply to Chip-Erase operations.

RST# Pin Low to Read Mode 20 µs

T14.1 1342

TABLE 15: Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

TBP Program Time 10 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 40 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 50 ms

TES Erase-Suspend Latency 10 µs

TBY1,2

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

This parameter does not apply to Chip-Erase operations.

RY/BY# Delay Time 90 ns

TBR1Bus Recovery Time 0µs

T15.1 1342

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 9: Read Cycle Timing Diagram

FIGURE 10: WE# Controlled Program Cycle Timing Diagram

1342 F05.0

DDRESSES

DQ15-0

WE#

OE#

CE#

VIH

HIGH-Z HIGH-Z

D ATA VALIDD ATA VALID

TRC TAA

TCE

TOE

TOLZ

TCLZ TOH TCHZ

TOHZ

1342 F06.0

ADDRESSES

DQ15-0

CE#

555 2AA 555 ADDR

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

OE#

WE#

RY/BY#

VALID

TDH

TWPH

TAS

TCH

TCS

TAH

TWP

TDS

TBY TBR

TBP

Note: X can be VIL or VIH, but no other value.

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 11: CE# Controlled Program Cycle Timing Diagram

FIGURE 12: Data# Polling Timing Diagram

1342 F07.1

DDRESSES

DQ15-0

CE#

555 2AA 555 ADDR

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

OE#

WE#

RY/BY#

VALID

TDH

TCPH

TAS

TCH

TCS

TAH

TCP

TDS

TBY TBR

TBP

Note: X can be VIL or VIH, but no other value.

1342 F08.1

ADDRESS A19-0

DQ7DATA

WE#

OE#

CE#

RY/BY#

DATA# DATA# DATA

TOES

TOEH

TBY

TCE

TOE

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 13: Toggle Bit Timing Diagram

FIGURE 14: WE# Controlled Chip-Erase Timing Diagram

1342 F09.1

ADDRESS A19-0

DQ7

WE#

OE#

CE#

VALID DATA

TOES

TOEH

TCE

TOE

TWO READ CYCLES

WITH SAME OUTPUTS

TBR

1342 F10.1

ADDRESSES

DQ15-0

WE#

555 2AA 2AA555 555

XX55 XX10

XX55XXAA XX80 XXAA

555

OE#

CE#

RY/BY#

VALID

SIX-BYTE CODE FOR CHIP-ERASE

TOEH

TSCE

TBY TBR

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchangeable

as long as minimum timings are met. See Table 15 on page 19.

X can be VL or VIH, but not other value.

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 15: WE# Controlled Block-Erase Timing Diagram

FIGURE 16: WE# Controlled Sector-Erase Timing Diagram

1342 F11.1

ADDRESSES

DQ15-0

WE#

555 2AA 2AA555 555

XX55 XX30

XX55XXAA XX80 XXAA

BAX

OE#

CE#

RY/ BY#

VALID

SIX-BYTE CODE FOR CHIP-ERASE

TWP

TBE

TBY TBR

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are

interchangeable as long as minimum timings are met. See Table 15 on page 19.

BAx = Block Address

X can be VL or VIH, but not other value.

1342 F12.1

ADDRESSES

15-0

WE#

555 2AA 2AA555 555

XX55 XX50

XX55XXAA XX80 XXAA

OE#

CE#

RY/ BY#

VALID

SIX-BYTE CODE FOR CHIP-ERASE

Note: This device also supports CD# controlled Sector-Erase operation. The WE# and CE# signals are

interchangeable as long as minimum timings are met. See Table 15 on page 19.

BAx = Block Address

X can be VL or VIH, but no other value.

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 17: Software ID Entry and Read

FIGURE 18: CFI Entry and Read

1342 F13.1

DDRESSES

DQ15-0

WE#

555 2AA 555 0000 0001

OE#

CE#

00BF Device IDXX55XXAA XX90

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

TWPH

TIDA

TWP

TAA

Note: Device ID = 7343H for GLS36VF1601G, and 7344H for GLS36VF1602G

X can be VIL or VIH, but no other value.

1342 F14.1

DDRESSES

DQ15-0

WE#

555 2AA 555

OE#

CE#

XX55XXAA XX98

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

TWPH

TIDA

TWP

TAA

Note: X can be VIL or VIH, but no other value.

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 19: Software ID Exit/CFI Exit

FIGURE 20: Sec ID Entry

1342 F15.1

ADDRESSES

DQ15-0

WE#

555 2AA 555

OE#

CE#

XX55XXAA XXF0

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

TWPH

TIDA

TWP

Note: X can be VIL or VIH, but no other value.

1342 F16.1

DDRESSES

DQ15-0

WE#

555 2AA 555

OE#

CE#

XX55XXAA XX88

SW0 SW2SW1

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

TWPH

TIDA

TWP

TAA

Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1 µs after the command

sequence.

X can be VIL or VIH, but no other value.

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 21: RST# Timing Diagram (When no internal operation is in progress)

FIGURE 22: RST# Timing Diagram (During Sector- or Block-Erase operation)

1342 F17.0

RY/BY#

RST#

CE#/OE#

TRP

TRHR

1342 F18.0

RY/BY#

CE#

OE#

TRP

TRY

TBR

RST#

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 23: AC Input/Output Reference Waveforms

FIGURE 24: A Test Load Example

1342 F19.0

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10%  90%) are <5 ns.

Note: VIT - VINPUT Te st

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1342 F20.0

T O TESTER

TO DUT

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 25: Program Algorithm

1342 F21.0

Start

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXA0H

Address: 555H

Load

Address/Data

Wait for end of

Program (T

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

ote: X can be VIL or VIH, but no other value.

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 26: Wait Options

1342 F22.0

W ait T

SCE

, T

or T

Program/Erase

Initiated

Internal Timer Toggle Bit

Yes

Program/Erase

Completed

Does DQ

match?

Read same

byte/word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read

byte/word

Is DQ

true data?

Read DQ

Program/Erase

Initiated

Program/Erase

Initiated

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 27: Software Product ID/CFI/Sec ID Entry Command Flowcharts

1342 F23.0

Load data: XXAAH

Address: 555H

Software Product ID Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX90H

Address: 555H

W ait TIDA

Read Software ID

Load data: XXAAH

Address: 555H

CFI Query Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX98H

Address: 555H

W ait TIDA

Read CFI data

Load data: XXAAH

Address: 555H

Sec ID Query Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX88H

Address: 555H

Wait TIDA

Read Sec ID

X can be VIL or VIH, but no other value

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 28: Software Product ID/CFI/Sec ID Exit Command Flowcharts

1342 F24.0

Load data: XXAAH

Address: 555H

Software ID Exit/CFI Exit/Sec ID Exit

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XXF0H

Address: 555H

Load data: XXF0H

Address: XXH

Return to normal

operation

W ait TIDA

Return to normal

operation

X can be V

or V

IH,

but no other value

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 29: Erase Command Sequence

1342F25.0

Load data: XXAAH

Address: 555H

Chip-Erase

ommand Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX10H

Address: 555H

Load data: XXAAH

Address: 555H

W ait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX50H

Address: SAX

Load data: XXAAH

Address: 555H

W ait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 555H

Block-Erase

Command Sequenc

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX30H

Address: BAX

Load data: XXAAH

Address: 555H

W ait TBE

Block erased

to FFFFH

Note: X can be VIL or VIH, but no other value.

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

PRODUCT ORDERING INFORMATION

Valid combinations for GLS36VF1601G

GLS36VF1601G-70-4C-B3KE GLS36VF1601G-70-4C-EKE GLS36VF1601G-70-4C-L1PE

GLS36VF1601G-70-4I-B3KE GLS36VF1601G-70-4I-EKE GLS36VF1601G-70-4I-L1PE

Valid combinations for GLS36VF1602G

GLS36VF1602G-70-4C-B3KE GLS36VF1602G-70-4C-EKE GLS36VF1602G-70-4C-L1PE

GLS36VF1602G-70-4I-B3KE GLS36VF1602G-70-4I-EKE GLS36VF1602G-70-4I-L1PE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your Greenliant sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Environmental Attribute

E1 = non-Pb

Package Modifier

K = 48 balls or leads

Package Type

B3 = TFBGA (6mm x 8mm)

E =TSOP (type 1, die up, 12mm x 20mm)

L1P = LFBGA (8mm x 10mm)

Temperature Range

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

Bank Split

1 = 4 Mbit + 12 Mbit

2 = 12 Mbit + 4 Mbit

Device Density

160 = 1 Mbit x16 or

2 Mbit x8

Voltage

V = 2.7-3.6V

Product Series

36 = Concurrent SuperFlash

1. Environmental suffix “E” denotes non-Pb solder.

Greenliant non-Pb solder devices are “RoHS Compli-

ant”.

GLS 36 VF 1601G - 70 - 4C - B3K E

XX XX XXXXX - XXX -XX-XXX X

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

PACKAGING DIAGRAMS

FIGURE 30: 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm

Greenliant Package Code: B3K

A1 CORNER

H G F E D C B A

A B C D E F G H

BOTTOM VIEWTOP VIEW

SIDE VIEW

SEATING PLANE 0.35 ± 0.05

1.10 ± 0.10

0.12

6.00 ± 0.20

0.45 ± 0.05

(48X)

A1 CORNER

8.00 ± 0.20

0.80

4.00

0.80

5.60

48-tfbga-B3K-6x8-450mic

-4

ote: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1mm

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 31: 48-lead Thin Small Outline Package (TSOP) 12mm x 20mm

Greenliant Package Code: EK

1.05

0.95

0.70

0.50

18.50

18.30

20.20

19.80

0.70

0.50

12.20

11.80

0.27

0.17

0.15

0.05

48-tsop-EK-8

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

0°- 5°

DETAIL

Pin # 1 Identifier

0.50

BSC

Data Sheet

16 Mbit Concurrent SuperFlash

GLS36VF1601G / GLS36VF1602G

FIGURE 32: 56-Ball, Low-Profile, Fine-Pitch Ball Grid Array (LFBGA) 8mm x 10mm

Greenliant Package Code: L1P

TABLE 16: Revision History

Number Description Date

00 •Initial release of data sheet Dec 2006

01 •Edited Tby TY/BY# Delay Time in Table 15 on page 19 from 90ns Min to 90ns Max Nov 2009

02 •Transferred from SST to Greenliant May 2010

03 •Corrected XX50 and XX30 values in Figures 15 and 16 on page 23. Nov 2010

H G F E D C B A

A B C D E F G H

SIDE VIEW

SEATING PLANE 0.35 ± 0.05

1.30 ± 0.10

0.12

0.45 ± 0.05

(56X)

0.80

5.60

0.80

5.60

56-lfbga-L1P-8x10-450mic-4

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1mm

A1 CORNER

BOTTOM VIEWTOP VIEW

8.00 ± 0.20

A1 CORNER

10.00 ± 0.20

Greenliant, the Greenliant logo and NANDrive are trademarks of Greenliant Systems, Ltd.

All trademarks and registered trademarks are the property of their respective owners.

These specifications are subject to change without notice.

CSF is a trademark and SuperFlash is a registered trademark of Silicon Storage Technology, Inc., a wholly owned subsidiary of

Microchip Technology Inc.