PIC16LC642-04/SOA14 - Microchip Technology, Inc.



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 1

Devices included in this data sheet:

• PIC16C641

• PIC16C642

• PIC16C661

• PIC16C662

High Performance RISC CPU:

• Only 35 instructions to learn

• All single-cycle instructions (200 ns), except for

program branches which are two-cycle

• Operating speed:

- DC - 20 MHz clock input

- DC - 200 ns instruction cycle

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative addressing modes

Peripheral Features:

• Up to 33 I/O pins with individual direction control

• High current sink/source for direct LED drive

• Analog comparator module with:

- Two analog comparators

- Programmable on-chip voltage reference

REF

) module

- Programmable input multiplexing from device

inputs and internal voltage reference

- Comparator outputs can be output signals

• Timer0: 8-bit timer/counter with 8-bit

programmable prescaler

Special Microcontroller Features:

• Power-on Reset (POR)

• Power-up Timer (PWRT) and

Oscillator Start-up Timer (OST)

• Brown-out Reset

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options

• Serial in-circuit programming (via two pins)

Device Program

Memory x14 Data

Memory x8

PIC16C641 2K 128

PIC16C642 4K 176

PIC16C661 2K 128

PIC16C662 4K 176

Pin Diagrams

PDIP, SOIC, Windowed CERDIP

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

VDD

VSS

RC7

RC6

RC5

RC4

PIC16C64X

MCLR/VPP

RA0/AN0

RA1/AN1

RA2/AN2/VREF

RA3/AN3

RA4/T0CKI

RA5

VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0

RC1

RC2

RC3

PDIP, Windowed CERDIP

PIC16C66X

MCLR/VPP

RA0/AN0

RA1/AN1

RA2/AN2/VREF

RA3/AN3

RA4/T0CKI

RA5

RE0/RD

OSC1/CLKIN

OSC2/CLKOUT

RE1/WR

RE2/CS

VDD

VSS

RD0/PSP0

RD1/PSP1

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

VDD

VSS

RD7/PSP7

RD6/PSP6

RD4/PSP4

RC7

RC6

RC5

RC4

RD3/PSP3

RD2/PSP2

RD5/PSP5

RC0

RC1

RC2

RC3

• Four user programmable ID locations

• Program Memory Parity Error checking circuitry

with Parity Error Reset (PER)

•

CMOS Technology:

• Low-power , high-speed CMOS EPROM technology

• Fully static design

• Wide operating voltage range: 3.0V to 6.0V

• Commercial, Industrial and Automotive

temperature ranges

• Low power consumption

- < 2.0 mA @ 5.0V, 4.0 MHz

- 15

A typical @ 3.0V, 32 kHz

- < 1.0

A typical standby current @ 3.0V

8-Bit EPROM Microcontrollers with Analog Comparators

PIC16C64X & PIC16C66X

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 2

Preliminary



1996 Microchip Technology Inc.

Pin Diagrams (Cont.’d)

181920212223242526

7654321

272829

40414243

PIC16C66X

RA4/T0CKI

RA5

RE0/RD

OSC1/CLKIN

OSC2/CLKOUT

RC0

RE1/WR

RE2/CS

VDD

VSS

RB3

RB2

RB1

RB0/INT

VDD

VSS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7

RA3/AN3

RA2/AN2/VREF

RA1/AN1

RA0/AN0

MCLR/VPP

RB7

RB6

RB5

RB4

RC6

RC5

RC4

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3

RC2

RC1

1819 20 21 2212 1314 15

44 43 42 41 40 39

1617

36 3435

PIC16C66X

RA3/AN3

RA2/AN2/VREF

RA1/AN1

RA0/AN0

MCLR/VPP

RB7

RB6

RB5

RB4

RC6

RC5

RC4

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3

RC2

RC1

RC0

OSC2/CLKOUT

OSC1/CLKIN

VSS

VDD

RE2/CS

RE1/WR

RE0/RD

RA5

RA4/T0CKI

RC7

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

VSS

VDD

RB0/INT

RB1

RB2

RB3

TQFP

PLCC



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 3

PIC16C64X & PIC16C66X

Table of Contents

1.0 General Description..........................................................................................................................................5

2.0 PIC16C64X & PIC16C66X Device Varieties ....................................................................................................7

3.0 Architectural Overview......................................................................................................................................9

4.0 Memory Organization .....................................................................................................................................17

5.0 I/O Ports..........................................................................................................................................................29

6.0 Timer0 Module................................................................................................................................................41

7.0 Comparator Module........................................................................................................................................47

8.0 Voltage Reference Module.............................................................................................................................53

9.0 Special Features of the CPU..........................................................................................................................55

10.0 Instruction Set Summary ................................................................................................................................73

11.0 Development Support.....................................................................................................................................87

12.0 Electrical Specifications..................................................................................................................................91

13.0 Device Characterization Information.............................................................................................................103

14.0 Packaging Information..................................................................................................................................105

Appendix A: Enhancements......................................................................................................................................115

Appendix B: Compatibility.........................................................................................................................................115

Appendix C: What’s New ..........................................................................................................................................116

Appendix D: What’s Changed...................................................................................................................................116

Appendix E: PIC16/17 Microcontrollers.....................................................................................................................117

Pin Compatibility .........................................................................................................................................................125

Index ...........................................................................................................................................................................127

List of Examples..........................................................................................................................................................129

List of Figures..............................................................................................................................................................129

List of Tables...............................................................................................................................................................130

On-Line Support..........................................................................................................................................................131

Reader Response.......................................................................................................................................................132

PIC16C64X & PIC16C66X Product Identification System..........................................................................................135

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional

amount of time to ensure that these documents are correct. However, we realize that we may have missed a few

things. If you ﬁnd any information that is missing or appears in error, please use the reader response form in the

back of this data sheet to inform us. We appreciate your assistance in making this a better document.

PIC16C64X & PIC16C66X

DS30559A-page 4

Preliminary



1996 Microchip Technology Inc.

NOTES:



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 5

PIC16C64X & PIC16C66X

1.0 GENERAL DESCRIPTION

PIC16C64X & PIC16C66X devices are 28-pin and

40-pin EPROM-based members of the versatile

PIC16CXXX family of low-cost, high-performance,

CMOS, fully-static, 8-bit microcontrollers.

All PIC16/17 microcontrollers employ an advanced

RISC architecture. The PIC16CXXX family has

enhanced core features, eight-level deep stack, and

multiple internal and external interrupt sources. The

separate instruction and data buses of the Harvard

architecture allow a 14-bit wide instruction word with

the separate 8-bit wide data. The two-stage instruction

pipeline allows all instructions to execute in a sin-

gle-cycle, except for program branches (which require

two cycles). A total of 35 instructions (reduced instruc-

tion set) are available. Additionally, a large register set

gives some of the architectural innovations used to

achieve a very high performance.

PIC16CXXX microcontrollers typically achieve a 2:1

code compression and a 4:1 speed improvement over

other 8-bit microcontrollers in its class.

The PIC16C641 has 128 bytes of RAM and the

PIC16C642 has 176 bytes of RAM. Both devices have

22 I/O pins, and an 8-bit timer/counter with an 8-bit pro-

grammable prescaler . In addition, they have two analog

comparators with a programmable on-chip voltage ref-

erence module. Program Memory has internal parity

error detection circuitry with a Parity Error Reset. The

comparator module is ideally suited for applications

requiring a low-cost analog interface (e.g., battery

chargers, threshold detectors, white goods

controllers, etc.).

The PIC16C661 has 128 bytes of RAM and the

PIC16C662 has 176 bytes of RAM. Both devices have

33 I/O pins, and an 8-bit timer/counter with an 8-bit pro-

grammable prescaler. They also have an 8-bit Parallel

Slave Port. In addition, the devices have two analog

comparators with a programmable on-chip voltage ref-

erence module. Program Memory has internal parity

error detection circuitry with a Parity Error Reset. The

comparator module is ideally suited for applications

requiring a low-cost analog interface (e.g., battery

chargers, threshold detectors, white goods

controllers, etc.).

PIC16CXXX devices have special features to reduce

external components, thus reducing cost, enhancing

system reliability and reducing power consumption.

There are four oscillator options, of which the single pin

RC oscillator provides a low-cost solution, the LP

oscillator minimizes power consumption, XT is a

standard crystal, and the HS is for High Speed crystals.

The SLEEP (power-down) mode offers power saving.

The user can wake-up the chip from SLEEP through

several external and internal interrupts and resets.

A highly reliable Watchdog Timer (WDT) with its own

on-chip RC oscillator provides protection against soft-

ware lock-up.

A UV-erasable CERDIP-packaged version is ideal for

code development while the cost-effective One-Time

Programmable (OTP) version is suitable for production

in any volume.

The PIC16CXXX series ﬁt perfectly in applications

ranging from battery chargers to low-power remote

sensors. The EPROM technology makes

customization of application programs (detection

levels, pulse generation, timers, etc.) extremely fast

and convenient. The small footprint packages make

this microcontroller series perfect for all applications

with space limitations. Low-cost, low-power,

high-performance, ease of use, and I/O ﬂexibility make

the PIC16C64X & PIC16C66X very versatile.

1.1 Family and Upward Compatibility

Those users familiar with the PIC16C5X family of

microcontrollers will realize that this is an enhanced

version of the PIC16C5X architecture. Please refer to

Appendix A for a detailed list of enhancements. Code

written for PIC16C5X can be easily ported to the

PIC16C64X & PIC16C66X (Appendix B).

1.2 Development Support

PIC16C64X & PIC16C66X devices are supported by

the complete line of Microchip Development tools,

including:

• MPLAB Integrated Development Environment

including MPLAB-Simulator.

• MPASM Universal Assembler and MPLAB-C Uni-

versal C compiler.

• PRO MATE II and PICSTART Plus device pro-

grammers.

• PICMASTER In-circuit Emulator System

•

fuzzy

TECH-MP Fuzzy Logic Development Tools

• DriveWay Visual Programming Tool

Please refer to Section 11.0 for more details about

these and other Microchip development tools.

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 6

Preliminary



1996 Microchip Technology Inc.

TABLE 1-1: PIC16C64X & PIC16C66X DEVICE FEATURES

PIC16C641 20 2K 128 TMR0 2 Yes - 4 22 3.0-6.0 Yes 28-pin PDIP, SOIC, Windowed CDIP

PIC16C642 20 4K 176 TMR0 2 Yes - 4 22 3.0-6.0 Yes 28-pin PDIP, SOIC, Windowed CDIP

PIC16C661 20 2K 128 TMR0 2 Yes Yes 5 33 3.0-6.0 Yes 40-pin PDIP, Windowed CDIP;

44-pin PLCC, TQFP

PIC16C662 20 4K 176 TMR0 2 Yes Yes 5 33 3.0-6.0 Yes 40-pin PDIP, Windowed CDIP;

44-pin PLCC, TQFP

All PIC16/17 Family devices have Power-on Reset, selectable W atchdog Timer, selectable code protect, and high I/O current

capability.

All PIC16CXXX Family devices use serial programming with clock pin RB6 and data pin RB7.

Maximum Frequency of Operation (MHz)

EPROM

Data Memory (bytes)

Timer Module(s)

Comparator(s)

Internal Reference Voltage

Interrupt Sources

I/O Pins

Voltage Range (Volts)

Brown-out Reset

Packages

Program Memory

Clock Memory Peripherals Features

Parallel Slave Port



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 7

PIC16C64X & PIC16C66X

2.0 PIC16C64X & PIC16C66X

DEVICE V ARIETIES

A variety of frequency ranges and packaging options

are available. Depending on application and production

requirements the proper device option can be selected

using the information in the Product Identiﬁcation Sys-

tem page at the end of this data sheet. When placing

orders, please use that page of the data sheet to spec-

ify the correct part number.

2.1 UV Erasable Devices

The UV erasable version, offered in CERDIP package

is optimal for prototype development and pilot

programs. This version can be erased and

reprogrammed to any of the oscillator modes.

Microchip's PICSTART



Plus and PRO MATE



programmers both support programming of the

PIC16C64X & PIC16C66X.

2.2 One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers who need ﬂexibility for frequent code

updates and small volume applications. In addition to

the program memory, the conﬁguration bits must also

be programmed.

2.3 Quick-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who choose not to program a

medium to high quantity of units and whose code pat-

terns have stabilized. The devices are identical to the

OTP devices but with all EPROM locations and conﬁg-

uration options already programmed by the factory.

Certain code and prototype veriﬁcation procedures

apply before production shipments are available.

Please contact your Microchip Technology sales ofﬁce

for more details.

2.4 Serialized Quick-Turnaround-

Production (SQTP

) Devices

Microchip offers a unique programming service where

a few user-deﬁned locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password or ID number.

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 8

Preliminary



1996 Microchip Technology Inc.

NOTES:



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 9

PIC16C64X & PIC16C66X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16C64X &

PIC16C66X devices can be attributed to a number of

architectural features commonly found in RISC micro-

processors. To begin with, the PIC16C64X &

PIC16C66X use a Harvard architecture in which pro-

gram and data are accessed from separate memories

using separate buses. This improves bandwidth over

traditional von Neumann architecture where program

and data are fetched from the same memory. Separat-

ing program and data memory further allows instruc-

tions to be sized differently than an 8-bit wide data

word. Instruction opcodes are 14-bits wide making it

possible to have all single word instructions. A 14-bit

wide program memory access bus fetches a 14-bit

instruction in a single cycle. A two-stage pipeline over-

laps fetch and execution of instructions. Consequently,

all instructions (35) execute in a single cycle (200 ns @

20 MHz) except for program branches, which require

two cycles.

The PIC16C641 and PIC16C661 both address 2K x 14

on-chip program memory while the PIC16C642 and

PIC16C662 address 4K x 14. All program memory is

internal.

PIC16C64X & PIC16C66X devices can directly or indi-

rectly address their register ﬁles or data memory. All

special function registers including the program

counter are mapped in the data memory. These

devices have an orthogonal (symmetrical) instruction

set that makes it possible to carry out any operation on

any register using any addressing mode. This symmet-

rical nature and lack of ‘special optimal situations’

make programming with the PIC16C64X & PIC16C66X

simple yet efﬁcient. In addition, the learning curve is

reduced signiﬁcantly.

PIC16C64X & PIC16C66X devices contain an 8-bit

ALU and working register. The ALU is a general pur-

pose arithmetic unit. It performs arithmetic and Bool-

ean functions between data in the working register and

any register ﬁle.

The ALU is 8-bits wide and capable of addition,

subtraction, shift, and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically one operand is the working register

(W register). The other operand is a ﬁle register or an

immediate constant. In single operand instructions, the

operand is either the W register or a ﬁle register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the ST ATUS register . The C and DC bits

operate as a Borrow and Digit Borrow out bit,

respectively, bit in subtraction. See the

SUBLW

and

SUBWF

instructions for examples.

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 10

Preliminary



1996 Microchip Technology Inc.

FIGURE 3-1: PIC16C641/642 BLOCK DIAGRAM

EPROM

Program

Memory

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr 7

RAM Bank 9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up T imer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR VDD, VSS

Voltage

Brown-out

Reset

Timer0

PORTA

Comparator

RA3/AN3

RA2/AN2/VREF

RA1/AN1

RA0/AN0

Reference

RA4/T0CKI

PORTB RB0/INT

Select

RB1

RB2

RB3

RB4

RB5

RB6

RB7

PORTC RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

RA5

Parity Error

Reset

PIC16C641 has 2K x 14 Program Memory and 128 x 8 RAM

PIC16C642 has 4K x 14 Program Memory and 176 x 8 RAM



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 11

PIC16C64X & PIC16C66X

FIGURE 3-2: PIC16C661/662 BLOCK DIAGRAM

EPROM

Program

Memory

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr 7

RAM Bank 9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

Voltage

Timer0

PORTA

Comparator

RA3/AN3

RA2/AN2/VREF

RA1/AN1

RA0/AN0

Reference

RA4/T0CKI

PORTB RB0/INT

Select

RB1

RB2

RB3

RB4

RB5

RB6

RB7

PORTC RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

PORTD RD0/PSP0

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

PORTE

RE0/RD

RE1/WR

RE2/CS

Parallel

Slave

Port

RA5

Power-up

Timer

Oscillator

Start-up T imer

Power-on

Reset

Watchdog

Timer

MCLR VDD, VSS

Brown-out

Reset

Parity Error

Reset

PIC16C661 has 2K x 14 Program Memory and 128 x 8 RAM

PIC16C662 has 4K x 14 Program Memory and 176 x 8 RAM

PIC16C64X & PIC16C66X

DS30559A-page 12

Preliminary



1996 Microchip Technology Inc.

TABLE 3-1: PIC16C641/642 PINOUT DESCRIPTION

Name Pin # I/O/P

Type Buffer

Type Description

OSC1/CLKIN 9 I ST/CMOS Oscillator crystal input or external clock source input.

OSC2/CLKOUT 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal

oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has

1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR/V

1 I/P ST Master clear (reset) input or programming voltage input. This pin is

an active low reset to the device.

PORTA is a bi-directional I/O port.

RA0/AN0 2 I/O ST Analog comparator input.

RA1/AN1 3 I/O ST Analog comparator input.

RA2/AN2/V

REF

4 I/O ST Analog comparator input or V

REF

output.

RA3/AN3 5 I/O ST Analog comparator input or comparator output.

RA4/T0CKI 6 I/O ST Can be selected to be the clock input to the T imer0 timer/counter

or a comparator output. Output is open drain type.

RA5 7 I/O ST PORTB is a bi-directional I/O port. PORTB can be software pro-

grammed for internal weak pull-ups on all inputs.

RB0/INT 21 I/O TTL/ST

(1)

RB0 can also be selected as an external interrupt pin.

RB1 22 I/O TTL

RB2 23 I/O TTL

RB3 24 I/O TTL

RB4 25 I/O TTL Interrupt on change pin.

RB5 26 I/O TTL Interrupt on change pin.

RB6 27 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming clock.

RB7 28 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

RC0 11 I/O ST

RC1 12 I/O ST

RC2 13 I/O ST

RC3 14 I/O ST

RC4 15 I/O ST

RC5 16 I/O ST

RC6 17 I/O ST

RC7 18 I/O ST

8,19 P — Ground reference for logic and I/O pins.

20 P — Positive supply for logic and I/O pins.

Legend: O = output I/O = input/output P = power

I = input — = not used ST = Schmitt Trigger input

TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 13

PIC16C64X & PIC16C66X

TABLE 3-2: PIC16C661/662 PINOUT DESCRIPTION

Name DIP

Pin # QFP

Pin # PLCC

Pin # I/O/P

Type Buffer

Type Description

OSC1/CLKIN 13 30 14 I ST/CMOS Oscillator crystal input or external clock source

input.

OSC2/CLKOUT 14 31 15 O — Oscillator crystal output. Connects to crystal or reso-

nator in crystal oscillator mode. In RC mode, OSC2

pin outputs CLKOUT which has 1/4 the frequency of

OSC1, and denotes the instruction cycle rate.

MCLR/V

1 18 2 I/P ST Master clear (reset) input or programming voltage

input. This pin is an active low reset to the device.

PORTA is a bi-directional I/O port.

RA0/AN0 2 19 3 I/O ST Analog comparator input.

RA1/AN1 3 20 4 I/O ST Analog comparator input.

RA2/AN2/V

REF

4 21 5 I/O ST Analog comparator input or V

REF

output.

RA3/AN3 5 22 6 I/O ST Analog comparator input or comparator output.

RA4/T0CKI 6 23 7 I/O ST Can be selected to be the clock input to the

Timer0 timer/counter or a comparator output.

Output is open drain type.

RA5 7 24 8 I/O ST PORTB is a bi-directional I/O port. PORTB can be

software programmed for internal weak pull-ups on

all inputs.

RB0/INT 33 8 36 I/O TTL/ST

(1)

RB0 can also be selected as an external

interrupt pin.

RB1 34 9 37 I/O TTL

RB2 35 10 38 I/O TTL

RB3 36 11 39 I/O TTL

RB4 37 14 41 I/O TTL Interrupt on change pin.

RB5 38 15 42 I/O TTL Interrupt on change pin.

RB6 39 16 43 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming

clock.

RB7 40 17 44 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming

data.

PORTC is a bi-directional I/O port.

RC0 15 32 16 I/O ST

RC1 16 35 18 I/O ST

RC2 17 36 19 I/O ST

RC3 18 37 20 I/O ST

RC4 23 42 25 I/O ST

RC5 24 43 26 I/O ST

RC6 25 44 27 I/O ST

RC7 26 1 29 I/O ST

Legend: O = output I/O = input/output P = power

I = input — = not used ST = Schmitt Trigger input

TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

3: This buffer is a Schmitt Trigger input when conﬁgured as a general purpose I/O and a TTL input when used

in the Parallel Slave Port Mode (for interfacing to a microprocessor port).

PIC16C64X & PIC16C66X

DS30559A-page 14

Preliminary



1996 Microchip Technology Inc.

PORTD can be a bi-directional I/O port or parallel

slave port for interfacing to a microprocessor bus.

RD0/PSP0 19 38 21 I/O ST/TTL

(3)

RD1/PSP1 20 39 22 I/O ST/TTL

(3)

RD2/PSP2 21 40 23 I/O ST/TTL

(3)

RD3/PSP3 22 41 24 I/O ST/TTL

(3)

RD4/PSP4 27 2 30 I/O ST/TTL

(3)

RD5/PSP5 28 3 31 I/O ST/TTL

(3)

RD6/PSP6 29 4 32 I/O ST/TTL

(3)

RD7/PSP7 30 5 33 I/O ST/TTL

(3)

PORTE is a bi-directional I/O port.

RE0/RD 8 25 9 I/O ST/TTL

(3)

RE0/RD read control for parallel slave port.

RE1/WR 9 26 10 I/O ST/TTL

(3)

RE1/WR write control for parallel slave port.

RE2/CS 10 27 11 I/O ST/TTL

(3)

RE2/CS select control for parallel slave port.

12,31 6,29 13,34 P — Ground reference for logic and I/O pins.

11,32 7,28 12,35 P — Positive supply for logic and I/O pins.

NC — 12,13,

33,34 1,17

28,40 — — Not Connected.

Name DIP

Pin # QFP

Pin # PLCC

Pin # I/O/P

Type Buffer

Type Description

Legend: O = output I/O = input/output P = power

I = input — = not used ST = Schmitt Trigger input

TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

3: This buffer is a Schmitt Trigger input when conﬁgured as a general purpose I/O and a TTL input when used

in the Parallel Slave Port Mode (for interfacing to a microprocessor port).



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 15

PIC16C64X & PIC16C66X

3.1 Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3, and Q4. Internally, the

program counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The

instruction is decoded and executed during the

following Q1 through Q4. The clocks and instruction

execution ﬂow is shown in Figure 3-3.

3.2 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3, and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g.,

GOTO

)

then two cycles are required to complete the instruction

(Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register (IR)” in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-3: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

PIC16C64X & PIC16C66X

DS30559A-page 16

Preliminary



1996 Microchip Technology Inc.

NOTES:



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 17

PIC16C64X & PIC16C66X

4.0 MEMORY ORGANIZATION

4.1 Program Memory Organization

The PIC16C64X & PIC16C66X have a 13-bit program

counter capable of addressing an 8K x 14 program

memory space. For the PIC16C641 and PIC16C661

only the ﬁrst 2K x 14 (0000h - 07FFh) is physically

implemented. For the PIC16C642 and PIC16C662 only

the ﬁrst 4K x 14 (0000h - 0FFh) is physically imple-

mented. Accessing a location above the 2K or 4K

boundary will cause a wrap-around. The reset vector is

at 0000h and the interrupt vector is at 0004h (Figure 4-

1 and Figure 4-2). See Section 4.4 for Program Mem-

ory paging.

FIGURE 4-1: PIC16C641/661 PROGRAM

MEMORY MAP AND STACK

PC<12:0>

0000h

0004h

0005h

07FFh

0800h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

2000h

2007h

3FFFh

TEST

Conﬁguration Word

TEST

User Memory Space

FIGURE 4-2: PIC16C642/662 PROGRAM

MEMORY MAP AND STACK

PC<12:0>

0000h

0004h

0005h

0FFFh

1000h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

2000h

2007h

3FFFh

TEST

Conﬁguration Word

TEST

User Memory Space

Page0

On-chip Program

Memory

Page1

07FFh

0800h

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 18

Preliminary



1996 Microchip Technology Inc.

4.2 Data Memory Organization

The data memory (Figure 4-4) is partitioned into two

banks which contain the general purpose registers and

the special function registers. Bank 0 is selected when

bit RP0 (STATUS<5>) is cleared. Bank 1 is selected

when the RP0 bit is set. The Special Function Regis-

ters are located in the ﬁrst 32 locations of each Bank.

pose registers implemented as static RAM. Some spe-

cial function registers are mapped in Bank 1.

4.2.1 GENERAL PURPOSE REGISTER FILE

The register ﬁle is organized as 176 x 8 for the

PIC16C642/662, and 128 x8 for the PIC16C641/661.

Each is accessed either directly, or indirectly through

the File Select Register FSR (Section 4.5).

FIGURE 4-3: PIC16C641/661 DATA

MEMORY MAP

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PORTC

PIR1

CMCON

INDF(1)

OPTION

PCL

STATUS

FSR

TRISA

TRISB

TRISC

PIE1

PCON

VRCON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

General

Purpose

General

Purpose

7Fh FFh

Bank 0 Bank 1

File

Address

BFh

C0h

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

2: Not implemented on the PIC16C641.

File

Address

PORTD(2) TRISD(2)

TRISE(2)

PCLATH

INTCON

PORTE(2)

PCLATH

INTCON

Mapped

in Page 0

EFh

F0h



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 19

PIC16C64X & PIC16C66X

FIGURE 4-4: PIC16C642/662 DATA

MEMORY MAP

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

PIR1

CMCON

INDF(1)

OPTION

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

PIE1

PCON

VRCON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

General

Purpose

7Fh FFh

Bank 0 Bank 1

File

Address

Unimplemented data memory loca-

tions, read as '0'.

Note 1: Not a physical register.

2: Not implemented on the PIC16C642.

File

Address

PORTC TRISC

PORTD(2) TRISD(2)

PORTE(2) TRISE(2)

General

Purpose

Mapped

in Bank 0

EFh

F0h

4.2.2 SPECIAL FUNCTION REGISTERS

The special function registers are registers used by the

CPU and Peripheral Modules for controlling the desired

operation of the device (Table 4-1). These registers are

static RAM.

The special function registers can be classiﬁed into two

sets (core and peripheral). The special function regis-

ters associated with the “core” functions are described

in this section. Those related to the operation of the

peripheral features are described in the section of that

peripheral feature.

PIC16C64X & PIC16C66X

DS30559A-page 20

Preliminary



1996 Microchip Technology Inc.

TABLE 4-1: SPECIAL FUNCTION REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR,

PER

Value on

all other

resets

(1)

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx xxxx xxxx

01h TMR0 Timer0 Module’s Register

xxxx xxxx uuuu uuuu

02h PCL Program Counter's (PC) Least Signiﬁcant Byte

0000 0000 0000 0000

03h STATUS IRP

(2)

RP1

(2)

RP0 TO PD ZDCC

0001 1xxx 000q quuu

04h FSR Indirect data memory address pointer

xxxx xxxx uuuu uuuu

05h PORTA — — PORTA Data Latch when written: PORTA pins when read

--xx 0000 --xu 0000

06h PORTB PORTB Data Latch when written: PORTB pins when read

xxxx xxxx uuuu uuuu

06h PORTC PORTC Data Latch when written: PORTC pins when read

xxxx xxxx uuuu uuuu

06h PORTD

(3)

PORTD Data Latch when written: PORTD pins when read

xxxx xxxx uuuu uuuu

06h PORTE

(3)

—— — — — RE2 RE1 RE0

---- -xxx ---- -uuu

0Ah PCLATH — — — Write buffer for upper 5 bits of program counter

---0 0000 ---0 0000

0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch PIR1 PSPIF

(4)

CMIF — — — — — —

00-- ---- 00-- ----

0Dh-1Eh Unimplemented

——

1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0

00-- 0000 00-- 0000

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx xxxx xxxx

81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

1111 1111 1111 1111

82h PCL Program Counter's (PC) Least Signiﬁcant Byte

0000 0000 0000 0000

83h STATUS IRP

(2)

RP1

(2)

RP0 TO PD ZDCC

0001 1xxx 000q quuu

84h FSR Indirect data memory address pointer

xxxx xxxx uuuu uuuu

85h TRISA — — PORTA Data Direction Register

--11 1111 --11 1111

86h TRISB PORTB Data Direction Register

1111 1111 1111 1111

86h TRISC PORTC Data Direction Register

1111 1111 1111 1111

86h TRISD

(3)

PORTD Data Direction Register

1111 1111 1111 1111

86h TRISE

(3)

IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0

0000 -111 0000 -111

8Ah PCLATH — — — Write buffer for upper 5 bits of program counter

---0 0000 ---0 0000

8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000x

8Ch PIE1 PSPIE

(4)

CMIE — — — — — —

00-- ---- 00-- ----

8Dh Unimplemented

——

8Eh PCON MPEEN — — — — PER POR BOR

u--- -qqq u--- -uuu

8Fh-9Eh Unimplemented

——

9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0

000- 0000 000- 0000

Legend:

= unimplemented locations read as ‘0’,

= unchanged,

= unknown,

= value depends on condition, shaded = unimplemented

Note 1: Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation.

2: The IRP and RP1 bits are reserved, always maintain these bits clear.

3: The PORTD, PORTE, TRISD, and TRISE registers are not implemented on the PIC16C641/642.

4: Bits PSPIE and PSPIF are reserved on the PIC16C641/642, always maintain these bits clear.



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 21

PIC16C64X & PIC16C66X

4.2.2.1 STATUS REGISTER

The STATUS register, shown in Figure 4-5, contains

the arithmetic status of the ALU, the RESET status, and

the bank select bits for data memory.

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example,

CLRF STATUS

will clear the upper-three

bits and set the Z bit. This leaves the STATUS register

000uu1uu

(where

= unchanged).

It is recommended, therefore, that only

BCF, BSF,

SWAPF,

and

MOVWF

instructions are used to alter the

STATUS register because these instructions do not

affect any status bit. For other instructions, not affecting

any status bits, see the “Instruction Set Summary.”

Note 1:

The IRP and RP1 bits (STATUS<7:6>) are

reserved on the PIC16C64X &

PIC16C66X and should be maintained

clear. Use of these bits as general pur-

pose R/W bits is NOT recommended,

since this may affect upward compatibility

with future products.

Note 2:

The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the

SUBLW

and

SUBWF

instructions for examples.

FIGURE 4-5: STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7:

IRP:

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

Bit IRP is reserved on the PIC16C64X & PIC16C66X, always maintain this bit clear.

bit 6-5:

RP1:RP0

: Register Bank Select bits (used for direct addressing)

= Bank 3 (180h - 1FFh)

= Bank 2 (100h - 17Fh)

= Bank 1 (80h - FFh)

= Bank 0 (00h - 7Fh)

Each bank is 128 bytes. Bit RP1 is reserved on the PIC16C64X & PIC16C66X, always maintain this bit

clear.

bit 4:

: T ime-out bit

1 = After power-up,

CLRWDT

instruction, or

SLEEP

instruction

0 = A WDT time-out occurred

bit 3:

: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most signiﬁcant bit of the result occurred

0 = No carry-out from the most signiﬁcant bit of the result occurred

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of

the source register.

PIC16C64X & PIC16C66X

DS30559A-page 22 Preliminary  1996 Microchip Technology Inc.

4.2.2.2 OPTION REGISTER

The OPTION register is a readable and writable

the TMR0/WDT prescaler, the external RB0/INT

interrupt, TMR0, and the weak pull-ups on PORTB.

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT.

FIGURE 4-6: OPTION REGISTER (ADDRESS 81h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R= Readable bit

W= Writable bit

U= Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7 bit0

bit 7: RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6: INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

 1996 Microchip Technology Inc. Preliminary DS30559A-page 23

PIC16C64X & PIC16C66X

4.2.2.3 INTCON REGISTER

The INTCON register is a readable and writable

for all non-peripheral interrupt sources.

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

FIGURE 4-7: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R= Readable bit

W= Writable bit

U= Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

bit 6: PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4: INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

bit 3: RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2: T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register overﬂowed (must be cleared in software)

0 = TMR0 register did not overﬂow

bit 1: INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

1 = When at least one of the RB7:RB4 pins changed state (See Section 5.2 to clear interrupt)

0 = None of the RB7:RB4 pins have changed state

PIC16C64X & PIC16C66X

DS30559A-page 24 Preliminary  1996 Microchip Technology Inc.

4.2.2.4 PIE1 REGISTER

This register contains the individual enable bits for the

comparator and Parallel Slave Port interrupts.

FIGURE 4-8: PIE1 REGISTER (ADDRESS 8Ch)

R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

PSPIE(1) CMIE — — — — — — R= Readable bit

W= Writable bit

U= Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7 bit0

bit 7: PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write interrupt

bit 6: CMIE: Comparator Interrupt Enable bit

1 = Enables the Comparator interrupt

0 = Disables the Comparator interrupt

bit 5-0: Unimplemented: Read as '0'

Note 1: Bit PSPIE is reserved on the PIC16C641/642, always maintain this bit clear.

 1996 Microchip Technology Inc. Preliminary DS30559A-page 25

PIC16C64X & PIC16C66X

4.2.2.5 PIR1 REGISTER

This register contains the individual ﬂag bits for the

comparator and Parallel Slave Port interrupts.

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt ﬂag bits are clear prior to enabling

an interrupt.

FIGURE 4-9: PIR1 REGISTER (ADDRESS 0Ch)

R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

PSPIF(1) CMIF — — — — — — R= Readable bit

W= Writable bit

U= Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7 bit0

bit 7: PSPIF(1): Parallel Slave Port Interrupt Flag bit

1 = A read or write operation has taken place (must be cleared in software)

0 = No read or write operation has taken place

bit 6: CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software)

0 = Comparator input has not changed

bit 5-0: Unimplemented: Read as '0'

Note 1: Bit PSPIF is reserved on the PIC16C641/642, always maintain this bit clear.

PIC16C64X & PIC16C66X

DS30559A-page 26 Preliminary  1996 Microchip Technology Inc.

4.2.2.6 PCON REGISTER

The PCON register contains ﬂag bits to differentiate

between a Power-on Reset (POR), an external MCLR

reset, WDT reset, Brown-out Reset (BOR), and Parity

Error Reset (PER). The PCON register also contains a

status bit, MPEEN, which reﬂects the value of the

MPEEN bit in Conﬁguration Word. See Table 9-4 for

status of these bits on various resets.

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked

on subsequent resets to see if BOR is

cleared, indicating a brown-out has

occurred. The BOR status bit is a “don't

care” and is not necessarily predictable if

the brown-out circuit is disabled (by

programming the BODEN bit in the

Conﬁguration word).

FIGURE 4-10: PCON REGISTER (ADDRESS 8Eh)

R-U U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-u

MPEEN ————PER POR BOR R= Readable bit

W= Writable bit

U= Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7 bit0

bit 7: MPEEN: Memory Parity Error Circuitry Status bit

Reﬂects the value of Conﬁguration Word bit, MPEEN

bit 6-3: Unimplemented: Read as '0'

bit 2: PER: Memory Parity Error Reset Status bit

1 = No error occurred

0 = Program memory fetch parity error occurred

(must be set in software after a Parity Error Reset occurs)

bit 1: POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

 1996 Microchip Technology Inc. Preliminary DS30559A-page 27

PIC16C64X & PIC16C66X

4.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte

comes from the PCL register, which is readable and

writable. The high byte (PC<12:8>) is not directly read-

able or writable and comes from PCLATH. On any

reset, the PC is cleared. Figure 4-11 shows the two

situations for the loading of the PC. The upper example

in the ﬁgure shows how the PC is loaded on a write to

PCL (PCLATH<4:0> → PCH). The lower example in

the ﬁgure shows how the PC is loaded during a CALL

or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 4-11: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an

offset to the program counter (ADDWF PCL). When

doing a table read using a computed GOTO method,

care should be exercised if the table location crosses a

PCL memory boundary (each 256 byte block). Refer to

the application note

“Implementing a Table Read”

(AN556).

PC 12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU result

GOTO, CALL

Opcode <10:0>

PC 12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

4.3.2 STACK

PIC16C64X & PIC16C66X devices have an 8 level

deep x 13-bit wide hardware stack (Figure 4-2). The

stack space is not part of either program or data space

and the stack pointer is not readable or writable. The

PC is PUSHed onto the stack when a CALL instruction

is executed or an interrupt causes a branch. The stack

is POPed in the event of a RETURN, RETLW or a RETFIE

instruction execution. PCLATH is not affected by a

PUSH or POP operation.

The stack operates as a circular buffer . This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the ﬁrst

push. The tenth push overwrites the second push (and

so on).

4.4 Program Memory Paging

PIC16C642 and PIC16C662 devices have 4K of pro-

gram memory, but the CALL and GOTO instructions only

have an 11-bit address range. This 11-bit address

range allows a branch within a 2K program memory

page size. To allow CALL and GOTO instructions to

address the entire 4K program memory address range,

there must be another bit to specify the program mem-

ory page. This paging bit comes from the PCLATH<3>

bit (Figure 4-11). When doing a CALL or GOTO instruc-

tion, the user must ensure that this page select bit

(PCLATH<3>) is programmed so that the desired pro-

gram memory page is addressed. If a return from a

CALL instruction (or interrupt) is executed, the entire

13-bit PC is pushed onto the stack. Therefore, manipu-

lation of the PCLATH<3> bit is not required for the

return instructions (which POPs the address from the

stack).

Note 1: There are no status bits to indicate stack

overﬂow or stack underﬂow conditions.

Note 2: There are no instructions mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL,

RETURN, RETLW, and RETFIE instruc-

tions, or the vectoring to an interrupt

address.

Note: The PIC16C64X & PIC16C66X ignore the

PCLATH<4> bit, which is used for program

memory pages 2 and 3 (1000h - 1FFFh).

The use of PCLATH<4> as a general pur-

pose read/write bit is not recommended

since this may affect upward compatibility

with future products.

PIC16C64X & PIC16C66X

DS30559A-page 28 Preliminary  1996 Microchip Technology Inc.

4.5 Indirect Addressing, INDF, and FSR

Registers

The INDF register is not a physical register . Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF reg-

ister. Any instruction using the INDF register actually

accesses data pointed to by the ﬁle select register

(FSR). Reading INDF itself indirectly will produce 00h.

Writing to the INDF register indirectly results in a no-

operation (although status bits may be affected). An

effective 9-bit address is obtained by concatenating the

8-bit FSR register and the IRP bit (STATUS<7>), as

shown in Figure 4-12. However, bit IRP is not used in

the PIC16C64X & PIC16C66X.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer

movwf FSR ;to RAM

NEXT clrf INDF ;clear INDF register

incf FSR ;inc pointer

btfss FSR,4 ;all done?

goto NEXT ;no goto next

;yes continue

CONTINUE:

FIGURE 4-12: DIRECT/INDIRECT ADDRESSING

For memory map detail see Figure 4-3 and Figure 4-4.

Note 1: Bits RP1 and IRP are reserved, always maintain these bits clear.

Data

Memory

Indirect AddressingDirect Addressing

bank select location select

(1)RP1 RP0 6 0

from opcode IRP(1) FSR register

bank select location select

00 01 10 11 00h

7Fh

00h

7Fh Bank 0 Bank 1 Bank 2 Bank 3

not used



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 29

PIC16C64X & PIC16C66X

5.0 I/O PORTS

The PIC16C641 and PIC16C642 have three ports,

PORTA, PORTB, and PORTC. PIC16C661 and

PIC16C662 devices have ﬁve ports, PORTA through

PORTE. Some pins for these I/O ports are multiplexed

with alternate functions for the peripheral features on

the device. In general, when a peripheral is enabled,

that pin may not be used as a general purpose I/O pin.

5.1 PORTA and TRISA Registers

PORTA is a 6-bit wide latch. RA4 is a Schmitt Trigger

input and an open drain output. Pin RA4 is multiplexed

with the T0CKI clock input. All other RA port pins have

Schmitt Trigger input levels and full CMOS output driv-

ers. All pins have data direction bits (TRIS registers)

which can conﬁgure these pins as input or output.

Setting a bit in the TRISA register puts the correspond-

ing output driver in a hi-impedance mode. Clearing a bit

in the TRISA register puts the contents of the output

latch on the selected pin.

Reading the PORTA register reads the status of the

pins, whereas writing to it will write to the port latch. All

write operations are read-modify-write operations.

Therefore, a write to a port implies that the port pins are

read, this value is modiﬁed, and then written to the port

data latch.

The PORTA pins are multiplexed with comparator and

voltage reference functions. The operation of these

pins are selected by control bits in the CMCON

(comparator control register) register and the VRCON

(voltage reference control) register. When selected as

comparator inputs, these pins will read as '0's.

FIGURE 5-1: BLOCK DIAGRAM OF

RA1:RA0 PINS

TRISA controls the direction of the RA pins, even when

they are being used as comparator inputs. The user

must make sure to keep the pins conﬁgured as inputs

when using them as comparator inputs.

The RA2 pin will also function as the output for the

voltage reference. When in this mode, the V

REF

pin is

a very hi-impedance output. The user must set the

TRISA<2> bit and use hi-impedance loads.

In one of the comparator modes deﬁned by the

CMCON register, pins RA3 and RA4 become outputs

of the comparators. The TRISA<4:3> bits must be

cleared to enable outputs to use this function.

EXAMPLE 5-1: INITIALIZING PORTA

CLRF PORTA ;Initialize PORTA by

;clearing output latches

MOVLW 0x07 ;Turn comparators off,

MOVWF CMCON ;enable pins for I/O

BSF STATUS, RP0 ;Select bank1

MOVLW 0x1F ;Value to initialize

;data direction

MOVWF TRISA ;Set RA<4:0> as inputs

;TRISA<7:5> are clear

Note:

On reset, the TRISA register is set to all

inputs. The digital inputs are disabled and

the comparator inputs are forced to ground

to reduce excess current consumption.

Note: I/O pins have protection diodes to VDD and VSS.

Data

bus QD

CK P

Port

TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

Analog VSS

VDD

I/O Pin

Input Mode

To Comparator

Schmitt T rigger

Input Buffer

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 30

Preliminary



1996 Microchip Technology Inc.

FIGURE 5-2: BLOCK DIAGRAM OF RA2 PIN

Note: I/O pin has protection diodes to VDD and VSS.

Data

bus QD

CK P

Port

TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

Analog VSS

VDD

RA2 Pin

Input Mode

To Comparator

Schmitt T rigger

Input Buffer

VROE

VREF

FIGURE 5-3: BLOCK DIAGRAM OF RA3 PIN

Data

bus QD

CK P

Port

TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

Analog VSS

VDD

RA3 Pin

To Comparator

Schmitt T rigger

Input Buffer

Input Mode

Comparator Output

Comparator Mode = 110



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 31

PIC16C64X & PIC16C66X

FIGURE 5-4: BLOCK DIAGRAM OF RA4 PIN

TABLE 5-1: PORTA FUNCTIONS

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit # Buffer

Type Function

RA0/AN0 bit0 ST Input/output or comparator input.

RA1/AN1 bit1 ST Input/output or comparator input.

RA2/AN2/V

REF

bit2 ST Input/output or comparator input or V

REF

output.

RA3/AN3 bit3 ST Input/output or comparator input/output.

RA4/T0CKI bit4 ST Input/output or external clock input for TMR0 or comparator output. Out-

put is open drain type.

RA5 bit5 ST Input/output.

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

resets

05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0

--xx 0000 --uu 0000

85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

--11 1111 --11 1111

1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0

00-- 0000 00-- 0000

9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0

000- 0000 000- 0000

Legend:

= unknown,

= unchanged,

= unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Data

bus QD

Port

TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

VSS

RA4 Pin

TMR0 Clock Input

Schmitt T rigger

Input Buffer

Comparator Output

Comparator Mode = 110

PIC16C64X & PIC16C66X

DS30559A-page 32

Preliminary



1996 Microchip Technology Inc.

5.2 PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The

corresponding data direction register is TRISB. Setting

a bit in the TRISB register puts the corresponding out-

put driver in a hi-impedance mode. Clearing a bit in the

TRISB register puts the contents of the output latch on

the selected pin(s).

Reading PORTB register reads the status of the pins,

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. There-

fore, a write to a port implies that the port pins are read,

this value is modiﬁed, and then written to the port data

latch.

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

done by clearing the RBPU (OPTION<7>) bit. The

weak pull-up is automatically turned off when the port

pin is conﬁgured as an output. The pull-ups are dis-

abled on a Power-on Reset.

Four of PORTB’s pins, RB7:RB4, have an interrupt on

change feature. Only pins conﬁgured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

conﬁgured as an output is excluded from the interrupt

on change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’ed together to generate the RBIF interrupt (ﬂag

latched in (INTCON<0>)).

FIGURE 5-5: BLOCK DIAGRAM OF

RB7:RB4 PINS

Data Latch

From other

RBPU(2) P

VDD

I/O

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak

pull-up

RD Port

Latch

TTL

Input

Buffer

pin(1)

Note 1: I/O pins have diode protection to VDD and VSS.

2: TRISB = '1' enables weak pull-up if RBPU = '0'

(OPTION<7>).

Buffer

RB7:RB6 in serial programming mode

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the

interrupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear ﬂag bit RBIF.

A mismatch condition will continue to set ﬂag bit RBIF.

Reading PORTB will end the mismatch condition, and

allow ﬂag bit RBIF to be cleared.

This interrupt on mismatch feature, together with

software conﬁgurable pull-ups on these four pins allow

easy interface to a keypad and make it possible for

wake-up on key-depression. (See AN552 in the

Microchip

Embedded Control Handbook

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

FIGURE 5-6: BLOCK DIAGRAM OF

RB3:RB0 PINS

Data Latch

RBPU(2) P

VDD

Data bus

WR Port

WR TRIS

RD TRIS

RD Port

weak

pull-up

RD Port

RB0/INT

I/O

pin(1)

TTL

Input

Buffer

Note 1: I/O pins have diode protection to VDD and VSS.

2: TRISB = '1' enables weak pull-up if RBPU = '0'

(OPTION<7>).

Buffer



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 33

PIC16C64X & PIC16C66X

EXAMPLE 5-2: INITIALIZING PORTB

CLRF PORTB ; Initialize PORTB by

; clearing output

; data latches

BSF STATUS, RP0 ; Select Bank 1

MOVLW 0xCF ; Value used to

; initialize data

; direction

MOVWF TRISB ; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

TABLE 5-3: PORTB FUNCTIONS

TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit # Buffer Type Function

RB0/INT bit0 TTL/ST

(1)

Input/output or external interrupt input. Internal software programmable

weak pull-up.

RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.

RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.

RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.

RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable

weak pull-up.

RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable

weak pull-up.

RB6 bit6 TTL/ST

(2)

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming clock pin.

RB7 bit7 TTL/ST

(2)

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming data pin.

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

resets

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

xxxx xxxx uuuu uuuu

86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

1111 1111 1111 1111

81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

1111 1111 1111 1111

Legend:

= unknown,

= unchanged, shaded cells are not used by PORTB.

PIC16C64X & PIC16C66X

DS30559A-page 34

Preliminary



1996 Microchip Technology Inc.

5.3 PORTC and TRISC Registers

PORTC is an 8-bit bi-directional port. Each pin is indi-

vidually conﬁgurable as an input or output through the

TRISC register. PORTC pins have Schmitt Trigger

input buffers.

EXAMPLE 5-3: INITIALIZING PORTC

CLRF PORTC ; Initialize PORTC by

; clearing output

; data latches

BSF STATUS, RP0 ; Select Bank 1

MOVLW 0xCF ; Value used to

; initialize data

; direction

MOVWF TRISC ; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

FIGURE 5-7: PORTC BLOCK DIAGRAM (IN

I/O PORT MODE)

Data

bus

PORT

TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

input

buffer

I/O pin(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

TABLE 5-5: PORTC FUNCTIONS

TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name Bit# Buffer Type Function

RC0 bit0 ST Input/output

RC1 bit1 ST Input/output

RC2 bit2 ST Input/output

RC3 bit3 ST Input/output

RC4 bit4 ST Input/output

RC5 bit5 ST Input/output

RC6 bit6 ST Input/output

RC7 bit7 ST Input/output

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on all

other resets

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0

xxxx xxxx uuuu uuuu

87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

1111 1111 1111 1111

Legend:

= unknown,

= unchanged.



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 35

PIC16C64X & PIC16C66X

5.4 PORTD and TRISD Registers

(PIC16C661 and PIC16C662 only)

PORTD is an 8-bit port with Schmitt Trigger input buff-

ers. Each pin is individually conﬁgurable as an input or

output.

PORTD can be conﬁgured as an 8-bit wide micropro-

cessor port (parallel slave port) by setting control bit

PSPMODE (TRISE<4>). In this mode, the input buffers

are TTL.

FIGURE 5-8: PORTD BLOCK DIAGRAM (IN

I/O PORT MODE)

Data

bus

PORT

TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

input

buffer

I/O pin(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

TABLE 5-7: PORTD FUNCTIONS

TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Name Bit# Buffer Type Function

RD0/PSP0 bit0 ST/TTL

(1)

Input/output port pin or parallel slave port bit0

RD1/PSP1 bit1 ST/TTL

(1)

Input/output port pin or parallel slave port bit1

RD2/PSP2 bit2 ST/TTL

(1)

Input/output port pin or parallel slave port bit2

RD3/PSP3 bit3 ST/TTL

(1)

Input/output port pin or parallel slave port bit3

RD4/PSP4 bit4 ST/TTL

(1)

Input/output port pin or parallel slave port bit4

RD5/PSP5 bit5 ST/TTL

(1)

Input/output port pin or parallel slave port bit5

RD6/PSP6 bit6 ST/TTL

(1)

Input/output port pin or parallel slave port bit6

RD7/PSP7 bit7 ST/TTL

(1)

Input/output port pin or parallel slave port bit7

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on all

other resets

08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

xxxx xxxx uuuu uuuu

88h TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0

1111 1111 1111 1111

89h TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0

0000 -111 0000 -111

Legend:

= unknown,

= unchanged,

= unimplemented read as '0'. Shaded cells are not used by PORTD.

PIC16C64X & PIC16C66X

DS30559A-page 36 Preliminary  1996 Microchip Technology Inc.

5.5 PORTE and TRISE Register

(PIC16C661 and PIC16C662 only)

PORTE has three pins RE0/RD, RE1/WR, and RE2/

CS, which are individually conﬁgurable as inputs or

outputs. These pins have Schmitt T rigger input buf fers.

I/O PORTE becomes control inputs for the micropro-

cessor port when bit PSPMODE (TRISE<4>) is set. In

this mode, the user must make sure that the

TRISE<2:0> bits are set (pins are conﬁgured as digital

inputs). In this mode the input buffers are TTL.

Figure 5-9 shows the TRISE register, which also con-

trols the parallel slave port operation.

FIGURE 5-9: TRISE REGISTER (ADDRESS 89h)

R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1

IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: IBF: Input Buffer Full Status bit

1 = A word has been received and waiting to be read by the CPU

0 = No word has been received

bit 6: OBF: Output Buffer Full Status bit

1 = The output buffer still holds a previously written word

0 = The output buffer has been read

bit 5: IBOV: Input Buffer Overﬂow Detect bit (in microprocessor mode)

1 = A write occurred when a previously input word has not been read (must be cleared in software)

0 = No overﬂow occurred

bit 4: PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel slave port mode

0 = General purpose I/O mode

bit 3: Unimplemented: Read as '0'

bit 2: TRISE2: Direction control bit for pin RE2/CS

1 = Input

0 = Output

bit 1: TRISE1: Direction control bit for pin RE1/WR

1 = Input

0 = Output

bit 0: TRISE0: Direction control bit for pin RE0/RD

1 = Input

0 = Output

 1996 Microchip Technology Inc. Preliminary DS30559A-page 37

PIC16C64X & PIC16C66X

FIGURE 5-10: PORTE BLOCK DIAGRAM (IN I/O PORT MODE)

TABLE 5-9: PORTE FUNCTIONS

TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name Bit# Buffer Type Function

RE0/RD bit0 ST/TTL(1) Input/output port pin or read control input in parallel slave port mode:

1 = Not a read operation

0 = Read operation. Reads PORTD register (if chip selected)

RE1/WR bit1 ST/TTL(1) Input/output port pin or write control input in parallel slave port mode:

1 = Not a write operation

0 = Write operation. Writes PORTD register (if chip selected)

RE2/CS bit2 ST/TTL(1) Input/output port pin or chip select control input in parallel slave port

mode:CS

1 = Device is not selected

0 = Device is selected

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on all

other resets

09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

89h TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 0000 -111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.

Data Bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

Schmitt

Trigger

input

buffer

I/O pin

RD TRIS

Note: I/O pins have protection diodes to VDD and VSS.

PIC16C64X & PIC16C66X

DS30559A-page 38 Preliminary  1996 Microchip Technology Inc.

5.6 I/O Programming Considerations

5.6.1 BI-DIRECTIONAL I/O PORTS

Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF

instructions, for example, read the register into the

CPU, execute the bit operation and write the result

back to the register. Caution must be used when these

instructions are applied to a port with both inputs and

outputs deﬁned. For example, a BSF operation on bit5

of PORTB will cause all eight bits of POR TB to be read

into the CPU. Then the BSF operation takes place on

bit5 and PORTB is written to the output latches. If

another bit of PORTB is used as a bi-directional I/O pin

(e.g., bit0) and it is deﬁned as an input at this time, the

input signal present on the pin itself would be read into

the CPU and rewritten to the data latch of this particular

pin, overwriting the previous content. As long as the pin

stays in the input mode, no problem occurs. However,

if bit0 is switched into output mode later on, the content

of the data latch may now be unknown.

Reading the port register reads the values of the port

pins. Writing to the port register writes the value to the

port latch. When using read-modify-write instructions

(e.g., BCF, BSF, etc.) on a port, the value of the port

pins is read, the desired operation is done to this value,

and this value is then written to the port latch.

Example 5-4 shows the effect of two sequential

read-modify-write instructions on an I/O port.

A pin actively outputting a Low or High should not be

driven from external devices at the same time in order

to change the level on this pin (“wired-or”, “wired-and”).

The resulting high output currents may damage

the chip.

EXAMPLE 5-4: READ-MODIFY-WRITE

INSTRUCTIONS ON AN I/O

PORT

;Initial PORT settings: PORTB<7:4> Inputs

; PORTB<3:0> Outputs

;PORTB<7:6> have external pull-ups and are

;not connected to other circuitry

;

; PORT latch PORT pins

; ---------- ---------

BCF PORTB, 7 ; 01pp pppp 11pp pppp

BCF PORTB, 6 ; 10pp pppp 11pp pppp

BCF STATUS, RP1 ;

BSF STATUS, RP0 ;

BCF TRISB, 7 ; 10pp pppp 11pp pppp

BCF TRISB, 6 ; 10pp pppp 10pp pppp

;

;Note that the user may have expected the

;pin values to be 00pp ppp. The 2nd BCF

;caused RB7 to be latched as the pin value

;(high).

5.6.2 SUCCESSIVE OPERATIONS ON I/O

PORTS

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle

(Figure 5-11). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should be

such to allow the pin voltage to stabilize (load

dependent) before the next instruction which causes

that ﬁle to be read into the CPU is executed. Otherwise,

the previous state of that pin may be read into the CPU

rather than the new state. When in doubt, it is better to

separate these instructions with an NOP or another

instruction not accessing this I/O port.

FIGURE 5-11: SUCCESSIVE I/O OPERATION

PC PC + 1 PC + 2 PC + 3

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

fetched

RB7:RB0

MOVWF PORTB

write to

PORTB NOP

Port pin

sampled here

NOP

MOVF PORTB,W

Instruction

executed MOVWF PORTB

write to

PORTB

NOP

MOVF PORTB,W

TPD

Note:

This example shows a write to PORTB

followed by a read from PORTB.

Note that:

data setup time = (0.25TCY - TPD)

where TCY = instruction cycle

TPD = propagation delay

Therefore, at higher clock frequencies,

a write followed by a read may be

problematic.

 1996 Microchip Technology Inc. Preliminary DS30559A-page 39

PIC16C64X & PIC16C66X

5.7 Parallel Slave Port

(PIC16C661 and PIC16C662 only)

PORTD operates as an 8-bit wide parallel slave port, or

as a microprocessor port when control bit PSPMODE

(TRISE<4>) is set. In slave mode it is asynchronously

readable and writable by the external world through

RD control input pin (RE0/RD) and WR control input pin

(RE1/WR).

It can directly interface to an 8-bit microprocessor data

bus. The external microprocessor can read or write the

PORTD latch as an 8-bit latch. Setting PSPMODE

enables port pin RE0/RD to be the RD input, RE1/WR

to be the WR input and RE2/CS to be the CS (chip

select) input. For this functionality, the corresponding

data direction bits of the TRISE register (TRISE<2:0>)

must be conﬁgured as inputs (set).

There are actually two 8-bit latches, one for data-out

(from the PIC16/17) and one for data input. The user

writes 8-bit data to PORTD data latch and reads data

from the port pin latch (note that they have the same

address). In this mode, the TRISD register is ignored

since the microprocessor is controlling the direction of

data ﬂow.

Input Buffer Full Status Flag bit IBF (TRISE<7>) is set

if a received word is waiting to be read by the CPU.

Once the PORTD input latch is read, bit IBF is cleared.

IBF is a read only status bit. Output Buffer Full Status

Flag bit OBF (TRISE<6>) is set if a word written to

PORTD latch is waiting to be read by the external bus.

Once the PORTD output latch is read by the micropro-

cessor , bit OBF is cleared. Input Buffer Overﬂow Status

ﬂag bit IBOV (TRISE<5>) is set if a second write to the

microprocessor port is attempted when the previous

word has not been read by the CPU (the ﬁrst word is

retained in the buffer).

When not in Parallel Slave Port mode, bits IBF and

OBF are held clear. However, if ﬂag bit IBOV was pre-

viously set, it must be cleared in software.

An interrupt is generated and latched into ﬂag bit

PSPIF (PIR1<7>) when a read or a write operation is

completed. Flag bit PSPIF must be cleared by user

software. The interrupt can be disabled by clearing the

interrupt enable bit PSPIE (PIE1<7>).

FIGURE 5-12: PORTD AND PORTE AS A

PARALLEL SLAVE PORT

Data bus

PORT

RDx

PORT

One bit of PORTD

Set interrupt ﬂag

PSPIF (PIR1<7>)

Read

Chip Select

Write

Note: I/O pins have protection diodes to VDD and VSS.

TTL

TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on all

other resets

08h PORTD PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0 xxxx xxxx uuuu uuuu

09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

89h TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 0000 -111

0Ch PIR1 PSPIF(1) CMIF — — — — — — 00-- ---- 00-- ----

8Ch PIE1 PSPIE(1) CMIE — — — — — — 00-- ---- 00-- ----

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by the PSP.

Note 1: These bits are reserved on the PIC16C641/642, always maintain these bits clear.

PIC16C64X & PIC16C66X

DS30559A-page 40 Preliminary  1996 Microchip Technology Inc.

NOTES:



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 41

PIC16C64X & PIC16C66X

6.0 TIMER0 MODULE

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Read and write capability

- Interrupt on overﬂow from FFh to 00h

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 6-1 is a simpliﬁed block diagram of the Timer0

module.

Timer mode is selected by clearing bit T0CS

(OPTION<5>). In timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two instruction cycles (Figure 6-2 and

Figure 6-3). The user can work around this by writing

an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS. In this

mode, Timer0 will increment either on every rising or

falling edge of pin RA4/T0CKI. The incrementing edge

is determined by the source edge select bit T0SE

(OPTION<4>). Clearing bit T0SE selects the rising

edge. Restrictions on the external clock input are dis-

cussed in detail in Section 6.2.

The prescaler is mutually exclusively shared between

the Timer0 module and the Watchdog T imer. The pres-

caler assignment is controlled in software by control bit

PSA (OPTION<3>). Clearing bit PSA will assign the

prescaler to the Timer0 module. The prescaler is not

readable or writable. When the prescaler is assigned to

the Timer0 module, prescale values of 1:2, 1:4, …,

1:256 are selectable. Section 6.3 details the operation

of the prescaler.

6.1 Timer0 Interrupt

The TMR0 interrupt is generated when the register

(TMR0) overﬂows from FFh to 00h. This overﬂow sets

interrupt ﬂag bit T0IF (INTCON<2>). The interrupt can

be masked by clearing enable bit T0IE (INTCON<5>).

Flag bit T0IF must be cleared in software by the T imer0

interrupt service routine before re-enabling this inter-

rupt. The TMR0 interrupt cannot wake the processor

from SLEEP since the timer is shut off during SLEEP.

Figure 6-4 displays the Timer0 interrupt timing.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER

Note 1: Bits, T0CS, T0SE, PSA, and PS2, PS1, PS0 are (OPTION<5:0).

2: The prescaler is shared with Watchdog Timer (refer to Figure 6-6 for detailed diagram).

RA4/T0CKI

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

clocks TMR0 reg

PSout

(2 cycle delay)

PSout

Data bus

Set bit T0IF

on overﬂow

PSA

PS2, PS1, PS0

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1 Read TMR0

reads NT0 + 2

Instruction

Executed

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 42

Preliminary



1996 Microchip Technology Inc.

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

FIGURE 6-4: TIMER0 INTERRUPT TIMING

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1

T0+1 NT0

Instruction

Execute

Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT(3)

Timer0

T0IF bit

(INTCON<2>)

FEh

GIE bit

(INTCON<7>)

INSTRUCTION

Instruction

fetched

PC PC +1 PC +1 0004h 0005h

Instruction

executed

Inst (PC)

Inst (PC-1)

Inst (PC+1)

Inst (PC)

Inst (0004h) Inst (0005h)

Inst (0004h)Dummy cycle Dummy cycle

FFh 00h 01h 02h

Note 1: Interrupt ﬂag bit T0IF is sampled here (every Q1).

2: Interrupt latency = 4Tcy where Tcy = instruction cycle time.

3: CLKOUT is available only in RC oscillator mode.

FLOW



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 43

PIC16C64X & PIC16C66X

6.2 Using Timer0 with External Clock

When an external clock input is used for T imer0, it must

meet certain requirements. The requirements ensure

the external clock can be synchronized with the internal

phase clock (T

OSC

). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.2.1 EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 6-5).

Therefore, it is necessary for T0CKI to be high for at

least 2Tosc (and a small RC delay of 20 ns) and low for

at least 2Tosc (and a small RC delay of 20 ns). Refer to

the electrical speciﬁcation of the desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple-counter type pres-

caler so that the prescaler output is symmetrical. For

the external clock to meet the sampling requirement,

the ripple-counter must be taken into account. There-

fore, it is necessary for T0CKI to have a period of at

least 4Tosc (and a small RC delay of 40 ns) divided by

the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the mini-

mum pulse width requirement of 10 ns. Refer to param-

eters 40, 41, and 42 in the electrical speciﬁcation of the

desired device.

6.2.2 TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the T imer0 mod-

ule is actually incremented. Figure 6-5 shows the delay

from the external clock edge to the timer incrementing.

FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

External Clock Input or

Prescaler output (2)

External Clock/Prescaler

Output after sampling

Increment T imer0 (Q4)

Timer0 T0 T0 + 1 T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.

2: External clock if no prescaler selected, prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

(3) (1)

Small pulse

misses sampling

PIC16C64X & PIC16C66X

DS30559A-page 44

Preliminary



1996 Microchip Technology Inc.

6.3 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module or as a postscaler for the Watchdog

Timer (WDT), respectively (Figure 6-6). For simplicity,

this counter is being referred to as “prescaler” through-

out this data sheet. Note that the prescaler may be

used by either the Timer0 module or the Watchdog

Timer, but not both. Thus, a prescaler assignment for

the T imer0 module means that there is no prescaler for

the Watchdog Timer, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine

the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g.,

CLRF 1, MOVWF 1,

BSF 1,x

) will clear the prescaler count. When

assigned to Watchdog Timer, a

CLRWDT

instruction will

clear the prescaler count along with the Watchdog

Timer. The prescaler is not readable or writable.

FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

RA4/T0CKI

T0SE

CLKOUT (=Fosc/4)

SYNC

Cycles TMR0 reg

8-bit Prescaler

8 - to - 1MUX

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).

PSA

WDT Enable bit

Data Bus

Set ﬂag bit T0IF

on Overﬂow

PSA

T0CS



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 45

PIC16C64X & PIC16C66X

6.3.1 SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the ﬂy” during program

execution.

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0

→

WDT)

BCF STATUS, RP0 ;Bank 0

CLRF TMR0 ;Clear TMR0 & Prescaler

BSF STATUS, RP0 ;Bank 1

CLRWDT ;Clears WDT

MOVLW b'xxxx1xxx' ;Select new prescale

MOVWF OPTION_REG ;value & WDT

BCF STATUS, RP0 ;Bank 0

Note:

To avoid an unintended device RESET, the

following instruction sequence (shown in

Example 6-1) must be executed when

changing the prescaler assignment from

Timer0 to the WDT. This precaution must

be followed even if the WDT is disabled.

To change prescaler from the WDT to the Timer0 mod-

ule, use the sequence shown in Example 6-2.

EXAMPLE 6-2: CHANGING PRESCALER

(WDT

→

TIMER0)

CLRWDT ;Clear WDT and

;prescaler

BSF STATUS, RP0 ;Bank 1

MOVLW b'xxxx0xxx' ;Select TMR0, new

;prescale value and

MOVWF OPTION_REG ;clock source

BCF STATUS, RP0 ;Bank 0

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on all

other resets

01h TMR0 Timer0 module’s register

xxxx xxxx uuuu uuuu

0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

1111 1111 1111 1111

85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

--11 1111 --11 1111

Legend:

= unknown,

= unchanged,

= unimplemented locations read as '0'. Shaded cells are not used by Timer0.

PIC16C64X & PIC16C66X

DS30559A-page 46

Preliminary



1996 Microchip Technology Inc.

NOTES:



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 47

PIC16C64X & PIC16C66X

7.0 COMPARATOR MODULE

The comparator module contains two analog

comparators. The inputs to the comparators are

multiplexed with pins RA0 through RA4. The on-chip

V oltage Reference (Section 8.0) can also be an input to

the comparators.

The CMCON register , shown in Figure 7-1, controls the

comparator input and output multiplexers. A block

diagram of the comparator is shown in Figure 7-2.

FIGURE 7-1: CMCON REGISTER

(ADDRESS 1Fh)

R-0 R-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

C2OUT C1OUT — — CIS CM2 CM1 CM0 R =Readable bit

W =Writable bit

U =Unimplemented bit, read

as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7:

C2OUT

: Comparator 2 output

1 = C2 V

+ > C2 V

–

0 = C2 V

+ < C2 V

–

bit 6:

C1OUT

: Comparator 1 output

1 = C1 V

+ > C1 V

–

0 = C1 V

+ < C1 V

–

bit 5-4:

Unimplemented:

Read as '0'

bit 3:

CIS

: Comparator Input Switch

When CM2:CM0: =

001

Then:

1 = C1 V

– connects to RA3

0 = C1 V

– connects to RA0

When CM2:CM0 =

010

Then:

1 = C1 V

– connects to RA3

C2 V

– connects to RA2

0 = C1 V

– connects to RA0

C2 V

– connects to RA1

bit 2-0:

CM2:CM0

: Comparator mode

Figure 7-2 shows the comparator modes and CM2:CM0 bit settings.

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 48

Preliminary



1996 Microchip Technology Inc.

7.1 Comparator Conﬁguration

There are eight modes of operation for the

comparators. The CMCON register is used to select

the mode. Figure 7-2 shows the eight possible modes.

The TRISA register controls the data direction of the

comparator pins for each mode. If the comparator

mode is changed, the comparator output level may not

be valid for the speciﬁed mode change delay shown

in Table 12-2.

Note:

Comparator interrupts should be disabled

during a comparator mode change other-

wise a false interrupt may occur.

FIGURE 7-2: COMPARATOR I/O OPERATING MODES

RA0/AN0 VIN-

VIN+

RA3/AN3 Off (Read as '0')

Comparators Reset (POR Default Value)

CM2:CM0 = 000

RA1/AN1 VIN-

VIN+

RA2/AN2 Off (Read as '0')

RA0/AN0 VIN-

VIN+

RA3/AN3 C1OUT

Two Independent Comparators

CM2:CM0 = 100

RA1/AN1 VIN-

VIN+

RA2/AN2 C2OUT

RA0/AN0 VIN-

VIN+

RA3/AN3 C1OUT

Two Common Reference Comparators

CM2:CM0 = 011

RA1/AN1 VIN-

VIN+

RA2/AN2 C2OUT

RA0/AN0 VIN-

VIN+

RA3/AN3 Off (Read as '0')

One Independent Comparator

CM2:CM0 = 101

RA1/AN1 VIN-

VIN+

RA2/AN2 C2OUT

RA0/AN0 VIN-

VIN+

RA3/AN3 Off (Read as '0')

Comparators Off

CM2:CM0 = 111

RA1/AN1 VIN-

VIN+

RA2/AN2 Off (Read as '0')

RA0/AN0 VIN-

VIN+

RA3/AN3 C1OUT

Four Inputs Multiplexed to Two Comparators

CM2:CM0 = 010

RA1/AN1 VIN-

VIN+

RA2/AN2 C2OUT

From VREF Module

CIS = 0

CIS = 1

CIS = 0

CIS = 1

RA0/AN0 VIN-

VIN+

RA3/AN3 C1OUT

Two Common Reference Comparators with Outputs

CM2:CM0 = 110

RA1/AN1 VIN-

VIN+

RA2/AN2 C2OUT

RA4 Open Drain

RA0/AN0 VIN-

VIN+

RA3/AN3 C1OUT

Three Inputs Multiplexed to Two Comparators

CM2:CM0 = 001

RA1/AN1 VIN-

VIN+

RA2/AN2 C2OUT

CIS = 0

CIS = 1

A = Analog Input, port reads zeros always.

D = Digital Input.

CIS (CMCON<3>) is the Comparator Input Switch.



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 49

PIC16C64X & PIC16C66X

The code example in Example 7-1 depicts the steps

required to conﬁgure the comparator module. RA3 and

RA4 are conﬁgured as digital outputs. RA0 and RA1

are conﬁgured as the V - inputs and RA2 as the V+ input

to both comparators.

EXAMPLE 7-1: INITIALIZING THE

COMPARATOR MODULE

FLAG_REG EQU 0x20

CLRF FLAG_REG ;Init Flag Register

CLRF PORTA ;Init PORTA

ANDLW 0xC0 ;Mask Comp bits

IORWF FLAG_REG,F ;Bits to Flag_Reg

MOVLW 0x03 ;Init Comp Mode

MOVWF CMCON ;CM2:CM0 = 011

BSF STATUS,RP0 ;Select Bank 1

MOVLW 0x07 ;Init Data direction

MOVWF TRISA ;RA<2:0> to inputs

;RA<4:3> to outputs

;TRISA<7:5> read '0'

BCF STATUS,RP0 ;Select Bank 0

CALL DELAY_10

s ;10

s delay

MOVF CMCON,F ;Read CMCON to end

;change condition

BCF PIR1,CMIF ;Clear Pending Ints

BSF STATUS,RP0 ;Select Bank 1

BSF PIE1,CMIE ;Enable Comp Ints

BCF STATUS,RP0 ;Select Bank 0

BSF INTCON,PEIE ;Enable Periph Ints

BSF INTCON,GIE ;Global Int enable

7.2 Comparator Operation

A single comparator is shown in Figure 7-3 along with

the relationship between the analog input levels and

the digital output. When the analog input at V

+ is less

than the analog input V

–, the output of the comparator

is a digital low level. When the analog input at V

+ is

greater than the analog input V

–, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 7-3 represents

the uncertainty due to input offsets and response time.

7.3 Comparator Reference

An external or internal reference signal may be used

depending on the comparator operating mode. The

analog signal that is present at V

– is compared to the

signal at V

+, and the digital output of the comparator

is adjusted accordingly (Figure 7-3).

FIGURE 7-3: SINGLE COMPARATOR

7.3.1 EXTERNAL REFERENCE SIGNAL

When external voltage references are used, the

comparator module can be conﬁgured to have the com-

parators operate from the same or different reference

sources. However , threshold detector applications may

require the same reference. The reference signal must

be between V

and V

, and can be applied to either

pin of the comparator(s).

7.3.2 INTERNAL REFERENCE SIGNAL

The comparator module also allows the selection of an

internally generated voltage reference for the

comparators. Section 8.0, contains a detailed descrip-

tion of the V oltage Reference Module that provides this

signal. The internal reference signal is used when the

comparators are in mode CM2:CM0 =

010

(Figure 7-2). In this mode, the internal voltage refer-

ence is applied to the V

+ pin of both comparators.

VIN-

VIN+Output

VIN-

VIN+

Output

PIC16C64X & PIC16C66X

DS30559A-page 50 Preliminary  1996 Microchip Technology Inc.

7.4 Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output is guaranteed to have a valid level.

If the internal reference is changed, the maximum delay

of the internal voltage reference must be considered

when using the comparator outputs. Otherwise, the

maximum delay of the comparators should be used

(Table 12-2 and Table 12-3).

7.5 Comparator Outputs

The comparator outputs are read through the CMCON

outputs may also be directly output to the RA3 and RA4

I/O pins. When CM2:CM0 = 110, multiplexors in the

output path of the RA3 and RA4 pins will switch and the

output of each pin will be the unsynchronized output of

the comparator. The uncertainty of each of the

comparators is related to the input offset voltage and

the response time given in the speciﬁcations.

Figure 7-4 shows the comparator output block diagram.

The TRISA bits will still function as an output enable/

disable for the RA3 and RA4 pins while in this mode.

Note 1: When reading the PORTA register , all pins

conﬁgured as analog inputs will read as a

‘0’. Pins conﬁgured as digital inputs will

convert an analog input according to the

Schmitt Trigger input speciﬁcation.

Note 2: Analog levels on any pin that is deﬁned as

a digital input may cause the input buffer

to consume more current than is speci-

ﬁed.

FIGURE 7-4: COMPARATOR OUTPUT BLOCK DIAGRAM

To RA3 or RA4 pin

RD CMCON

Set CMIF bit

MULTIPLEX

Port Pins

RD CMCON

NRESET

From other Comparator

To Data Bus

 1996 Microchip Technology Inc. Preliminary DS30559A-page 51

PIC16C64X & PIC16C66X

7.6 Comparator Interrupts

The comparator interrupt ﬂag is set whenever there is

a change in the output value of either comparator . User

software will need to maintain information about the

status of the output bits, as read from CMCON<7:6>, to

determine the actual change that has occurred. The

CMIF bit (PIR1<6>), is the comparator interrupt ﬂag

and must be cleared in user software.

To enable the Comparator interrupt the following bits

must be set:

• CMIE (PIE1<6>)

• PEIE (INTCON<6>)

• GIE (INTCON<7>)

The user, in the interrupt service routine, can clear the

interrupt in the following manner:

a) Any read or write of CMCON. This will end the

mismatch condition.

b) Clear ﬂag bit CMIF.

A mismatch condition will continue to set ﬂag bit CMIF.

Reading CMCON will end the mismatch condition, and

allow ﬂag bit CMIF to be cleared.

7.7 Comparator Operation During SLEEP

When a comparator is active and the device is placed

in SLEEP mode, the comparator remains active and

the interrupt is functional if enabled. This interrupt will

wake up the device from SLEEP mode when enabled.

While the comparator is powered up, higher sleep

currents than shown in the power-down current

speciﬁcation will occur. Each comparator that is

operational will consume additional current as shown in

the comparator speciﬁcations. To minimize power

consumption while in SLEEP mode, turn off the

comparators, CM2:CM0 = 111, before entering sleep.

If the device wakes up from sleep, the contents of the

CMCON register are not affected.

7.8 Effects of a RESET

A device reset forces the CMCON register to its reset

state. This forces the comparator module to be in the

comparator reset mode, CM2:CM0 = 000. This

ensures that all potential inputs are analog inputs.

Device current is minimized when analog inputs are

present at reset time. The comparators will be powered

down during the reset interval.

7.9 Analog Input Connection

Considerations

A simpliﬁed circuit for an analog input is shown in

Figure 7-5. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. The analog input therefore, must be between

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up may occur. A

maximum source impedance of 10 kΩ is

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

FIGURE 7-5: ANALOG INPUT MODEL

AIN CPIN

5 pF

VDD

VT = 0.6V

RC < 10k

ILEAKAGE

±500 nA

VSS

Legend CPIN = Input Capacitance

VT= Threshold V oltage

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC = Interconnect Resistance

RS= Source Impedance

VA= Analog V oltage

PIC16C64X & PIC16C66X

DS30559A-page 52 Preliminary  1996 Microchip Technology Inc.

TABLE 7-1: REGISTERS ASSOCIATED WITH THE COMPARATOR MODULE

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

Value on

all other

resets

1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000

9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000

0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) CMIF — — — — — — 00-- ---- 00-- ----

8Ch PIE1 PSPIE(1) CMIE — — — — — — 00-- ---- 00-- ----

85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

Note 1: These bits are reserved on the PIC16C641/642, always maintain these bits clear.



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 53

PIC16C64X & PIC16C66X

8.0 VOLTAGE REFERENCE

MODULE

The Voltage Reference is a 16-tap resistor ladder

network that provides a selectable voltage reference.

The resistor ladder is segmented to provide two ranges

of V

REF

values and has a power-down function to

conserve power when the reference module is not

being used.

The VRCON register , shown in Figure 8-1, controls the

operation of the Voltage Reference Module. The block

diagram is given in Figure 8-2.

FIGURE 8-1: VRCON REGISTER (ADDRESS 9Fh)

FIGURE 8-2: VOLTAGE REFERENCE BLOCK DIAGRAM

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

VREN VROE VRR — VR3 VR2 VR1 VR0 R =Readable bit

W =Writable bit

U =Unimplemented bit, read

as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7:

VREN:

REF

Enable

1 = V

REF

circuit powered up

0 = V

REF

circuit powered down, no I

drain

bit 6:

VROE:

REF

Output Enable

1 = V

REF

is output on RA2 pin

0 = V

REF

is disconnected from RA2 pin

bit 5:

VRR:

REF

Range selection

1 = Low Range

0 = High Range

bit 4:

Unimplemented:

Read as '0'

bit 3-0:

VR3:VR0

: V

REF

value selection 0

≤

VR3:VR0

≤

When: VRR = 1

Then: V

REF

= (VR3:VR0/ 24) • V

When: VRR = 0

Then: V

REF

= 1/4 • V

+ (VR3:VR0/ 32) • V

Note: R is deﬁned in Table 12-3.

VRR

VR3

VR0 (From VRCON<3:0>)

16-1 Analog Mux

8R RRRR

VREN

VREF

16 Stages

VR2

VR1

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 54

Preliminary



1996 Microchip Technology Inc.

8.1 Conﬁguring the Voltage Reference

The Voltage Reference Module can output 16 distinct

voltage levels for each range.

The equations used to calculate the output of the

Voltage Reference are as follows:

If VRR = 1

Then V

REF

= (VR3:VR0/24) • V

If VRR = 0

Then V

REF

= (V

• 1/4) + (VR3:VR0/32) • V

The settling time of the Voltage Reference must be

considered when changing the V

REF

output

(Table 12-2). Example 8-1 shows an example of how to

conﬁgure the Voltage Reference for an output voltage

of 1.25V with V

= 5.0V.

EXAMPLE 8-1: VOLTAGE REFERENCE

CONFIGURATION

MOVLW 0x02 ; 4 inputs muxed

MOVWF CMCON ; to 2 comparators

BSF STATUS,RP0 ; Select Bank 1

MOVLW 0x07 ; RA3:RA0 to outputs

MOVWF TRISA ;

MOVLW 0xA6 ; enable Vref low

MOVWF VRCON ; range, VR3:VR0 = 6

BCF STATUS,RP0 ; Select Bank 0

CALL DELAY_10

s ; 10

s delay

8.2 Voltage Reference Accuracy/Error

The full range of V

to V

cannot be realized due to

the construction of the module. The transistors on the

top and bottom of the resistor ladder network

(Figure 8-2) keep V

REF

from approaching V

or V

The Voltage Reference is V

derived and therefore,

the V

REF

output changes with ﬂuctuations in V

. The

absolute accuracy of the Voltage Reference can be

found in Table 12-3.

8.3 Operation During Sleep

When the device wakes up from sleep through an

interrupt or a W atchdog T imer time-out, the contents of

the VRCON register are not affected. To minimize

current consumption in SLEEP mode, the Voltage

Reference Module should be disabled.

8.4 Effects of a Reset

A device reset disables the V oltage Reference by clear-

ing bit VREN (VRCON<7>). This reset also

disconnects the reference from the RA2 pin by clearing

bit VROE (VRCON<6>) and selects the high voltage

range by clearing bit VRR (VRCON<5>). The V

REF

value select bits, VRCON<3:0>, are also cleared.

8.5 Connection Considerations

The Voltage Reference Module operates independently

of the comparator module. The output of the reference

generator may be connected to the RA2 pin if the

TRISA<2> bit is set and bit VROE is set. Enabling the

Voltage Reference output onto the RA2 pin with an

input signal present will increase current consumption.

Connecting RA2 as a digital output with V

REF

enabled

will also increase current consumption.

The RA2 pin can be used as a simple D/A output with

limited drive capability. Due to the limited drive

capability, a buffer must be used in conjunction with the

Voltage Reference output for external connections to

REF

. Figure 8-3 shows an example buffering

technique.

FIGURE 8-3: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

TABLE 8-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value On

POR,

BOR

Value on

all other

resets

9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0

000- 0000 000- 0000

1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0

00-- 0000 00-- 0000

85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

--11 1111 --11 1111

Note 1: R is dependent upon the Voltage Reference Conﬁguration VRCON<3:0> and VRCON<5>.

VREF output

Voltage

Reference

Output

Impedance

R(1) Pin RA2

VREF

Module

PIC16C662



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 55

PIC16C64X & PIC16C66X

9.0 SPECIAL FEATURES OF THE

CPU

What sets apart a microcontroller from other

processors are special circuits to deal with the needs of

real-time applications. The PIC16C64X & PIC16C66X

families have a host of such features intended to max-

imize system reliability, minimize cost through elimina-

tion of external components, provide power saving

operating modes and offer code protection.

These are:

1. Oscillator selection

2. Resets

Power-on Reset (POR)

Power-up T imer (PWRT)

Oscillator Start-up Timer (OST)

Brown-out Reset (BOR)

Parity Error Reset (PER)

3. Interrupts

4. Watchdog T imer (WDT)

5. SLEEP

6. Code protection

7. ID Locations

8. In-circuit serial programming

The PIC16C64X & PIC16C66X has a Watchdog Timer

which is enabled by a conﬁguration bit (WDTE). It runs

off its own RC oscillator for added reliability. There are

two timers that offer necessary delays on power-up.

One is the Oscillator Start-up Timer (OST), intended to

keep the chip in reset until the crystal oscillator is sta-

ble. The other is the Power-up Timer (PWRT), which

provides a ﬁxed delay of 72 ms (nominal) on power-up

only, designed to keep the part in reset while the power

supply stabilizes. Circuitry has been provided for

checking program memory parity with a reset when an

error is indicated. There is also circuitry to reset the

device if a brown-out occurs which provides at least a

72 ms reset. With these three functions on-chip, most

applications need no external reset circuitry.

SLEEP mode is designed to offer a very low current

power-down mode. The user can wake-up from SLEEP

through external reset, Watchdog Timer wake-up or

through an interrupt. Several oscillator options are also

made available to allow the part to ﬁt the application.

The RC oscillator option saves system cost while the

LP crystal option saves power. A set of conﬁguration

bits are used to select various options.

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 56

Preliminary



1996 Microchip Technology Inc.

9.1 Conﬁguration Bits

The conﬁguration bits can be programmed (read as '0')

or left unprogrammed (read as '1') to select various

device conﬁgurations. These bits are mapped in

program memory location 2007h.

The user will note that address 2007h is beyond

the user program memory space. In fact, it belongs

to the special test/conﬁguration memory space

(2000h–3FFFh), which can be accessed only during

programming.

FIGURE 9-1: CONFIGURATION WORD

CP1 CP0 CP1 CP0 CP1 CP0 MPEEN BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 CONFIG Address

bit13 bit0

bit 13-8

CP1:CP0:

Code protection bits

(2)

5-4:

= Code protection off

= Upper half of program memory code protected

= Upper 3/4th of program memory code protected

= All memory is code protected

bit 7:

MPEEN

: Memory Parity Error Enable

1 = Memory Parity Checking is enabled

0 = Memory Parity Checking is disabled

bit 6:

BODEN

: Brown-out Reset Enable bit

(1)

1 = BOR enabled

0 = BOR disabled

bit 3:

PWRTE

: Power-up Timer Enable bit

(1)

1 = PWRT disabled

0 = PWRT enabled

bit 2:

WDTE

: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0:

FOSC1:FOSC0

: Oscillator Selection bits

= RC oscillator

= HS oscillator

= XT oscillator

= LP oscillator

Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the

Power-up Timer is enabled anytime Brown-out Reset is enabled.

2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 57

PIC16C64X & PIC16C66X

9.2 Oscillator Conﬁgurations

9.2.1 OSCILLATOR TYPES

The PIC16CXXX can be operated in four different

oscillator modes. The user can program two

conﬁguration bits (FOSC1 and FOSC0) to select one of

these four modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC Resistor/Capacitor

9.2.2 CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

In XT, LP or HS modes a crystal or ceramic resonator

is connected to the OSC1 and OSC2 pins to establish

oscillation (Figure 9-2). The PIC16CXXX oscillator

design requires the use of a parallel cut crystal. Use of

a series cut crystal may give a frequency out of the

crystal manufacturers speciﬁcations. When in XT, LP or

HS modes, the device can have an external clock

source to drive the OSC1 pin (Figure 9-3).

FIGURE 9-2: CRYSTAL OPERATION

(OR CERAMIC RESONATOR)

(HS, XT OR LP OSC

CONFIGURATION)

FIGURE 9-3: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP

OSC CONFIGURATION)

See Table 9-1 or Table 9-2 for recommended val-

ues of C1 and C2.

Note: A series resistor may be required for

AT strip cut crystals.

XTAL

OSC2

OSC1

RF SLEEP

To internal logic

PIC16CXXX

see Note

clock from

ext. system PIC16CXXX

OSC1

OSC2

Open

TABLE 9-1: CAPACITOR SELECTION

FOR CERAMIC RESONATORS

(PRELIMINARY)

TABLE 9-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

(PRELIMINARY)

Ranges tested:

Mode Freq OSC1

XT 455 kHz

2.0 MHz

4.0 MHz

22 - 100 pF

15 - 68 pF

HS 8.0 MHz

16.0 MHz 10 - 68 pF

10 - 22 pF

Note: Recommended values of C1 and C2 are identical

to the ranges tested table.

Higher capacitance increases the stability of the

oscillator but also increases the start-up time.

These values are for design guidance only. Since

each resonator has its own characteristics, the

user should consult the resonator manufacturer for

appropriate values of external components.

Resonators used:

455 kHz Panasonic EFO-A455K04B

0.3%

2.0 MHz Murata Erie CSA2.00MG

0.5%

4.0 MHz Murata Erie CSA4.00MG

0.5%

8.0 MHz Murata Erie CSA8.00MT

0.5%

16.0 MHz Murata Erie CSA16.00MX

0.5%

All resonators used did not have built-in capacitors.

Mode Freq OSC1 OSC2

LP 32 kHz

200 kHz 68 - 100 pF

15 - 30 pF 68 - 100 pF

15 - 30 pF

XT 100 kHz

2 MHz

4 MHz

68 - 150 pF

15 - 30 pF

150 - 200 pF

15 - 30 pF

HS 8 MHz

10 MHz

20 MHz

15 - 30 pF

Higher capacitance increases the stability of the

oscillator but also increases the start-up time.

These values are for design guidance only. Rs may

be required in HS mode as well as XT mode to

avoid overdriving crystals with low drive level spec-

iﬁcation. Since each crystal has its own

characteristics, the user should consult the crystal

manufacturer for appropriate values of external

components.

Crystals used:

32.768 kHz Epson C-001R32.768K-A

20 PPM

100 kHz Epson C-2 100.00 KC-P

20 PPM

200 kHz STD XTL 200.000 kHz

20 PPM

2.0 MHz ECS ECS-20-S-2

50 PPM

4.0 MHz ECS ECS-40-S-4

50 PPM

10.0 MHz ECS ECS-100-S-4

50 PPM

20.0 MHz ECS ECS-200-S-4

50 PPM

PIC16C64X & PIC16C66X

DS30559A-page 58

Preliminary



1996 Microchip Technology Inc.

9.2.3 EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

Either a prepackaged oscillator can be used or a simple

oscillator circuit with TTL gates can be built. Prepack-

aged oscillators provide a wide operating range and

better stability. A well-designed crystal oscillator will

provide good performance with TTL gates. Two types

of crystal oscillator circuits can be used: one with series

resonance, or one with parallel resonance.

Figure 9-4 shows implementation of a parallel resonant

oscillator circuit. The circuit is designed to use the fun-

damental frequency of the crystal. The 74AS04 inverter

performs the 180-degree phase shift that a parallel

oscillator requires. The 4.7 k

Ω

resistor provides the

negative feedback for stability. The 10 k

Ω

potentiome-

ter biases the 74AS04 in the linear region. This could

be used for external oscillator designs.

FIGURE 9-4: EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Figure 9-5 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental fre-

quency of the crystal. The inverter performs a

180-degree phase shift in a series resonant oscillator

circuit. The 330 k

Ω

resistors provide the negative feed-

back to bias the inverters in their linear region.

FIGURE 9-5: EXTERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

20 pF

+5V

20 pF

10k 4.7k

10k

74AS04

XTAL

10k

74AS04

CLKIN

To Other

Devices

PIC16CXXX

330 kΩ

74AS04 74AS04 PIC16CXXX

CLKIN

To Other

Devices

XTAL

330 kΩ

74AS04

0.1 µF

9.2.4 RC OSCILLATOR

For timing insensitive applications the “RC” device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the resis-

tor (Rext) and capacitor (Cext) values, and the operat-

ing temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal pro-

cess parameter variation. Furthermore, the difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

Cext values. The user also needs to take into account

variation due to tolerance of external R and C compo-

nents used. Figure 9-6 shows how the R/C combina-

tion is connected to the PIC16CXXX. For Rext values

below 2.2 k

Ω

, the oscillator operation may become

unstable, or stop completely. For very high Rext values

(e.g. 1 M

Ω

), the oscillator becomes sensitive to noise,

humidity and leakage. Thus, we recommend to keep

Rext between 3 k

Ω

and 100 k

Ω

Although the oscillator will operate with no external

capacitor (Cext = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or pack-

age lead frame capacitance.

See characterization data for desired device for RC fre-

quency variation from part to part due to normal pro-

cess variation. The variation is larger for larger R (since

leakage current variation will affect RC frequency more

for large R) and for smaller C (since variation of input

capacitance will affect RC frequency more).

See characterization data for desired device for varia-

tion of oscillator frequency due to V

for given Rext/

Cext values as well as frequency variation due to oper-

ating temperature for given R, C, and V

values.

The oscillator frequency, divided by 4, is available on

the OSC2/CLKOUT pin, and can be used for test pur-

poses or to synchronize other logic (see Figure 3-3 for

waveform).

FIGURE 9-6: RC OSCILLATOR MODE

OSC2/CLKOUT

Cext

VDD

Rext

VSS

PIC16CXXX

OSC1

Fosc/4

Internal

clock



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 59

PIC16C64X & PIC16C66X

9.3 Reset

The PIC16CXXX differentiates between various kinds

of reset:

a) Power-on reset (POR)

b) MCLR reset during normal operation

c) MCLR reset during SLEEP

d) WDT reset (normal operation)

e) Brown-out Reset (BOR)

f) Parity Error Reset (PER)

Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in any

other reset. Most other registers are reset to a “reset

state” on Power-on reset, MCLR, WDT reset,

Brown-out Reset, Parity Error Reset, and on MCLR

reset during SLEEP. They are not affected by a WDT

wake-up, since this is viewed as the resumption of nor-

mal operation. T O and PD bits are set or cleared dif fer-

ently in different reset situations as indicated in

Table 9-4. These bits are used in software to determine

the nature of the reset. See Table 9-6 for a full descrip-

tion of reset states of all registers.

A simpliﬁed block diagram of the on-chip reset circuit is

shown in Figure 9-7.

The MCLR reset path has a noise ﬁlter to detect and

ignore small pulses. See Table 12-6 for pulse width

speciﬁcation.

FIGURE 9-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/

VDD

OSC1/

WDT

Module

VDD rise

detect

OST/PWRT

On-chip(1)

RC OSC

WDT Time-out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple-counter

Enable OST

Enable PWRT

SLEEP

See Table 9-3 for time-out situations.

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

Brown-out

Reset BODEN

CLKIN

VPP Pin

10-bit Ripple-counter

Program

Memory

Parity

MPEEN

PIC16C64X & PIC16C66X

DS30559A-page 60

Preliminary



1996 Microchip Technology Inc.

9.4 Power-on Reset (POR), Power-up

Timer (PWRT), Oscillator Start-up

Timer (OST), Brown-out Reset (BOR),

and Parity Error Reset (PER)

9.4.1 POWER-ON RESET (POR)

A Power-on Reset pulse is generated on-chip when

rise is detected (in the range of 1.6V to 1.8V). To

take advantage of the POR, just tie the MCLR pin

directly (or through a resistor) to V

. This will

eliminate external RC components usually needed to

create a Power-on Reset. A maximum rise time for V

is required. See Electrical Speciﬁcations for details.

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature, etc.) must be met to ensure

operation. If these conditions are not met, the device

must be held in reset until the operating conditions are

met.

For additional information, refer to Application Note

AN607 “

P ower-up Trouble Shooting.

”

9.4.2 POWER-UP T IMER (PWRT)

The Power-up Timer provides a ﬁxed 72 ms (nominal)

delay on power-up only, from POR or BOR. The

Power-up Timer operates on an internal RC oscillator.

The chip is kept in reset as long as PWRT is active. The

PWRT delay allows V

to rise to an acceptable level.

A conﬁguration bit, PWRTE can disable (if set) or

enable (if cleared or programmed) the Power-up T imer .

The Power-up Timer should always be enabled when

Brown-out Reset is enabled.

The power-up time delay will vary from chip to chip due

to V

, temperature, and process variations. See DC

parameters for details.

9.4.3 OSCILLATOR START-UP TIMER (OST)

The Oscillator Start-Up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal

oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP, and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

9.4.4 BROWN-OUT RESET (BOR)

PIC16C64X & PIC16C66X devices have on-chip

Brown-out Reset circuitry. A conﬁguration bit, BODEN,

can disable (if clear/programmed) or enable (if set) the

Brown-out Reset circuitry. If V

falls below 4.0V

(Parameter D005 in ES section) for greater than

parameter 35 in Table 12-6, the brown-out situation will

reset the chip. A reset is not guaranteed to occur if V

falls below 4.0V for less than parameter 35. The chip

will remain in Brown-out Reset until V

rises above

. The Power-up Timer will now be invoked and will

keep the chip in reset an additional 72 ms. If V

drops

below BV

while the Power-up Timer is running, the

chip will go back into a Brown-out Reset and the

Power-up Timer will be initialized. Once V

rises

above BV

, the Power-up Timer will execute a 72 ms

time delay. The Power-up Timer should always be

enabled when Brown-out Reset is enabled. Figure 9-8

shows typical Brown-out situations.

FIGURE 9-8: BROWN-OUT SITUATIONS

72 ms

BVDD Max.

BVDD Min.

VDD

Internal

Reset

BVDD Max.

BVDD Min.

VDD

Internal

Reset 72 ms

<72 ms

72 ms

BVDD Max.

BVDD Min.

VDD

Internal

Reset



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 61

PIC16C64X & PIC16C66X

9.4.5 PARITY ERROR RESET (PER)

PIC16C64X & PIC16C66X devices have on-chip parity

bits that can be used to verify the contents of program

memory. Parity bits may be useful in applications in

order to increase overall reliability of a system.

There are two parity bits for each word of Program

Memory. The parity bits are computed on alternating

bits of the program word. One computation is per-

formed using even parity, the other using odd parity. As

a program executes, the parity is veriﬁed. The even

parity bit is XOR’d with the even bits in the program

memory word. The odd parity bit is negated and XOR’d

with the odd bits in the program memory word. When

an error is detected, a reset is generated and the PER

ﬂag bit in the PCON register is set. This indication can

allow software to act on a failure. However, there is no

indication of the program memory location of the failure

of the Program Memory. This ﬂag can only be cleared

in software or by a POR.

The parity array is user selectable during programming.

Bit7 of the conﬁguration word located at address 2007h

can be programmed (read as '0') to disable parity

checking. If left unprogrammed (read as '1'), parity

checking is enabled.

9.4.6 TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows: First

PWRT time-out is invoked after POR has expired. Then

the OST is activated. The total time-out will vary based

on oscillator conﬁguration and PWRTE bit status. For

example, in RC mode with the PWRTE bit set (PWRT

disabled), there will be no time-out at all. Figure 9-9,

Figure 9-10 and Figure 9-11 depict time-out

sequences.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then

bringing MCLR high will begin execution immediately

(Figure 9-10). This is useful for testing purposes or to

synchronize more than one device operating in parallel.

Table 9-5 shows the reset conditions for some special

registers, while Table 9-6 shows the reset conditions

for all the registers.

9.4.7 POWER CONTROL/STATUS REGISTER

(PCON)

The power control/status register, PCON (address

8Eh) has four bits. See Figure 4-10 for register.

Bit0 is BOR (Brown-out Reset). BOR is unknown on a

Power-on-reset. It must initially be set by the user and

checked on subsequent resets to see if BOR = '0'

indicating that a Brown-out Reset has occurred. The

BOR status bit is a “don’t care” bit and is not necessar-

ily predictable if the brown-out circuit is disabled (by

clearing the BODEN bit in the Conﬁguration word).

Bit1 is POR (Power-on Reset). It is cleared on a

Power-on Reset and is unaffected otherwise. The user

set this bit following a Power-on Reset. On subsequent

resets if POR is ‘0’, it will indicate that a Power-on

Reset must have occurred.

Bit2 is PER (Parity Error Reset). It is cleared on a Parity

Error Reset and must be set by user software. It will

also be set on a Power-on Reset.

Bit7 is MPEEN (Memory Parity Error Enable). This bit

reﬂects the status of the MPEEN bit in conﬁguration

word. It is unaffected by any reset or interrupt.

TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS

Oscillator Conﬁguration Power-up Brown-out Reset Wake-up

from SLEEP

PWRTE = 0 PWRTE = 1

XT, HS, LP 72 ms + 1024 T

OSC

1024 T

OSC

72 ms + 1024 T

OSC

1024 T

OSC

RC 72 ms — 72 ms —

PIC16C64X & PIC16C66X

DS30559A-page 62

Preliminary  1996 Microchip Technology Inc.

TABLE 9-4: STATUS BITS AND THEIR SIGNIFICANCE

TABLE 9-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

PER POR BOR TO PD

10x11Power-on Reset

x0x0xIllegal, T O is set on POR

x0xx0Illegal, PD is set on POR

11011Brown-out Reset

11101WDT Reset

11100WDT Wake-up

111uuMCLR reset during normal operation

11110MCLR reset during SLEEP

01111Parity Error Reset

00xxxIllegal, PER is set on POR

0x0xxIllegal, PER is set on BOR

Condition Program

Counter STATUS

Power-on Reset 000h 0001 1xxx u--- -10x

MCLR reset during normal operation 000h 000u uuuu u--- -uuu

MCLR reset during SLEEP 000h 0001 0uuu u--- -uuu

WDT reset 000h 0000 1uuu u--- -uuu

WDT Wake-up PC + 1 uuu0 0uuu u--- -uuu

Brown-out Reset 000h 0001 1uuu u--- -uu0

Parity Error Reset 000h 0001 1uuu 1--- -0uu

Interrupt Wake-up from SLEEP PC + 1(1) uuu1 0uuu u--- -uuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the inter-

rupt vector (0004h) after execution of PC+1.

 1996 Microchip Technology Inc. Preliminary DS30559A-page 63

PIC16C64X & PIC16C66X

TABLE 9-6: INITIALIZATION CONDITION FOR REGISTERS

Brown-out Reset

Parity Error Reset

MCLR Reset during:

- normal operation

- SLEEP or

WDT Reset

Wake up from SLEEP

through:

- interrupt

- WDT time-out

W- xxxx xxxx uuuu uuuu uuuu uuuu

INDF 00h -- -

TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu

PCL 02h 0000 0000 0000 0000 PC + 1(2)

STATUS 03h 0001 1xxx 000q quuu(3) uuuq quuu(3)

FSR 04h xxxx xxxx uuuu uuuu uuuu uuuu

PORTA 05h --xx 0000 --xu 0000 --uu uuuu

PORTB 06h xxxx xxxx uuuu uuuu uuuu uuuu

PORTC 07h xxxx xxxx uuuu uuuu uuuu uuuu

PORTD(4) 08h xxxx xxxx uuuu uuuu uuuu uuuu

PORTE(4) 09h ---- -xxx ---- -uuu ---- -uuu

CMCON 1Fh 00-- 0000 00-- 0000 uu-- uuuu

PCLATH 0Ah ---0 0000 ---0 0000 ---u uuuu

INTCON 0Bh 0000 000x 0000 000u uuuu uuuu(1)

PIR1 0Ch 00-- ---- 00-- ---- uu-- ----(1)

OPTION 81h 1111 1111 1111 1111 uuuu uuuu

TRISA 85h --11 1111 --11 1111 --uu uuuu

TRISB 86h 1111 1111 1111 1111 uuuu uuuu

TRISC 87h 1111 1111 1111 1111 uuuu uuuu

TRISD(4) 88h 1111 1111 1111 1111 uuuu uuuu

TRISE(4) 89h 0000 -111 0000 -111 uuuu -uuu

PIE1 8Ch 00-- ---- 00-- ---- uu-- ----

PCON 8Eh u--- -qqq u--- -uuu u--- -uuu

VRCON 9Fh 000- 0000 000- 0000 uuu- uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’,q = value depends on condition.

Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

3: See Table 9-5 for reset value for speciﬁc condition.

4: These registers are associated with the Parallel Slave Port and are not implemented on the PIC16C641/642.

PIC16C64X & PIC16C66X

DS30559A-page 64 Preliminary  1996 Microchip Technology Inc.

FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 9-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

 1996 Microchip Technology Inc. Preliminary DS30559A-page 65

PIC16C64X & PIC16C66X

FIGURE 9-12: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

FIGURE 9-13: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 1

Note 1: External power-on reset circuit is required

only if VDD power-up slope is too slow.

The diode D helps discharge the capaci-

tor quickly when VDD powers down.

2: R < 40 kΩ is recommended to make sure

that voltage drop across R does not vio-

late the device’s electrical speciﬁcation.

3: R1 = 100Ω to 1 kΩ will limit any current

ﬂowing into MCLR from external capaci-

tor C in the event of MCLR/VPP pin

breakdown due to Electrostatic Dis-

charge (ESD) or Electrical Overstress

(EOS).

VDD

MCLR

PIC16CXXX

VDD

Note 1: This circuit will activate reset when VDD

goes below (Vz + 0.7V) where

Vz = Zener voltage.

2: Internal Brown-out Reset circuitry

should be disabled when using this cir-

cuit.

3: Resistors should be adjusted for the

characteristics of the transistor.

VDD 33k

10k

40k

VDD

MCLR

PIC16CXXX

FIGURE 9-14: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

Note 1: This brown-out circuit is less expensive,

albeit less accurate. T ransistor Q1 turns

off when VDD is below a certain level

such that:

2: Internal Brown-out Reset circuitry

should be disabled when using this cir-

cuit.

3: Resistors should be adjusted for the

characteristics of the transistor.

VDD • R1

R1 + R2 = 0.7 V

VDD

R2 40k

VDD

MCLR

PIC16CXXX

PIC16C64X & PIC16C66X

DS30559A-page 66 Preliminary  1996 Microchip Technology Inc.

9.5 Interrupts

The PIC16C641 and PIC16C642 have four sources of

interrupt, while the PIC16C661 and PIC16C662 have

five sources:

• External interrupt RB0/INT

• TMR0 overﬂow interrupt

• PORTB change interrupts (pins RB7:RB4)

• Comparator interrupt

• Parallel Slave Port interrupt (PIC16C661/662)

The interrupt control register, (INTCON), records

individual core interrupt requests in ﬂag bits. It also has

various individual enable bits and the global interrupt

enable bit.

The global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. GIE is cleared on reset.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine as well as sets the GIE bit, which

allows any pending interrupt to execute.

Those interrupts associated with the “core” have their

ﬂag and enable bits in the INTCON register. The core

interrupts are: RB0/INT pin interrupt, the RB port

change interrupt, and the TMR0 overﬂow interrupt. The

INTCON register also contains the Peripheral Interrupt

Enable bit, PEIE. Bit PEIE will enable/mask the periph-

eral interrupts (CM and PSP) from vectoring when bit

PEIE is set/cleared.

Flag bits PSPIF and CMIF are contained in special

function register PIR1. The corresponding interrupt

enable bits (PSPIE and CMIE) are contained in special

function register PIE1.

When an interrupt is responded to, the GIE is cleared

to disable any further interrupt, the return address is

pushed into the stack and the PC is loaded with 0004h.

Once in the interrupt service routine the source(s) of

the interrupt can be determined by polling the interrupt

ﬂag bits. The interrupt ﬂag bit(s) must be cleared in

software before re-enabling interrupts to avoid recur-

sive interrupts.

For external interrupt events, such as the RB0/INT or

Port RB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs (Figure 9-16).

The latency is the same for one or two cycle

instructions. Once in the interrupt service routine the

source(s) of the interrupt can be determined by polling

the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be

cleared in software before re-enabling interrupts to

avoid multiple interrupt requests. Individual interrupt

ﬂag bits are set regardless of the status of their

corresponding mask bit or the GIE bit.

Note 1: Individual interrupt ﬂag bits are set regard-

less of the status of their corresponding

mask bit or the GIE bit.

Note 2: When an instruction that clears the GIE bit

is executed, any interrupts that were

pending for execution in the next cycle are

ignored. The CPU will execute a NOP in

the cycle immediately following the

instruction which clears the GIE bit. The

interrupts which were ignored are still

pending to be serviced when the GIE bit is

set again.

FIGURE 9-15: INTERRUPT LOGIC

RBIF

RBIE

T0IF

T0IE

INTF

INTE

GIE

CMIE

Wake-up

(If in SLEEP mode)

Interrupt

CMIF

to CPU

PSPIE(1)

PSPIF(1)

PEIE

Note 1: The Parallel Slave Port is implemented on the PIC16C661 and PIC16C662 only.

 1996 Microchip Technology Inc. Preliminary DS30559A-page 67

PIC16C64X & PIC16C66X

9.5.1 RB0/INT INTERRUPT

The external interrupt on the RB0/INT pin is edge trig-

gered: either rising if bit INTEDG (OPTION<6>) is set,

or falling, if bit INTEDG is clear. When a valid edge

appears on the RB0/INT pin, ﬂag bit INTF

(INTCON<1>) is set. This interrupt can be enabled/dis-

abled by setting/clearing enable bit INTE

(INTCON<4>). The INTF bit must be cleared in soft-

ware in the interrupt service routine before re-enabling

this interrupt. The RB0/INT interrupt can wake-up the

processor from SLEEP, if bit INTE was set prior to

going into SLEEP. The status of the GIE bit decides

whether or not the processor branches to the interrupt

vector following wake-up. See Section 9.8 for details

on SLEEP and Figure 9-19 for timing of wake-up from

SLEEP through RB0/INT interrupt.

9.5.2 TMR0 INTERRUPT

An overﬂow (FFh → 00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can

be enabled/disabled by setting/clearing T0IE

(INTCON<5>) bit. For operation of the Timer0 module,

see Section 6.0.

9.5.3 PORTB INTERRUPT

An input change on any bit of PORTB<7:4> sets ﬂag bit

RBIF (INTCON<0>). The interrupt can be enabled/dis-

abled by setting/clearing enable bit RBIE

(INTCON<4>). For operation of PORTB (Section 5.2).

9.5.4 COMPARATOR INTERRUPT

See Section 7.6 for complete description of the com-

parator interrupt.

FIGURE 9-16: RB0/INT PIN INTERRUPT TIMING

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF ﬂag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

Interrupt Latency

PC PC+1 PC+1 0004h 0005h

Inst (0004h) Inst (0005h)

Dummy Cycle

Inst (PC) Inst (PC+1)

Inst (PC-1) Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF ﬂag is sampled here (every Q1).

2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in RC oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

PIC16C64X & PIC16C66X

DS30559A-page 68 Preliminary  1996 Microchip Technology Inc.

9.6 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. T ypically, users may wish to save key reg-

isters during an interrupt e.g. W register and STATUS

Example 9-1 stores and restores the STATUS and W

registers. The user register, W_TEMP, must be deﬁned

in both banks and must be deﬁned at the same offset

from the bank base address (i.e., W_TEMP is deﬁned

at 0x70 - 0x7F in Bank 0). The user register,

STATUS_TEMP, must be deﬁned in Bank 0.

Example 9-1:

• Stores the W register regardless of current bank

• Stores the STATUS register in Bank 0

• Executes the ISR code

• Restores the STATUS (and bank select bit

• Restores the W register

EXAMPLE 9-1: SAVING THE STATUS AND W REGISTERS IN RAM

MOVWF W_TEMP ; Copy W to a Temporary Register regardless of current bank

SWAPF STATUS,W ; Swap STATUS nibbles and place into W register

BCF STATUS,RP0 ; Change to Bank 0 regardless of current bank

MOVWF STATUS_TEMP ; Save STATUS to a Temporary register in Bank 0

: (Interrupt Service Routine)

SWAPF STATUS_TEMP,W ; Swap original STATUS register value into W (restores original bank)

MOVWF STATUS ; Restore STATUS register from W register

SWAPF W_TEMP,F ; Swap W_Temp nibbles and return value to W_Temp

SWAPF W_TEMP,W ; Swap W_Temp to W to restore original W value without affecting STATUS

 1996 Microchip Technology Inc. Preliminary DS30559A-page 69

PIC16C64X & PIC16C66X

9.7 Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator which does not require any external com-

ponents. The block diagram is shown in Figure 9-17.

This RC oscillator is separate from the RC oscillator of

the OSC1/CLKIN pin. This means that the WDT will

run, even if the clock on the OSC1 and OSC2 pins has

been stopped, for example, by execution of a SLEEP

instruction. During normal operation, a WDT time-out

generates a device RESET. If the device is in SLEEP

mode, a WDT time-out causes the device to wake-up

and continue with normal operation, this is known as a

WDT wake-up. The WDT can be permanently disabled

by clearing conﬁguration bit WDTE (Section 9.1).

9.7.1 WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). The time-out period varies with temper-

ature, VDD and process variations from part to part (see

DC specs). If longer time-outs are desired, a prescaler

with a division ratio of up to 1:128 can be assigned to

the WDT, under software control, by writing to the

OPTION register. Thus, time-out periods of up to 2.3

seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT and

the postscaler (if assigned to the WDT) and prevent it

from timing out and generating a device RESET.

The TO bit in the STA TUS register will be cleared upon

a Watchdog Timer time-out (WDT Reset and WDT

wake-up).

9.7.2 WDT PROGRAMMING CONSIDERATIONS

It should also be taken in account that under worst case

conditions (VDD = Min., Temperature = Max., max.

WDT prescaler) it may take several seconds before a

WDT time-out occurs.

Note: When the prescaler is assigned to the

WDT, always execute a CLRWDT instruction

before changing the prescale value, other-

wise a WDT reset may occur.

FIGURE 9-17: WATCHDOG TIMER BLOCK DIAGRAM

FIGURE 9-18: SUMMARY OF WATCHDOG TIMER REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2007h Conﬁg. bits MPEEN BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0

81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

Legend: Shaded cells are not used by the Watchdog Timer.

Note 1: See Figure 9-1 for details of the operation of these bits.

From TMR0 Clock Source

(Figure 7-6)

To TMR0 (Figure 7-6)

Postscaler

WDT Timer

WDT

Enable Bit

PSA

8 - to - 1 MUX PS2:PS0

MUX PSA

WDT

Time-out

Note: PSA and PS2:PS0 are bits in the OPTION register.

PIC16C64X & PIC16C66X

DS30559A-page 70 Preliminary  1996 Microchip Technology Inc.

9.8 Power-Down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit in the STATUS register is

cleared, the TO bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had,

before the SLEEP instruction was executed (driving

high, low, or hi-impedance).

For lowest current consumption in this mode, all I/O

pins should be either at VDD, or VSS, with no external

circuitry drawing current from the I/O pin and the com-

parators and VREF module should be disabled. I/O pins

that are hi-impedance inputs should be pulled high or

low externally to avoid switching currents caused by

ﬂoating inputs. The T0CKI input should also be at VDD

or VSS for lowest current consumption. The contribu-

tion from on chip pull-ups on PORTB should be consid-

ered.

The MCLR pin must be at a logic high level (VIHMC).

9.8.1 WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

1. Any device reset

2. W atchdog T imer Wake-up (if WDT was enabled)

3. Interrupt from RB0/INT pin, RB Port change, or

the Comparator.

The ﬁrst event will reset the device upon wake-up.

However the latter two events will wake the device and

then resume program execution. The TO and PD bits in

the STATUS register can be used to determine the

cause of device reset. The PD bit, which is set on

power-up is cleared when SLEEP is invoked. The TO

bit is cleared if WDT wake-up occurred.

When the SLEEP instruction is being executed, the

next instruction (PC + 1) is pre-fetched. For the device

to wake-up through an interrupt event, the correspond-

ing interrupt enable bit must be set (enabled). W ake-up

is regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have an NOP after the SLEEP instruction.

9.8.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt ﬂag set, one of the following events will

occur:

• If the interrupt occurs before the execution of a

SLEEP instruction, the SLEEP instruction will com-

plete as an NOP. Therefore, the WDT and WDT

postscaler will not be cleared, the TO bit will not

be set and PD bit will not be cleared.

• If the interrupt occurs during or after the execution

of a SLEEP instruction, the device will immediately

wake-up from sleep. The SLEEP instruction will be

completely executed before the wake-up. There-

fore, the WDT and WDT postscaler will be

cleared, the TO bit will be set and the PD bit will

be cleared.

Even if the ﬂag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as an NOP.

To ensure that the WDT is clear, a CLRWDT instruction

should be executed before a SLEEP instruction.

FIGURE 9-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF ﬂag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

TOST(2)

PC+2

Note 1: XT, HS or LP oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.

3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.

4: CLKOUT is not available in these osc modes, but shown here for timing reference.

 1996 Microchip Technology Inc. Preliminary DS30559A-page 71

PIC16C64X & PIC16C66X

9.9 Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out for veriﬁcation purposes.

9.10 ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code-identiﬁcation numbers. These locations are

not accessible during normal execution but are

readable and writable during program/verify. Only the

least signiﬁcant 4 bits of the ID locations are used.

Note: Microchip does not recommend code

protecting windowed devices.

9.11 In-Circuit Serial Programming

The PIC16CXX microcontrollers can be serially

programmed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground, and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent ﬁrmware or a custom

ﬁrmware to be programmed.

The device is placed into a program/verify mode by

holding the RB6 and RB7 pins low while raising the

MCLR (VPP) pin from VIL to VIHH (see programming

speciﬁcation). RB6 becomes the programming clock

and RB7 becomes the programming data. Both RB6

and RB7 are Schmitt Trigger inputs in this mode.

After reset, to place the device into programming/verify

mode, the program counter (PC) is at location 00h. A

6-bit command is then supplied to the device.

Depending on the command, 14-bits of program data

are then supplied to or from the device, depending if

the command was a load or a read. For complete

details of serial programming, please refer to the

PIC16C6X/7X Programming Speciﬁcations (Literature

#DS30228).

A typical in-circuit serial programming connection is

shown in Figure 9-20.

FIGURE 9-20: TYPICAL IN-CIRCUIT SERIAL

PROGRAMMING

CONNECTION

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC16CXX

VDD

VSS

MCLR/VPP

RB6

RB7

+5V

VPP

CLK

Data I/O

VDD

PIC16C64X & PIC16C66X

DS30559A-page 72 Preliminary  1996 Microchip Technology Inc.

NOTES:



1996 Microchip Technology Inc. DS30559A-page 73

PIC16C64X & PIC16C66X

10.0 INSTRUCTION SET SUMMARY

Each PIC16CXX instruction is a 14-bit word divided

into an OPCODE which speciﬁes the instruction type

and one or more operands which further specify the

operation of the instruction. The PIC16CXX instruction

set summary in Table 10-2 lists

byte-oriented

bit-ori-

ented

, and

literal and control

operations. Table 10-1

shows the opcode ﬁeld descriptions.

For

byte-oriented

instructions, 'f' represents a ﬁle reg-

ister designator and 'd' represents a destination desig-

nator. The ﬁle register designator speciﬁes which ﬁle

The destination designator speciﬁes where the result of

the operation is to be placed. If 'd' is zero, the result is

placed in the W register . If 'd' is one, the result is placed

in the ﬁle register speciﬁed in the instruction.

For

bit-oriented

instructions, 'b' represents a bit ﬁeld

designator which selects the number of the bit affected

by the operation, while 'f' represents the number of the

ﬁle in which the bit is located.

For

literal and control

operations, 'k' represents an

eight or eleven bit constant or literal value.

TABLE 10-1: OPCODE FIELD

DESCRIPTIONS

The instruction set is highly orthogonal and is grouped

into three basic categories:

Field Description

Working register (accumulator)

Bit address within an 8-bit ﬁle register

Literal ﬁeld, constant data or label

Don't care location (= 0 or 1)

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

Microchip software tools.

Destination select; d = 0: store result in W,

d = 1: store result in ﬁle register f.

Default is d = 1

label

Label name

TOS

Top of Stack

Program Counter

PCLATH

Program Counter High Latch

GIE

Global Interrupt Enable bit

WDT

W atchdog Timer/Counter

Time-out bit

Power-down bit

dest

Destination either the W register or the speciﬁed

[ ] Options

( )

Contents

→

Assigned to

< >

∈

In the set of

talics

User deﬁned term (font is courier)

•

Byte-oriented

operations

•

Bit-oriented

operations

•

Literal and control

operations

All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the pro-

gram counter is changed as a result of an instruction.

In this case, the execution takes two instruction cycles

with the second cycle executed as a NOP. One instruc-

tion cycle consists of four oscillator periods. Thus, for

an oscillator frequency of 4 MHz, the normal instruction

execution time is 1

s. If a conditional test is true or the

program counter is changed as a result of an instruc-

tion, the instruction execution time is 2

Table 10-2 lists the instructions recognized by the

MPASM assembler.

Figure 10-1 shows the three general formats that the

instructions can have.

All examples use the following format to represent a

hexadecimal number:

0xhh

where h signiﬁes a hexadecimal digit.

FIGURE 10-1: GENERAL FORMAT FOR

INSTRUCTIONS

Note:

To maintain upward compatibility with

future PIC16CXX products, do not use the

OPTION

and

TRIS

instructions.

Byte-oriented ﬁle register operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 7-bit ﬁle register address

Bit-oriented ﬁle register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 7-bit ﬁle register address

Literal and control operations

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 74



1996 Microchip Technology Inc.

10.1 Special Function Registers as

Source/Destination

The PIC16C64X & PIC16C66X’s orthogonal instruction

set allows read and write of all ﬁle registers, including

special function registers. There are some special situ-

ations the user should be aware of:

10.1.1 STATUS AS DESTINATION

If an instruction writes to ST A TUS, the Z, C, and DC bits

may be set or cleared as a result of the instruction and

overwrite the original data bits written. For example,

executing

CLRF STATUS

will clear register STATUS,

and then set the Z bit leaving

0000 0100b

in the reg-

ister.

10.1.2 PCL AS SOURCE OR DESTINATION

Read, write or read-modify-write on PCL may have the

following results:

Read PC: PCL

→

dest

Write PCL: PCLATH

→

PCH;

8-bit destination value

→

PCL

Read-Modify-Write: PCL

→

ALU operand

PCLA TH

→

PCH;

8-bit result

→

PCL

Where PCH = program counter high byte (not an

addressable register), PCLATH = Program counter

high holding latch, dest = destination, WREG or f.

10.1.3 BIT MANIPULATION

All bit manipulation instructions are done by ﬁrst read-

ing the entire register , operating on the selected bit and

writing the result back (read-modify-write). The user

should keep this in mind when operating on special

function registers, such as ports.



1996 Microchip Technology Inc. DS30559A-page 75

PIC16C64X & PIC16C66X

TABLE 10-2: INSTRUCTION SET

Mnemonic,

Operands Description Cycles 14-Bit Opcode Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0000

dfff

lfff

0xx0

dfff

ffff

0011

ffff

0000

ffff

C,DC,Z

1,2

1,2,3

1,2

1,2,3

1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

00bb

01bb

10bb

11bb

bfff

ffff

1,2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into standby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

Note 1: When an I/O register is modiﬁed as a function of itself ( e.g.,

MOVF PORTB, 1

), the value used will be that value present

on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven low by an external

device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned

to the Timer0 Module.

3: If Program Counter (PC) is modiﬁed or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

PIC16C64X & PIC16C66X

DS30559A-page 76



1996 Microchip Technology Inc.

10.2 Instruction Descriptions

ADDLW Add Literal and W

Syntax: [

label

] ADDLW k

Operands: 0

≤

255

Operation: (W) + k

→

(W)

Status Affected: C, DC, Z

Encoding:

11 111x kkkk kkkk

Description:

The contents of the W register are

added to the eight bit literal 'k' and the

result is placed in the W register

Words: 1

Cycles: 1

Example

ADDLW 0x15

Before Instruction

W = 0x10

After Instruction

W = 0x25

ADDWF Add W and f

Syntax: [

label

] ADDWF f,d

Operands: 0

≤

127

∈ [0,1]

Operation: (W) + (f)

→

(dest)

Status Affected: C, DC, Z

Encoding:

00 0111 dfff ffff

Description:

Add the contents of the W register

with register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'

Words: 1

Cycles: 1

Example

ADDWF FSR, 0

Before Instruction

W = 0x17

FSR = 0xC2

After Instruction

W = 0xD9

FSR = 0xC2

ANDLW And Literal with W

Syntax: [

label

] ANDLW k

Operands: 0

≤

255

Operation: (W) .AND. (k)

→

(W)

Status Affected: Z

Encoding:

11 1001 kkkk kkkk

Description:

The contents of W register are

AND’ed with the eight bit literal 'k'. The

result is placed in the W register

Words: 1

Cycles: 1

Example

ANDLW 0x5F

Before Instruction

W = 0xA3

After Instruction

W = 0x03

ANDWF AND W with f

Syntax: [

label

] ANDWF f,d

Operands: 0

≤

127

∈ [0,1]

Operation: (W) .AND. (f)

→

(dest)

Status Affected: Z

Encoding:

00 0101 dfff ffff

Description:

AND the W register with register 'f'. If

'd' is 0 the result is stored in the W

back in register 'f'

Words: 1

Cycles: 1

Example ANDWF FSR, 1

Before Instruction

W = 0x17

FSR = 0xC2

After Instruction

W = 0x17

FSR = 0x02

 1996 Microchip Technology Inc. DS30559A-page 77

PIC16C64X & PIC16C66X

BCF Bit Clear f

Syntax: [

label

] BCF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

Status Affected: None

Encoding: 01 00bb bfff ffff

Description: Bit 'b' in register 'f' is cleared.

Words: 1

Cycles: 1

Example BCF FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

BSF Bit Set f

Syntax: [

label

] BSF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

Status Affected: None

Encoding: 01 01bb bfff ffff

Description: Bit 'b' in register 'f' is set.

Words: 1

Cycles: 1

Example BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC Bit Test, Skip if Clear

Syntax: [

label

] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

Status Affected: None

Encoding: 01 10bb bfff ffff

Description: If bit 'b' in register 'f' is '0' then the next

instruction is skipped.

If bit 'b' is '0' then the next instruction

fetched during the current instruction

execution is discarded, and a NOP is

executed instead, making this a 2 cycle

instruction.

Words: 1

Cycles: 1(2)

Example HERE

FALSE

TRUE

BTFSC

GOTO

•

FLAG,1

PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0,

PC = address TRUE

if FLAG<1>=1,

PC = address FALSE

PIC16C64X & PIC16C66X

DS30559A-page 78  1996 Microchip Technology Inc.

BTFSS Bit Test f, Skip if Set

Syntax: [

label

] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Encoding: 01 11bb bfff ffff

Description: If bit 'b' in register 'f' is '1' then the next

instruction is skipped.

If bit 'b' is '1', then the next instruction

fetched during the current instruction

execution, is discarded and a NOP is

executed instead, making this a 2 cycle

instruction.

Words: 1

Cycles: 1(2)

Example HERE

FALSE

TRUE

BTFSC

GOTO

•

FLAG,1

PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0,

PC = address FALSE

if FLAG<1> = 1,

PC = address TRUE

CALL Call Subroutine

Syntax: [

label

] CALL k

Operands: 0 ≤ k ≤ 2047

Operation: (PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Status Affected: None

Encoding: 10 0kkk kkkk kkkk

Description: Call Subroutine. First, return address

(PC+1) is pushed onto the stack. The

eleven bit immediate address is loaded

into PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALL is a two cycle instruction.

Words: 1

Cycles: 2

Example HERE CALL THERE

Before Instruction

PC = Address HERE

After Instruction

PC = Address THERE

TOS= Address HERE+1

CLRF Clear f

Syntax: [

label

] CLRF f

Operands: 0 ≤ f ≤ 127

Operation: 00h → (f)

1 → Z

Status Affected: Z

Encoding: 00 0001 1fff ffff

Description: The contents of register 'f' are cleared

and the Z bit is set.

Words: 1

Cycles: 1

Example CLRF FLAG_REG

Before Instruction

FLAG_REG = 0x5A

After Instruction

FLAG_REG = 0x00

Z=1

CLRW Clear W

Syntax: [

label

] CLRW

Operands: None

Operation: 00h → (W)

1 → Z

Status Affected: Z

Encoding: 00 0001 0000 0011

Description: W register is cleared. Zero bit (Z) is

set.

Words: 1

Cycles: 1

Example CLRW

Before Instruction

W = 0x5A

After Instruction

W = 0x00

Z=1

 1996 Microchip Technology Inc. DS30559A-page 79

PIC16C64X & PIC16C66X

CLRWDT Clear Watchdog Timer

Syntax: [

label

] CLRWDT

Operands: None

Operation: 00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

Status Affected: TO, PD

Encoding: 00 0000 0110 0100

Description: CLRWDT instruction resets the Watch-

dog Timer. It also resets the prescaler

of the WDT. Status bits TO and PD

are set.

Words: 1

Cycles: 1

Example CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT counter = 0x00

WDT prescaler= 0

TO =1

PD =1

COMF Complement f

Syntax: [

label

] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 00 1001 dfff ffff

Description: The contents of register 'f' are comple-

mented. If 'd' is 0 the result is stored in

W . If 'd' is 1 the result is stored back in

Words: 1

Cycles: 1

Example COMF REG1,0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13

W = 0xEC

DECF Decrement f

Syntax: [

label

] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (dest)

Status Affected: Z

Encoding: 00 0011 dfff ffff

Description: Decrement register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Words: 1

Cycles: 1

Example DECF CNT, 1

Before Instruction

CNT = 0x01

Z=0

After Instruction

CNT = 0x00

Z=1

DECFSZ Decrement f, Skip if 0

Syntax: [

label

] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (dest); skip if result = 0

Status Affected: None

Encoding: 00 1011 dfff ffff

Description: The contents of register 'f' are decre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded. A

NOP is executed instead making it a two

cycle instruction.

Words: 1

Cycles: 1(2)

Example HERE DECFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT - 1

if CNT = 0,

PC = address CONTINUE

if CNT ≠0,

PC = address HERE+1

PIC16C64X & PIC16C66X

DS30559A-page 80  1996 Microchip Technology Inc.

GOTO Unconditional Branch

Syntax: [

label

] GOTO k

Operands: 0 ≤ k ≤ 2047

Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11>

Status Affected: None

Encoding: 10 1kkk kkkk kkkk

Description: GOTO is an unconditional branch. The

eleven bit immediate value is loaded

into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTO is a two cycle instruction.

Words: 1

Cycles: 2

Example GOTO THERE

After Instruction

PC = Address THERE

INCF Increment f

Syntax: [

label

] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (dest)

Status Affected: Z

Encoding: 00 1010 dfff ffff

Description: The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed

in the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1

Cycles: 1

Example INCF CNT, 1

Before Instruction

CNT = 0xFF

Z=0

After Instruction

CNT = 0x00

Z=1

INCFSZ Increment f, Skip if 0

Syntax: [

label

] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (dest), skip if result = 0

Status Affected: None

Encoding: 00 1111 dfff ffff

Description: The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed

in the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded.

A NOP is executed instead making it a

two cycle instruction.

Words: 1

Cycles: 1(2)

Example HERE INCFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT + 1

if CNT= 0,

PC = address CONTINUE

if CNT≠0,

PC = address HERE +1

IORLW Inclusive OR Literal with W

Syntax: [

label

] IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. k → (W)

Status Affected: Z

Encoding: 11 1000 kkkk kkkk

Description: The contents of the W register is

OR’ed with the eight bit literal 'k'. The

result is placed in the W register.

Words: 1

Cycles: 1

Example IORLW 0x35

Before Instruction

W = 0x9A

After Instruction

W = 0xBF

Z=1

 1996 Microchip Technology Inc. DS30559A-page 81

PIC16C64X & PIC16C66X

IORWF Inclusive OR W with f

Syntax: [

label

] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .OR. (f) → (dest)

Status Affected: Z

Encoding: 00 0100 dfff ffff

Description: Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1

Cycles: 1

Example IORWF RESULT, 0

Before Instruction

RESULT = 0x13

W = 0x91

After Instruction

RESULT = 0x13

W = 0x93

Z=1

MOVLW Move Literal to W

Syntax: [

label

] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

Status Affected: None

Encoding: 11 00xx kkkk kkkk

Description: The eight bit literal 'k' is loaded into W

as 0’s.

Words: 1

Cycles: 1

Example MOVLW 0x5A

After Instruction

W = 0x5A

MOVF Move f

Syntax: [

label

] MOVF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 00 1000 dfff ffff

Description: The contents of register f is moved to

a destination dependant upon the sta-

tus of d. If d = 0, destination is W reg-

ister. If d = 1, the destination is ﬁle

ﬁle register since status ﬂag Z is

affected.

Words: 1

Cycles: 1

Example MOVF FSR, 0

After Instruction

W = value in FSR register

Z= 1

MOVWF Move W to f

Syntax: [

label

] MOVWF f

Operands: 0 ≤ f ≤ 127

Operation: (W) → (f)

Status Affected: None

Encoding: 00 0000 1fff ffff

Description: Move data from W register to register

'f'.

Words: 1

Cycles: 1

Example MOVWF OPTION

Before Instruction

OPTION = 0xFF

W = 0x4F

After Instruction

OPTION = 0x4F

W = 0x4F

PIC16C64X & PIC16C66X

DS30559A-page 82  1996 Microchip Technology Inc.

NOP No Operation

Syntax: [

label

] NOP

Operands: None

Operation: No operation

Status Affected: None

Encoding: 00 0000 0xx0 0000

Description: No operation.

Words: 1

Cycles: 1

Example NOP

OPTION Load Option Register

Syntax: [

label

] OPTION

Operands: None

Operation: (W) → OPTION

Status Affected: None

Encoding: 00 0000 0110 0010

Description: The contents of the W register are

loaded in the OPTION register. This

instruction is supported for code com-

patibility with PIC16C5X products.

Since OPTION is a readable/writable

it.

Words: 1

Cycles: 1

Example To maintain upward compatibility

with future PIC16CXX products, do

not use this instruction.

RETFIE Return from Interrupt

Syntax: [

label

] RETFIE

Operands: None

Operation: TOS → PC,

1 → GIE

Status Affected: None

Encoding: 00 0000 0000 1001

Description: Return from Interrupt. Stack is POPed

and Top of Stack (TOS) is loaded in

the PC. Interrupts are enabled by set-

ting Global Interrupt Enable bit, GIE

(INTCON<7>). This is a two cycle

instruction.

Words: 1

Cycles: 2

Example RETFIE

After Interrupt

PC = TOS

GIE = 1

RETLW Return with Literal in W

Syntax: [

label

] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

Status Affected: None

Encoding: 11 01xx kkkk kkkk

Description: The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Words: 1

Cycles: 2

Example

TABLE

CALL TABLE ;W contains table

;offset value

• ;W now has table value

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

 1996 Microchip Technology Inc. DS30559A-page 83

PIC16C64X & PIC16C66X

RETURN Return from Subroutine

Syntax: [

label

] RETURN

Operands: None

Operation: TOS → PC

Status Affected: None

Encoding: 00 0000 0000 1000

Description: Return from subroutine. The stack is

POPed and the top of the stack (TOS)

is loaded into the program counter.

This is a two cycle instruction.

Words: 1

Cycles: 2

Example RETURN

After Interrupt

PC = TOS

RLF Rotate Left f through Carry

Syntax: [

label

] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 00 1101 dfff ffff

Description: The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

stored back in register 'f'.

Words: 1

Cycles: 1

Example RLF REG1,0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W= 1100 1100

C=1

RRF Rotate Right f through Carry

Syntax: [

label

] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 00 1100 dfff ffff

Description: The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1

Cycles: 1

Example RRF REG1,0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W= 0111 0011

C=0

SLEEP

Syntax: [

label

] SLEEP

Operands: None

Operation: 00h → WDT,

0 → WDT prescaler,

1 → TO,

0 → PD

Status Affected: TO, PD

Encoding: 00 0000 0110 0011

Description: The power-down status bit, PD is

cleared. Time-out status bit, TO is

set. Watchdog Timer and its pres-

caler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped.

See Power-Down Mode (SLEEP) for

more details.

Words: 1

Cycles: 1

Example: SLEEP

PIC16C64X & PIC16C66X

DS30559A-page 84  1996 Microchip Technology Inc.

SUBLW Subtract W from Literal

Syntax: [

label

] SUBLW k

Operands: 0 ≤ k ≤ 255

Operation: k - (W) → (W)

Status

Affected: C, DC, Z

Encoding: 11 110x kkkk kkkk

Description: The W register is subtracted (2’s com-

plement method) from the eight bit literal

'k'. The result is placed in the W register.

Words: 1

Cycles: 1

Example 1: SUBLW 0x02

Before Instruction

W= 1

C=?

After Instruction

W= 1

C = 1; result is positive

Example 2: Before Instruction

W= 2

C=?

After Instruction

W= 0

C = 1; result is zero

Example 3: Before Instruction

W= 3

C=?

After Instruction

W = 0xFF

C = 0; result is nega-

tive

SUBWF Subtract W from f

Syntax: [

label

] SUBWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - (W) → (dest)

Status

Affected: C, DC, Z

Encoding: 00 0010 dfff ffff

Description: Subtract (2’s complement method) W reg-

ister from register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'.

Words: 1

Cycles: 1

Example 1: SUBWF REG1,1

Before Instruction

REG1 = 3

W=2

C=?

After Instruction

REG1 = 1

W=2

C = 1; result is positive

Example 2: Before Instruction

REG1 = 2

W=2

C=?

After Instruction

REG1 = 0

W=2

C = 1; result is zero

Example 3: Before Instruction

REG1 = 1

W=2

C=?

After Instruction

REG1 = 0xFF

W=2

C = 0; result is negative

 1996 Microchip Technology Inc. DS30559A-page 85

PIC16C64X & PIC16C66X

SWAPF Swap Nibbles in f

Syntax: [

label

] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>),

(f<7:4>) → (dest<3:0>)

Status Affected: None

Encoding: 00 1110 dfff ffff

Description: The upper and lower nibbles of regis-

ter 'f' are exchanged. If 'd' is 0 the

result is placed in W register. If 'd' is 1

the result is placed in register 'f'.

Words: 1

Cycles: 1

Example SWAPF REG, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5

W = 0x5A

TRIS Load TRIS Register

Syntax: [

label

] TRIS f

Operands: 5 ≤ f ≤ 7

Operation: (W) → TRIS register f;

Status Affected: None

Encoding: 00 0000 0110 0fff

Description: The instruction is supported for code

compatibility with the PIC16C5X prod-

ucts. Since TRIS registers are read-

able and writable, the user can directly

address them.

Words: 1

Cycles: 1

Example To maintain upward compatibility

with future PIC16CXX products, do

not use this instruction.

XORLW Exclusive OR Literal with W

Syntax: [

label

] XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W)

Status Affected: Z

Encoding: 11 1010 kkkk kkkk

Description: The contents of the W register are

XOR’ed with the eight bit literal 'k'.

The result is placed in the W regis-

ter.

Words: 1

Cycles: 1

Example: XORLW 0xAF

Before Instruction

W = 0xB5

After Instruction

W = 0x1A

XORWF Exclusive OR W with f

Syntax: [

label

] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .XOR. (f) → (dest)

Status Affected: Z

Encoding: 00 0110 dfff ffff

Description: Exclusive OR the contents of the W

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Words: 1

Cycles: 1

Example XORWF REG 1

Before Instruction

REG = 0xAF

W = 0xB5

After Instruction

REG = 0x1A

W = 0xB5

PIC16C64X & PIC16C66X

DS30559A-page 86  1996 Microchip Technology Inc.

NOTES:



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 87

PIC16C64X & PIC16C66X

11.0 DEVELOPMENT SUPPORT

11.1 Development Tools

The PIC16/17 microcontrollers are supported with a full

range of hardware and software development tools:

• PICMASTER/PICMASTER CE

Real-Time

In-Circuit Emulator

• ICEPIC Low-Cost PIC16C5X and PIC16CXX

In-Circuit Emulator

• PRO MATE



II Universal Programmer

• PICSTART



Plus Entry-Level Prototype

Programmer

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MP ASM Assembler

• MPLAB-SIM Software Simulator

• MPLAB-C (C Compiler)

• Fuzzy logic development system (fuzzyTECH



−

MP)

11.2 PICMASTER: High Performance

Universal In-Circuit Emulator with

MPLAB IDE

The PICMASTER Universal In-Circuit Emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for all

microcontrollers in the PIC12C5XX, PIC14000,

PIC16C5X, PIC16CXX and PIC17CXX families.

PICMASTER is supplied with the MPLAB



Integrated

Development Environment (IDE), which allows editing,

“make” and download, and source debugging from a

single environment.

Interchangeable target probes allow the system to be

easily reconﬁgured for emulation of different proces-

sors. The universal architecture of the PICMASTER

allows expansion to support all new Microchip micro-

controllers.

The PICMASTER Emulator System has been designed

as a real-time emulation system with advanced fea-

tures that are generally found on more expensive devel-

opment tools. The PC compatible 386 (and higher)

machine platform and Microsoft Windows



3.x environ-

ment were chosen to best make these features avail-

able to you, the end user.

A CE compliant version of PICMASTER is available for

European Union (EU) countries.

11.3 ICEPIC: Low-cost PIC16CXX In-Circuit

Emulator

ICEPIC is a low-cost in-circuit emulator solution for the

Microchip PIC16C5X and PIC16CXX families of 8-bit

OTP microcontrollers.

ICEPIC is designed to operate on PC-compatible

machines ranging from 286-AT



through Pentium



based machines under Windows 3.x environment.

ICEPIC features real time, non-intrusive emulation.

11.4 PRO MATE II: Universal Programmer

The PRO MATE II Universal Programmer is a full-fea-

tured programmer capable of operating in stand-alone

mode as well as PC-hosted mode.

The PRO MATE II has programmable V

and V

supplies which allows it to verify programmed memory

at V

min and V

max for maximum reliability. It has

an LCD display for displaying error messages, keys to

enter commands and a modular detachable socket

assembly to support various package types. In stand-

alone mode the PRO MATE II can read, verify or pro-

gram PIC16C5X, PIC16CXX, PIC17CXX and

PIC14000 devices. It can also set conﬁguration and

code-protect bits in this mode.

11.5 PICSTART Plus Entry Level

Development System

The PICSTART programmer is an easy-to-use, low-

cost prototype programmer. It connects to the PC via

one of the COM (RS-232) ports. MPLAB Integrated

Development Environment software makes using the

programmer simple and efﬁcient. PICST ART Plus is not

recommended for production programming.

PICSTART Plus supports all PIC12C5XX, PIC14000,

PIC16C5X, PIC16CXX and PIC17CXX devices with up

to 40 pins. Larger pin count devices such as the

PIC16C923 and PIC16C924 may be supported with an

adapter socket.

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 88

Preliminary



1996 Microchip Technology Inc.

11.6 PICDEM-1 Low-Cost PIC16/17

Demonstration Board

The PICDEM-1 is a simple board which demonstrates

the capabilities of several of Microchip’s microcontrol-

lers. The microcontrollers supported are: PIC16C5X

(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,

PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and

PIC17C44. All necessary hardware and software is

included to run basic demo programs. The users can

program the sample microcontrollers provided with

the PICDEM-1 board, on a PRO MATE II or

PICSTART-16B programmer, and easily test ﬁrm-

ware. The user can also connect the PICDEM-1

board to the PICMASTER emulator and download

the ﬁrmware to the emulator for testing. Additional pro-

totype area is available for the user to build some addi-

tional hardware and connect it to the microcontroller

socket(s). Some of the features include an RS-232

interface, a potentiometer for simulated analog input,

push-button switches and eight LEDs connected to

PORTB.

11.7 PICDEM-2

Low-Cost PIC16CXX

Demonstration Board

The PICDEM-2 is a simple demonstration board that

supports the PIC16C62, PIC16C64, PIC16C65,

PIC16C73 and PIC16C74 microcontrollers. All the

necessary hardware and software is included to

run the basic demonstration programs. The user

can program the sample microcontrollers provided

with the PICDEM-2 board, on a PRO MATE II pro-

grammer or PICSTART-16C, and easily test ﬁrmware.

The PICMASTER emulator may also be used with the

PICDEM-2 board to test ﬁrmware. Additional prototype

area has been provided to the user for adding addi-

tional hardware and connecting it to the microcontroller

socket(s). Some of the features include a RS-232 inter-

face, push-button switches, a potentiometer for simu-

lated analog input, a Serial EEPROM to demonstrate

usage of the I

C bus and separate headers for connec-

tion to an LCD module and a keypad.

11.8 PICDEM-3 Low-Cost PIC16CXX

Demonstration Board

The PICDEM-3 is a simple demonstration board that

supports the PIC16C923 and PIC16C924 in the PLCC

package. It will also support future 44-pin PLCC

microcontrollers with a LCD Module. All the neces-

sary hardware and software is included to run the

basic demonstration programs. The user can pro-

gram the sample microcontrollers provided with

the PICDEM-3 board, on a PRO MATE II program-

mer or PICSTART Plus with an adapter socket, and

easily test ﬁrmware. The PICMASTER emulator may

also be used with the PICDEM-3 board to test ﬁrm-

ware. Additional prototype area has been provided to

the user for adding hardware and connecting it to the

microcontroller socket(s). Some of the features include

an RS-232 interface, push-button switches, a potenti-

ometer for simulated analog input, a thermistor and

separate headers for connection to an external LCD

module and a keypad. Also provided on the PICDEM-3

board is an LCD panel, with 4 commons and 12 seg-

ments, that is capable of displaying time, temperature

and day of the week. The PICDEM-3 provides an addi-

tional RS-232 interface and Windows 3.1 software for

showing the demultiplexed LCD signals on a PC. A

simple serial interface allows the user to construct a

hardware demultiplexer for the LCD signals. PICDEM-

3 will be available in the 3rd quarter of 1996.

11.9 MPLAB Integrated Development

Environment Software

The MPLAB IDE Software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. MPLAB is a windows based application

which contains:

• A full featured editor

• Three operating modes

- editor

- emulator

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

MPLAB allows you to:

• Edit your source ﬁles (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PIC16/17 tools (automatically updates all

project information)

• Debug using:

- source ﬁles

- absolute listing ﬁle

• Transfer data dynamically via DDE (soon to be

replaced by OLE)

• Run up to four emulators on the same PC

The ability to use MPLAB with Microchip’s simulator

allows a consistent platform and the ability to easily

switch from the low cost simulator to the full featured

emulator with minimal retraining due to development

tools.

11.10 Assembler (MPASM)

The MPASM Universal Macro Assembler is a PC-

hosted symbolic assembler. It supports all microcon-

troller series including the PIC12C5XX, PIC14000,

PIC16C5X, PIC16CXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, condi-

tional assembly , and several source and listing formats.

It generates various object code formats to support

Microchip's development tools as well as third party

programmers.



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 89

PIC16C64X & PIC16C66X

MPASM allows full symbolic debugging from

the Microchip Universal Emulator System

(PICMASTER).

MPASM has the following features to assist in develop-

ing software for speciﬁc use applications.

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the ﬁles (Object, Listing, Symbol,

and special) required for symbolic debug with

Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source

and listing formats.

MPASM provides a rich directive language to support

programming of the PIC16/17. Directives are helpful in

making the development of your assemble source code

shorter and more maintainable.

11.11 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code

development in a PC host environment. It allows the

user to simulate the PIC16/17 series microcontrollers

on an instruction level. On any given instruction, the

user may examine or modify any of the data areas or

provide external stimulus to any of the pins. The input/

output radix can be set by the user and the execution

can be performed in; single step, execute until break, or

in a trace mode.

MPLAB-SIM fully supports symbolic debugging using

MPLAB-C and MPASM. The Software Simulator offers

the low cost ﬂexibility to develop and debug code out-

side of the laboratory environment making it an excel-

lent multi-project software development tool.

11.12 C Compiler (MPLAB-C)

The MPLAB-C Code Development System is a com-

plete ‘C’ compiler and integrated development environ-

ment for Microchip’s PIC16/17 family of

microcontrollers. The compiler provides powerful inte-

gration capabilities and ease of use not found with

other compilers.

For easier source level debugging, the compiler pro-

vides symbol information that is compatible with the

MPLAB IDE memory display (PICMASTER emulator

software versions 1.13 and later).

11.13 Fuzzy Logic Development System

(

fuzzy

TECH-MP)

fuzzy

TECH-MP fuzzy logic development tool is avail-

able in two versions - a low cost introductory version,

MP Explorer, for designers to gain a comprehensive

working knowledge of fuzzy logic system design; and a

full-featured version,

fuzzy

TECH-MP, edition for imple-

menting more complex systems.

Both versions include Microchip’s

fuzzy

LAB



demon-

stration board for hands-on experience with fuzzy logic

systems implementation.

11.14 MP-DriveWay



– Application Code

Generator

MP-DriveW ay is an easy-to-use Windows-based Appli-

cation Code Generator. With MP-DriveWay you can

visually conﬁgure all the peripherals in a PIC16/17

device and, with a click of the mouse, generate all the

initialization and many functional code modules in C

language. The output is fully compatible with Micro-

chip’s MPLAB-C C compiler. The code produced is

highly modular and allows easy integration of your own

code. MP-DriveWay is intelligent enough to maintain

your code through subsequent code generation.

11.15 SEEVAL



Evaluation and

Programming System

The SEEVAL SEEPROM Designer’s Kit supports all

Microchip 2-wire and 3-wire Serial EEPROMs. The kit

includes everything necessary to read, write, erase or

program special features of any Microchip SEEPROM

product including Smart Serials



and secure serials.

The Total Endurance



Disk is included to aid in trade-

off analysis and reliability calculations. The total kit can

signiﬁcantly reduce time-to-market and result in an

optimized system.

11.16 TrueGauge



Intelligent Battery

Management

The TrueGauge development tool supports system

development with the MTA11200B TrueGauge Intelli-

gent Battery Management IC. System design veriﬁca-

tion can be accomplished before hardware prototypes

are built. User interface is graphically-oriented and

measured data can be saved in a ﬁle for exporting to

Microsoft Excel.

11.17 K



Evaluation and

Programming Tools

evaluation and programming tools support

Microchips HCS Secure Data Products. The HCS eval-

uation kit includes an LCD display to show changing

codes, a decoder to decode transmissions, and a pro-

gramming interface to program test transmitters.

PIC16C64X & PIC16C66X

DS30559A-page 90

Preliminary



1996 Microchip Technology Inc.

TABLE 11-1: DEVELOPMENT TOOLS FROM MICROCHIP

Product ** MPLAB



Integrated

Development

Environment

MPLAB



Compiler MP-DriveWay

Applications

Code

Generator

fuzzyTECH



-MP

Explorer/Edition

Fuzzy Logic

Dev . T ool

*** PICMASTER



PICMASTER-CE

In-Circuit

Emulator

ICEPIC

Low-Cost

In-Circuit

Emulator

****PRO MATE



II Universal

Microchip

Programmer

PICSTART



Lite

Ultra Low-Cost

Dev. Kit

PICSTART



Plus

Low-Cost

Universal

Dev. Kit

PIC12C508, 509 SW007002 SW006005 — — EM167015/

EM167101 — DV007003 — DV003001

PIC14000 SW007002 SW006005 — — EM147001/

EM147101 — DV007003 — DV003001

PIC16C52, 54, 54A,

55, 56, 57, 58A SW007002 SW006005 SW006006 DV005001/

DV005002 EM167015/

EM167101 EM167201 DV007003 DV162003 DV003001

PIC16C554, 556, 558 SW007002 SW006005 — DV005001/

DV005002 EM167033/

EM167113 —- DV007003 — DV003001

PIC16C61 SW007002 SW006005 SW006006 DV005001/

DV005002 EM167021/

N/A EM167205 DV007003 DV162003 DV003001

PIC16C62, 62A,

64, 64A SW007002 SW006005 SW006006 DV005001/

DV005002 EM167025/

EM167103 EM167203 DV007003 DV162002 DV003001

PIC16C620, 621, 622 SW007002 SW006005 SW006006 DV005001/

DV005002 EM167023/

EM167109 EM167202 DV007003 DV162003 DV003001

PIC16C63, 65, 65A,

73, 73A, 74, 74A SW007002 SW006005 SW006006 DV005001/

DV005002 EM167025/

EM167103 EM167204 DV007003 DV162002 DV003001

PIC16C641, 642, 661,

662* SW007002 SW006005 — — EM167035/

EM167105 —- DV007003 DV162002 DV003001

PIC16C71 SW007002 SW006005 SW006006 DV005001/

DV005002 EM167027/

EM167105 EM167205 DV007003 DV162003 DV003001

PIC16C710, 711 SW007002 SW006005 SW006006 DV005001/

DV005002 EM167027/

EM167105 — DV007003 DV162003 DV003001

PIC16C72 SW007002 SW006005 SW006006 — EM167025/

EM167103 — DV007003 DV162002 DV003001

PIC16F83 SW007002 SW006005 SW006006 DV005001/

DV005002 EM167029/

EM167107 — DV007003 DV162003 DV003001

PIC16C84 SW007002 SW006005 SW006006 DV005001/

DV005002 EM167029/

EM167107 EM167206 DV007003 DV162003 DV003001

PIC16F84 SW007002 SW006005 SW006006 DV005001/

DV005002 EM167029/

EM167107 — DV007003 DV162003 DV003001

PIC16C923, 924* SW007002 SW006005 SW006006 DV005001/

DV005002 EM167031/

EM167111 — DV007003 — DV003001

PIC17C42,

42A, 43, 44 SW007002 SW006005 SW006006 DV005001/

DV005002 EM177007/

EM177107 — DV007003 — DV003001

*Contact Microchip Technology for availability date

**MPLAB Integrated Development Environment includes MPLAB-SIM Simulator and

MPASM Assembler

***All PICMASTER and PICMASTER-CE ordering part numbers above include

PRO MATE II programmer

****PRO MATE socket modules are ordered separately. See development systems

ordering guide for speciﬁc ordering part numbers

Product TRUEGAUGE



Development Kit SEEVAL



Designers Kit Hopping Code Security Programmer Kit Hopping Code Security Eval/Demo Kit

All 2 wire and 3 wire

Serial EEPROM's N/A DV243001 N/A N/A

MTA11200B DV114001 N/A N/A N/A

HCS200, 300, 301 * N/A N/A PG306001 DM303001



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 91

PIC16C64X & PIC16C66X

12.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings †

Ambient Temperature under bias............................................................................................................. –40

to +125

Storage Temperature ............................................................................................................................... –65

to +150

Voltage on any pin with respect to V

(except V

and MCLR) .....................................................–0.3V to V

+ 0.3V

Voltage on V

with respect to V

................................................................................................................ 0 to +7.5V

Voltage on MCLR with respect to V

(Note 2) .................................................................................................0 to +14V

Total power Dissipation (Note 1)...............................................................................................................................1.0W

Maximum Current out of V

pin ..........................................................................................................................300 mA

Maximum Current into V

pin .............................................................................................................................250 mA

Input Clamp Current, I

<0 or V

> V

)

.......................................................................................................................±

20 mA

Output Clamp Current, I

(Vo <0 or Vo>V

)

................................................................................................................±

20 mA

Maximum Output Current sunk by any I/O pin........................................................................................................25 mA

Maximum Output Current sourced by any I/O pin...................................................................................................25 mA

Maximum current sunk by

PORTA, PORTB, and PORTE (combined) (Note 2)...................................................200 mA

Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 2)..............................................200 mA

Maximum current sunk by PORTC and PORTD (combined) (Note 2)..................................................................200 mA

Maximum current sourced by PORTC and PORTD (combined) (Note 2).............................................................200 mA

Note 1:

Power dissipation is calculated as follows: P

DIS

= V

x {I

∑

} +

∑

{(V

-V

) x I

} +

∑

l x I

)

Note 2:

PORTD and PORTE are not implemented on the PIC16C641 and PIC16C642.

TABLE 12-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

†

NOTICE

: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

OSC

PIC16C641-04

PIC16C642-04

PIC16C661-04

PIC16C662-04

PIC16C641-10

PIC16C642-10

PIC16C661-10

PIC16C662-10

PIC16C641-20

PIC16C642-20

PIC16C661-20

PIC16C662-20

PIC16LC641-04

PIC16LC642-04

PIC16LC661-04

PIC16LC662-04

JW Devices

RC V

: 4.0V to 6.0V

: 5 mA max. @ 5.5V

: 21

A max. @ 4.0V

Freq: 4.0 MHz max.

: 4.5V to 5.5V

: 2.7 mA typ. @ 5.5V

: 1.5

A typ. @ 4.0V

Freq: 4.0 MHz max.

: 4.5V to 5.5V

: 2.7 mA typ. @ 5.5V

: 1.5

A typ. @ 4.0V

Freq: 4.0 MHz max.

: 3.0V to 6.0V

: 2.0 mA typ. @ 3.0V

: 0.9

A typ. @ 3.0V

Freq: 4.0 MHz max.

: 4.0V to 6.0V

: 5 mA max. @ 5.5V

: 21

A max. @ 4.0V

Freq: 4.0 MHz Max.

XT V

: 4.0V to 6.0V

: 5 mA max. @ 5.5V

: 21

A max. @ 4.0V

Freq: 4.0 MHz max.

: 4.5V to 5.5V

: 2.7 mA typ. @ 5.5V

: 1.5

A typ. @ 4.0V

Freq: 4.0 MHz max.

: 4.5V to 5.5V

: 2.7 mA typ. @ 5.5V

: 1.5

A typ. @ 4.0V

Freq: 4.0 MHz max.

: 3.0V to 6.0V

: 2.0 mA typ. @ 3.0V

: 0.9

A typ. @ 3.0V

Freq: 4.0 MHz max.

: 4.0V to 6.0V

: 5 mA max. @ 5.5V

: 21

A max. @ 4.0V

Freq: 4.0 MHz max.

HS V

: 4.5V to 5.5V

: 13.5 mA typ. @ 5.5V

: 1.5

A typ. @ 4.5V

Freq: 4.0 MHz max.

: 4.5V to 5.5V

: 30 mA max. @ 5.5V

: 1.5

A typ. @ 4.5V

Freq: 10 MHz max.

: 4.5V to 5.5V

: 30 mA max. @ 5.5V

: 1.5

A typ. @ 4.5V

Freq: 20 MHz max.

Do not use in HS mode V

: 4.5V to 5.5V

: 30 mA max. @ 5.5V

: 1.5

A typ. @ 4.5V

Freq: 10 MHz max.

LP V

: 4.0V to 6.0V

: 52.5

A typ. @

32 kHz, 4.0V

: 0.9

A typ. @ 4.0V

Freq: 200 kHz max.

Do not use in LP mode Do not use in LP mode V

: 3.0V to 6.0V

: 48

A max. @

32 kHz, 3.0V

: 5.0

A max. @ 3.0V

Freq: 200 kHz max.

: 3.0V to 6.0V

: 48

A max. @

32 kHz, 3.0V

: 5.0

A max. @ 3.0V

Freq: 200 kHz max.

The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX speciﬁcations. It is recommended that

the user select the device type that ensures the speciﬁcations required.

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 92

Preliminary



1996 Microchip Technology Inc.

12.1 DC Characteristics: PIC16C641/642/661/662-04 (Commercial, Industrial, Automotive)

PIC16C641/642/661/662-10 (Commercial, Industrial, Automotive)

PIC16C641/642/661/662-20 (Commercial, Industrial, Automotive)

Standard Operating Conditions (unless otherwise stated)

Operating temperature –40

≤

+85

C for industrial,

≤

+70

C commercial, and

–40

≤

+125

C automotive

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

D001

D001A V

Supply Voltage 4.0

4.5 –

–6.0

5.5 V

VXT, RC and LP osc conﬁguration

HS osc conﬁguration

D002* V

RAM Data Retention V oltage

(1)

1.5 – – V Device in SLEEP mode

D003 V

POR

start voltage to

ensure internal Power-on

Reset signal

–V

– V See section on Power-on Reset for

details

D004* S

VDD

rise rate to ensure internal

Power-on Reset signal 0.05 – – V/ms See section on Power-on Reset for

details

D005 V

BOR

Brown-out Reset Voltage 3.7

3.7 4.0

4.0 4.3

4.4 V

VBODEN conﬁguration bit is clear

Automotive

D010 I

Supply Current(2) – 2.7 5 mA XT and RC osc conﬁguration

FOSC = 4 MHz, VDD = 5.5V,

WDT disabled (4)

D010A – 35 70 µA LP osc conﬁguration,

PIC16C64X & PIC16C66X-04 only

FOSC = 32 kHz, VDD = 4.0V,

WDT disabled

D013 – 13.5 30 mA HS osc conﬁguration

FOSC = 20 MHz, VDD = 5.5V,

WDT disabled

Module Differential Current (5)

D015 ∆IBOR Brown-out Reset Current – 350 425 µA BODEN bit is clear, VDD = 5.0V

D016 ∆ICOMP Comparator Current for

each Comparator – – 100 µAVDD = 4.0V

D017 ∆IVREF VREF Current – – 300 µAVDD = 4.0V

D021 ∆IWDT WDT Current –

–6.0

–20

25 µA

µAVDD = 4.0V

Automotive

D021 IPD Power-down Current (3) –

–1.5

2.5 21

24 µA

µAVDD = 4.0V, WDT disabled

Automotive

* These parameters are characterized but not tested.

† Data in “T yp” column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as speciﬁed.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2Rext (mA) with Rext in kΩ.

5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

 1996 Microchip Technology Inc. Preliminary DS30559A-page 93

PIC16C64X & PIC16C66X

12.2 DC Characteristics: PIC16LC641/642/661/662-04 (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature –40°C≤ TA ≤ +85°C for industrial and

0°C ≤ TA ≤ +70°C commercial

Param

No. Sym Characteristic Min Typ† Max Units Conditions

D001 VDD Supply Voltage 3.0 – 6.0 V XT, RC, and LP osc conﬁguration

D002* VDR RAM Data Retention

Voltage (1) 1.5 – – V Device in SLEEP mode

D003 VPOR VDD start voltage to

ensure internal Power-on

Reset signal

–VSS – V See section on Power-on Reset for

details

D004* SVDD VDD rise rate to ensure internal

Power-on Reset signal 0.05 – – V/ms See section on Power-on Reset for

details

D005 VBOR Brown-out Reset Voltage 3.7 4.0 4.3 V BODEN conﬁguration bit is clear

D010

D010A

IDD Supply Current (2) –

–

2.0

22.5

3.8

µA

XT and RC osc conﬁguration

FOSC = 4.0 MHz, VDD = 3.0V,

WDT disabled (4)

LP osc conﬁguration

FOSC = 32 kHz, VDD = 3.0V,

WDT disabled

Module Differential Current (5)

D015 ∆IBOR Brown-out Reset Current – 350 425 µA BODEN bit is clear, VDD = 5.0V

D016 ∆ICOMP Comparator Current for

each Comparator – – 100 µAVDD = 3.0V

D017 ∆IVREF VREF Current – – 300 µAVDD = 3.0V

D021 ∆IWDT WDT Current – 6.0 20 µAVDD = 3.0V

D021 IPD Power-down Current (3) – 0.9 5 µAVDD = 3.0V, WDT disabled

* These parameters are characterized but not tested.

† Data in “T yp” column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as speciﬁed.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2Rext (mA) with Rext in kΩ.

5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

PIC16C64X & PIC16C66X

DS30559A-page 94 Preliminary  1996 Microchip Technology Inc.

12.3 DC Characteristics: PIC16C641/661 (Commercial, Industrial, Automotive)

PIC16C642/662 (Commercial, Industrial, Automotive)

PIC16LC641/661 (Commercial, Industrial)

PIC16LC642/662 (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature –40°C≤ TA ≤ +85°C for industrial,

0°C ≤ TA ≤ +70°C commercial, and

–40°C≤ TA ≤ +125°C automotive

Operating voltage VDD range as described in DC spec Section 12.1 and 12.2

Param

No. Sym Characteristic Min Typ

†Max Unit Conditions

VIL Input Low Voltage

I/O ports

D030 with TTL buffer VSS

VSS -

-0.15VDD

0.8V V

VFor entire VDD range

4.5V ≤ VDD ≤ 5.5V

D031 with Schmitt Trigger input VSS - 0.2VDD V

D032 MCLR, RA4/T0CKI,OSC1 (in

RC mode) Vss - 0.2VDD V(1)

D033 OSC1 (XT and HS modes) Vss - 0.3VDD V

OSC1 (LP modes) Vss - 0.6VDD-1.0 V

VIH Input High Voltage

I/O ports

D040 with TTL buffer 2.0 - VDD V

D041 with Schmitt Trigger input 0.25VDD

to 0.8V -VDD V

D042 MCLR RA4/T0CKI 0.8VDD -VDD V

D043

D043A OSC1 (XT, HS, LP modes)

OSC1 (RC mode) 0.7VDD

0.9VDD -

-VDD

-V

V(1)

D070 IPURB PORTB weak pull-up current 50 200 400 µAVDD = 5.0V, VPIN = VSS

IIL Input Leakage Current(2,3)

I/O ports (Except PORTA) --±1.0 µAV

SS ≤ VPIN ≤ VDD,

pin at hi-impedance

D060 PORTA - - ±0.5 µA Vss ≤ VPIN ≤ VDD,

pin at hi-impedance

D061 RA4/T0CKI - - ±1.0 µA Vss ≤ VPIN ≤ VDD

D063 OSC1, MCLR --±5.0 µA Vss ≤ VPIN ≤ VDD, XT, HS and LP

osc conﬁguration

VOL Output Low Voltage

D080 I/O ports - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,

-40° to +85°C

- - 0.6 V IOL = 7.0 MA, VDD = 4.5V, +125°C

D083 OSC2/CLKOUT - - 0.6 V IOL = 1.6 mA, VDD = 4.5V,

-40° to +85°C

(RC only) - - 0.6 V IOL = 1.2 mA, VDD = 4.5V, +125°C

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and

are not tested.

Note 1: In RC oscillator conﬁguration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the

PIC16C64X & PIC16C66X be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The speciﬁed levels repre-

sent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as coming out of the pin.

 1996 Microchip Technology Inc. Preliminary DS30559A-page 95

PIC16C64X & PIC16C66X

VOH Output High Voltage (3)

D090 I/O ports (Except RA4) VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V,

-40° to +85°C

VDD-0.7 - - V IOH = -2.5 mA,

VDD = 4.5V, +125°C

D092 OSC2/CLKOUT VDD-0.7 - - V IOH = -1.3 mA, VDD=4.5V,

-40° to +85°C

(RC only) VDD-0.7 - - V IOH = -1.0 mA,

VDD = 4.5V, +125°C

Capacitive Loading Specs

on Output Pins

D100 COSC2 OSC2 pin - - 15 pF In XT, HS and LP modes when

external clock used to drive OSC1.

D101 CIO All I/O pins/OSC2 (in RC mode) - - 50 pF

Standard Operating Conditions (unless otherwise stated)

Operating temperature –40°C≤ TA ≤ +85°C for industrial,

0°C ≤ TA ≤ +70°C commercial, and

–40°C≤ TA ≤ +125°C automotive

Operating voltage VDD range as described in DC spec Section 12.1 and 12.2

Param

No. Sym Characteristic Min Typ

†Max Unit Conditions

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and

are not tested.

Note 1: In RC oscillator conﬁguration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the

PIC16C64X & PIC16C66X be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The speciﬁed levels repre-

sent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as coming out of the pin.

PIC16C64X & PIC16C66X

DS30559A-page 96 Preliminary  1996 Microchip Technology Inc.

TABLE 12-2: COMPARATOR SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 6.0V, -40˚C < TA < +125˚C, unless otherwise stated. Current consumption is spec-

iﬁed in Table 12-1.

TABLE 12-3: VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 6.0V, -40°C < TA < +125°C, unless otherwise stated. Current consumption is spec-

iﬁed in Table 12-1.

Characteristics Sym Min Typ Max Units Comments

Input offset voltage - ± 5.0 ± 10 mV

Input common mode voltage* 0 - VDD - 1.5 V

CMRR* 35 - - db

Response T ime(1)* - 150 400

600 ns

ns PIC16C64X/66X

PIC16LC64X/66X

Comparator Mode Change to

Output Valid* -- 10µs

* These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from

VSS to VDD.

Characteristics Sym Min Typ Max Units Comments

Resolution VDD/24 - VDD/32 LSb

Absolute Accuracy -

-1/4

1/2 LSb

LSb Low Range (VRR = 1)

High Range (VRR = 0)

Unit Resistor Value (R)* - 2k - ΩFigure 8-2

Settling T ime(1)*- - 10 µs

* These parameters are characterized but not tested.

Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.

 1996 Microchip Technology Inc. Preliminary DS30559A-page 97

PIC16C64X & PIC16C66X

12.4 Timing Parameter Symbology

The timing parameter symbols have been created with one of the following formats:

FIGURE 12-1: LOAD CONDITIONS

1. TppS2ppS

2. TppS

F Frequency T Time

Lowercase subscripts (pp) and their meanings:

ck CLKOUT osc OSC1

io I/O port t0 T0CKI

mc MCLR

Uppercase letters and their meanings:

F Fall P Period

H High R Rise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-Impedance

VDD/2

Pin Pin

VSS VSS

RL= 464Ω

CL= 50 pF for all pins except OSC2

15 pF for OSC2 output

Load condition 1 Load condition 2

PIC16C64X & PIC16C66X

DS30559A-page 98 Preliminary  1996 Microchip Technology Inc.

12.5 Timing Diagrams and Speciﬁcations

FIGURE 12-2: EXTERNAL CLOCK TIMING

TABLE 12-4: EXTERNAL CLOCK TIMING REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

Fosc External CLKIN Frequency(1) DC — 4 MHz XT and RC osc mode,

VDD = 5.0V

DC — 20 MHz HS osc mode

DC — 200 kHz LP osc mode

Oscillator Frequency (1) DC — 4 MHz RC osc mode, VDD = 5.0V

0.1 — 4 MHz XT osc mode

4 — 20 MHz HS osc mode

5 – 200 kHz LP osc mode

1 Tosc External CLKIN Period(1) 250 — — ns XT and RC osc mode

50 — — ns HS osc mode

5——µs LP osc mode

Oscillator Period(1) 250 — — ns RC osc mode

250 — 10,000 ns XT osc mode

50 — 250 ns HS osc mode

5——µs LP osc mode

CY Instruction Cycle Time(1) 200 — DC ns TCY = FOSC/4

3* TosL,

TosH External Clock in (OSC1)

High or Low Time 100 — — ns XT osc mode

2.5 — — µs LP osc mode

15 — — ns HS osc mode

4* TosR,

TosF External Clock in (OSC1)

Rise or Fall Time — — 25 ns XT osc mode

— — 50 ns LP osc mode

— — 15 ns HS osc mode

* These parameters are characterized but not tested.

† Data in “T yp” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All speciﬁed values are

based on characterization data for that particular oscillator type under standard operating conditions with

the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation

and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an

external clock applied to the OSC1 pin.

When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

133

 1996 Microchip Technology Inc. Preliminary DS30559A-page 99

PIC16C64X & PIC16C66X

FIGURE 12-3: CLKOUT AND I/O TIMING

TABLE 12-5: CLKOUT AND I/O TIMING REQUIREMENTS

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns Note 1

11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns Note 1

12* TckR CLKOUT rise time — 35 100 ns Note 1

13* TckF CLKOUT fall time — 35 100 ns Note 1

14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1

15* TioV2ckH Port in valid before CLKOUT ↑ TOSC + 200 — — ns Note 1

16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1

17* TosH2ioV OSC1↑ (Q1 cycle) to

Port out valid — 50 150 ns

18* TosH2ioI OSC1↑ (Q2 cycle) to

Port input invalid (I/O in

hold time)

PIC16C64X/66X 100 — — ns

PIC16LC64X/66X 200 — — ns

19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns

20* TioR Port output rise time PIC16C64X/66X — 10 40 ns

PIC16LC64X/66X — — 80 ns

21* TioF Port output fall time PIC16C64X/66X — 10 40 ns

PIC16LC64X/66X — — 80 ns

22††* Tinp INT pin high or low time TCY ——ns

23††* Trbp RB7:RB4 change INT high or low time TCY ——ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance

only and are not tested.

†† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

Note: See Figure 12-1 for load conditions.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

13 14

20, 21

19 18

12 16

old value new value

PIC16C64X & PIC16C66X

DS30559A-page 100 Preliminary  1996 Microchip Technology Inc.

FIGURE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP

TIMER TIMING

FIGURE 12-5: BROWN-OUT RESET TIMING

TABLE 12-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET REQUIREMENTS

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2 — — µsVDD = 5V, -40˚C to +125˚C

31* T wdt W atchdog Timer Time-out Period

(No Prescaler) 71833msVDD = 5V, -40˚C to +125˚C

32 Tost Oscillation Start-up Timer Period — 1024TOSC ——TOSC = OSC1 period

33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +125˚C

34 TIOZ I/O Hi-impedance from MCLR Low

or Watchdog Timer Reset — — 2.1 µs

35 TBOR Brown-out Reset pulse width 100 — — µsVDD ≤ BVDD (D005)

36 TPER Parity Error Reset — TBD — µs

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

VDD

MCLR

Internal

POR

PWRT

Timeout

OSC

Timeout

Internal

RESET

Watchdog

Timer

RESET

I/O Pins

Parity

Error

Reset

VDD BVDD

 1996 Microchip Technology Inc. Preliminary DS30559A-page 101

PIC16C64X & PIC16C66X

FIGURE 12-6: TIMER0 CLOCK TIMING

TABLE 12-7: TIMER0 CLOCK REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns

With Prescaler 10 — — ns

41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns

With Prescaler 10 — — ns

42* Tt0P T0CKI Period TCY + 40

N— — ns N = prescale

value (1, 2, 4, …,

256)

* These parameters are characterized but not tested.

† Data in “T yp” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

RA4/T0CKI

TMR0

PIC16C64X & PIC16C66X

DS30559A-page 102 Preliminary  1996 Microchip Technology Inc.

FIGURE 12-7: PARALLEL SLAVE PORT TIMING (PIC16C661 AND PIC16C662)

TABLE 12-8: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C661 AND PIC16C662)

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

62 TdtV2wrH Data in valid before WR↑ or CS↑ (setup time) 20 — — ns

63* TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) PIC16C66X 20 — — ns

PIC16LC66X 35 — — ns

64 TrdL2dtV RD↓ and CS↓ to data–out valid — — 80 ns

65 TrdH2dtI RD↑ or CS↓ to data–out invalid 10 — 30 ns

† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note: Refer to Figure 12-1 for load conditions

RE2/CS

RE0/RD

RE1/WR

RD7:RD0



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 103

PIC16C64X & PIC16C66X

13.0 DEVICE CHARACTERIZATION

INFORMATION

NOT AVAILABLE AT THIS TIME.

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 104

Preliminary



1996 Microchip Technology Inc.

NOTES:



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 105

PIC16C64X & PIC16C66X

14.0 PACKAGING INFORMATION

Package Type: 28-Lead Skinny Plastic Dual In-Line (SP) - 300 mil

Package Group: Plastic Dual In-Line (PLA)

Symbol

Millimeters Inches

Min Max Notes Min Max Notes

A 3.632 4.572 0.143 0.180

A1 0.381 — 0.015 —

A2 3.175 3.556 0.125 0.140

B 0.406 0.559 0.016 0.022

B1 1.016 1.651

Typical

0.040 0.065

Typical

B2 0.762 1.016

4 places

0.030 0.040

4 places

B3 0.203 0.508

4 places

0.008 0.020

4 places

C 0.203 0.331

Typical

0.008 0.013

Typical

D 34.163 35.179 1.385 1.395

D1 33.020 33.020

BSC

1.300 1.300

BSC

E 7.874 8.382 0.310 0.330

E1 7.112 7.493 0.280 0.295

e1 2.540 2.540

Typical

0.100 0.100

Typical

eA 7.874 7.874

BSC

0.310 0.310

BSC

eB 8.128 9.906 0.320 0.390

L 3.175 3.683 0.125 0.145

S 0.584 1.220 0.023 0.048

Pin No. 1

Indicator

Area

E1 E

Base

Plane

Seating

Plane A1A2A

Detail A

B2 B1

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 106

Preliminary



1996 Microchip Technology Inc.

Package Type: 28-Lead Plastic Small Outline (SO) - Wide, 300 mil Body

Package Group: Plastic SOIC (SO)

Symbol

Millimeters Inches

Min Max Notes Min Max Notes

A 2.362 2.642 0.093 0.104

A1 0.101 0.300 0.004 0.012

B 0.355 0.483 0.014 0.019

C 0.241 0.318 0.009 0.013

D 17.703 18.085 0.697 0.712

E 7.416 7.595 0.292 0.299

e 1.270 1.270

BSC

0.050 0.050

BSC

H 10.007 10.643 0.394 0.419

h 0.381 0.762 0.015 0.030

L 0.406 1.143 0.016 0.045

CP — 0.102 — 0.004

h x 45°

Chamfer

h x 45°

Seating

Plane

Base

Plane

A1 A

Pin No. 1

Indicator

Area



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 107

PIC16C64X & PIC16C66X

Package Type: 28-Lead Ceramic Side Brazed Dual In-Line with Window (JW) (300 mil)

Package Group: Ceramic Side Brazed Dual In-Line (CER)

Symbol Millimeters Inches

Min Max Notes Min Max Notes

A 3.937 5.030 0.155 0.198

A1 1.016 1.524 0.040 0.060

A2 2.921 3.506 0.115 0.138

A3 1.930 2.388 0.076 0.094

B 0.406 0.508 0.016 0.020

B1 1.219 1.321

Typical

0.048 0.052

C 0.228 0.305

Typical

0.009 0.012

D 35.204 35.916 1.386 1.414

D1 32.893 33.147

BSC

1.295 1.305

E 7.620 8.128 0.300 0.320

E1 7.366 7.620 0.290 0.300

e1 2.413 2.667

Typical

0.095 0.105

eA 7.366 7.874

BSC

0.290 0.310

eB 7.594 8.179 0.299 0.322

L 3.302 4.064 0.130 0.160

S 1.143 1.397 0.045 0.055

S1 0.533 0.737 0.021 0.029

E1 E

Base

Plane

Seating

Plane

B1 B

LA1 A2A3 A

Pin No. 1

Indicator Area

αC

PIC16C64X & PIC16C66X

DS30559A-page 108

Preliminary



1996 Microchip Technology Inc.

Package Type: 40-Lead Ceramic Dual In-Line with Window (JW) - (600 mil)

Package Group: Ceramic CERDIP Dual In-Line (CDP)

Symbol

Millimeters Inches

Min Max Notes Min Max Notes

A 4.318 5.715 0.170 0.225

A1 0.381 1.778 0.015 0.070

A2 3.810 4.699

0.150 0.185

A3 3.810 4.445 0.150 0.175

B 0.355 0.585 0.014 0.023

B1 1.270 1.651

Typical

0.050 0.065

Typical

C 0.203 0.381

Typical

0.008 0.015

Typical

D 51.435 52.705 2.025 2.075

D1 48.260 48.260

BSC

1.900 1.900

BSC

E 15.240 15.875 0.600 0.625

E1 12.954 15.240 0.510 0.600

e1 2.540 2.540

BSC

0.100 0.100

BSC

eA 14.986 16.002

Typical

0.590 0.630

Typical

eB 15.240 18.034 0.600 0.710

L 3.175 3.810 0.125 0.150

S 1.016 2.286 0.040 0.090

S1 0.381 1.778 0.015 0.070

αC

Pin No. 1

Indicator

Area

E1 E

BD1

A1A3AA2

Seating

Plane

Base

Plane



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 109

PIC16C64X & PIC16C66X

Package Type: 40-Lead Plastic Dual In-Line (P) - 600 mil

Package Group: Plastic Dual In-Line (PLA)

Symbol

Millimeters Inches

Min Max Notes Min Max Notes

A — 5.080 — 0.200

A1 0.381 — 0.015 —

A2 3.175 4.064 0.125 0.160

B 0.355 0.559 0.014 0.022

B1 1.270 1.778

Typical

0.050 0.070

Typical

C 0.203 0.381

Typical

0.008 0.015

Typical

D 51.181 52.197 2.015 2.055

D1 48.260 48.260

BSC

1.900 1.900

BSC

E 15.240 15.875 0.600 0.625

E1 13.462 13.970 0.530 0.550

e1 2.489 2.591

Typical

0.098 0.102

Typical

eA 15.240 15.240

BSC

0.600 0.600

BSC

eB 15.748 17.272 0.620 0.680

L 2.921 3.683 0.115 0.145

S 1.270 — 0.050 —

S1 0.508 — 0.020 —

Pin No. 1

Indicator

Area

E1 E

BD1

Base

Plane

Seating

Plane

A1A2A

PIC16C64X & PIC16C66X

DS30559A-page 110

Preliminary



1996 Microchip Technology Inc.

Package Type: 44-Lead Plastic Leaded Chip Carrier (L) - Square

Package Group: Plastic Leaded Chip Carrier (PLCC)

Symbol

Millimeters Inches

Min Max Notes Min Max Notes

A 4.191 4.572 0.165 0.180

A1 2.413 2.921 0.095 0.115

D 17.399 17.653 0.685 0.695

D1 16.510 16.663 0.650 0.656

D2 15.494 16.002 0.610 0.630

D3 12.700 12.700

BSC

0.500 0.500

BSC

E 17.399 17.653 0.685 0.695

E1 16.510 16.663 0.650 0.656

E2 15.494 16.002 0.610 0.630

E3 12.700 12.700

BSC

0.500 0.500

BSC

CP — 0.102 — 0.004

LT 0.203 0.381 0.008 0.015

0.177

.007 BD-E

-A-

0.254

-C-

-F-

-D-

-B-

-E- S

0.177

.007 AF-G

EE1

-H-

-G-

.010 Max 1.524

.060

0.508

.020

1.651

.065

R1.14/0.64

.045/.025 R1.14/0.64

.045/.025

1.651

.065

0.508

.020 -H-

0.254

.010 Max

Min

0.812/0.661

.032/.026 3

-C-

0.64

.025 Min 5

0.533/0.331

.021/.013

0.177

.007 MAF-G S ,D-E S

1.27

.050

2 Sides AS

0.177

.007 BA

D3/E3

D20.101

.004

0.812/0.661

.032/.026

0.38

.015 F-G

0.38

.015 F-G

-H-

Seating

Plane

2 Sides

N Pics

D/2

E/2



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 111

PIC16C64X & PIC16C66X

Package Type: 44-Lead Thin Plastic Quad Flatpack (PT/TQ) - 10x10x1 mm Body 1.0/0.10 mm Lead Form

Package Group: Plastic TQFP

Symbol

Millimeters Inches

Min Max Notes Min Max Notes

A — 1.200 — 0.047

A1 0.050 0.150 0.002 0.006

A2 0.950 1.050 0.037 0.041

b 0.300 0.450 0.012 0.018

b1 0.300 0.400 0.012 0.016

D 12.0 12.0

BSC

0.472 0.0472

BSC

D1 10.0 10.0

BSC

0.394 0.394

BSC

E 12.0 12.0

BSC

0.472 0.472 BSC

E1 10.0 10.0 BSC 0.394 0.394 BSC

e 0.8 0.8 BSC 0.031 0.031 BSC

L 0.450 0.750 0.018 0.030

DD/2

E/2

0.09/0.20

0.09/0.16

Base Metal

with Lead Finish

A1 0.08

R min.

0.20 min.

1.00 ref. L

0-7°

Datum Plane

Gauge Plane

0.25

0° min.

DETAIL B

PinNo. 1

Indicator

Area

Detail B

8 Places

11/13°

PIC16C64X & PIC16C66X

DS30559A-page 112 Preliminary  1996 Microchip Technology Inc.

14.1 Package Marking Information

Legend: MM...MMicrochip part number information

XX...X Customer speciﬁc information*

AA Year code (last 2 digits of calendar year)

BB Week code (week of January 1 is week ‘01’)

C Facility code of the plant at which wafer is manufactured

C = Chandler, Arizona, U.S.A.

D Mask revision number

E Assembly code of the plant or country of origin in which

part was assembled

Note:In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next

line thus limiting the number of available characters for customer speciﬁc information.

*Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and

assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip

Sales Ofﬁce. For QTP devices, any special marking adders are included in QTP price.

XXXXXXXXXXXXXXX

AABBCDE

28-Lead PDIP (Skinny DIP)

MMMMMMMMMMMM

AABBCDE

Example

PIC16C642-10/SP

28-Lead SOIC

XXXXXXXXXXXXXXXXXXXX

AABBCDE

MMMMMMMMMMMMMMMM

Example

945/CAA

PIC16C642-10/SO

Example28-Lead Side Brazed Skinny Windowed

XXXXXXXXXXX

AABBCDE

PIC16C642/JW

9517CAT

 1996 Microchip Technology Inc. Preliminary DS30559A-page 113

PIC16C64X & PIC16C66X

14.2 Package Marking Information

Legend: MM...MMicrochip part number information

XX...X Customer speciﬁc information*

AA Year code (last 2 digits of calendar year)

BB Week code (week of January 1 is week ‘01’)

C Facility code of the plant at which wafer is manufactured

C = Chandler, Arizona, U.S.A.

D Mask revision number

E Assembly code of the plant or country of origin in which

part was assembled

Note:In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next

line thus limiting the number of available characters for customer speciﬁc information.

*Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and

assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip

Sales Ofﬁce. For QTP devices, any special marking adders are included in QTP price.

XXXXXXXXXXXXXXXXXX

AABBCDE

40-Lead PDIP

MMMMMMMMMMMMMM

9512CAA

Example

PIC16C662-04/P

44-Lead PLCC

MMMMMMMM

AABBCDE

XXXXXXXXXX

44-Lead TQFP

XXXXXXXXXX

AABBCDE

MMMMMMMM

XXXXXXXXXX

Example

PIC16C662

AABBCDE

-20/L

Example

-20/TQ

AABBCDE

PIC16C662

MMMMMMMMM

XXXXXXXXXXX

AABBCDE

40-Lead CERDIP Windowed

XXXXXXXXXXX

PIC16C662/JW

AABBCDE

Example

PIC16C64X & PIC16C66X

DS30559A-page 114 Preliminary  1996 Microchip Technology Inc.

NOTES:



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 115

PIC16C64X & PIC16C66X

APPENDIX A: ENHANCEMENTS

The following are the list of enhancements over the

PIC16C5X microcontroller family:

1. Instruction word length is increased to 14 bits.

This allows larger page sizes both in program

memory (4K now as opposed to 512 before) and

before).

2. A PC high latch register (PCLATH) is added to

handle program memory paging. P A2, PA1, P A0

bits are removed from STATUS register.

3. Data memory paging is slightly redeﬁned.

STATUS register is modiﬁed.

4. Four new instructions have been added:

RETURN

RETFIE

ADDLW

, and

SUBLW

Two instructions

TRIS

and

OPTION

are being

phased out although they are kept for

compatibility with PIC16C5X.

OPTION

and

TRIS

registers are made

addressable.

6. Interrupt capability is added. Interrupt vector is

at 0004h.

7. Stack size is increased to 8 deep.

8. Reset vector is changed to 0000h.

9. Reset of all registers is revisited. Six different

reset (and wake-up) types are recognized.

Registers are reset differently.

10. Wake up from SLEEP through interrupt is

added.

11. Two separate timers, Oscillator Start-up Timer

(OST) and Power-up Timer (PWRT) are

included for more reliable power-up. These

timers can be invoked selectively to avoid

unnecessary delays on power-up and wake-up.

12. PORTB has weak pull-ups and interrupt on

change feature.

13. Timer0 clock input, T0CKI pin is also a port pin

(RA4/T0CKI) and has a TRIS bit.

14. FSR is made a full 8-bit register.

15. “In-circuit programming” is made possible. The

user can program PIC16CXX devices using only

ﬁve pins: V

, V

, RB6 (clock) and RB7

(data in/out).

16. PCON status register is added with a Power-on

Reset status bit (POR), a Brown-out Reset sta-

tus bit (BOR), a Parity Error Reset (PER), and a

Memory Parity Enable (MPEEN) bit.

17. Code protection scheme is enhanced such that

portions of the program memory can be

protected, while the remainder is unprotected.

18. PORTA inputs are now Schmitt Trigger inputs.

19. Brown-out Reset circuitry has been added.

APPENDIX B: COMPATIBILITY

To convert code written for PIC16C5X to PIC16CXX,

the user should take the following steps:

1. Remove any program memory page select

operations (PA2, PA1, PA0 bits) for

CALL

GOTO

2. Revisit any computed jump operations (write to

PC or add to PC, etc.) to make sure page bits

are set properly under the new scheme.

3. Eliminate any data memory page switching.

Redeﬁne data variables to reallocate them.

4. Verify all writes to STATUS, OPTION, and FSR

registers since these have changed.

5. Change reset vector to 0000h.

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 116

Preliminary



1996 Microchip Technology Inc.

APPENDIX C: WHAT’S NEW

New Data Sheet

APPENDIX D: WHAT’S CHANGED

New Data Sheet

PIC16C64X & PIC16C66X



1996 Microchip Technology Inc. DS30559A-page 117

APPENDIX E: PIC16/17 MICROCONTROLLERS

E.1 PIC14000 Devices

PIC14000 20 4K 192 TMR0

ADTMR I2C/

SMBus 14 11 22 2.7-6.0 Yes

Internal Oscillator,

Bandgap Reference,

Temperature Sensor,

Calibration Factors,

Low Voltage Detector,

SLEEP, HIBERNATE,

Comparators with

Programmable References

(2)

28-pin DIP, SOIC, SSOP

(.300 mil)

Maximum Frequency of Operation (MHz)

Data Memory (bytes)

Timer Module(s)

Serial Port(s) (SPI/I

C, USART)

Slope A/D Converter

Interrupt Sources

I/O Pins

Voltage Range (Volts)

EPROM Program Memory (x14 words)

Clock Memory Peripherals Features

In-Circuit Serial Programming

Additional On-chip

Features

Packages

(high-res) Channels

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 118



1996 Microchip Technology Inc.

E.2 PIC16C5X Family of Devices

PIC16C52 4 384 — 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC

PIC16C54 20 512 — 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16C54A 20 512 — 25 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16CR54A 20 — 512 25 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16C55 20 512 — 24 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP

PIC16C56 20 1K — 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16C57 20 2K — 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP

PIC16CR57B 20 — 2K 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP

PIC16C58A 20 2K — 73 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16CR58A 20 — 2K 73 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

All PIC16/17 Family devices have Power-On Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.

Packages

Number of Instructions

Voltage Range (Volts)

I/O Pins

Timer Module(s)

RAM Data Memory (bytes)

(x12 words)

Program Memory

ROM

EPROM

Maximum Frequency of Operation (MHz)

FeaturesPeripheralsMemoryClock

PIC16C64X & PIC16C66X



1996 Microchip Technology Inc. DS30559A-page 119

E.3 PIC16CXXX Family of Devices

PIC16C554 20 512 80 TMR0 — —313 2.5-6.0 — 18-pin DIP, SOIC; 20-pin SSOP

PIC16C556 20 1K 80 TMR0 — — 3 13 2.5-6.0 — 18-pin DIP, SOIC; 20-pin SSOP

PIC16C558 20 2K 128 TMR0 — — 3 13 2.5-6.0 — 18-pin DIP, SOIC; 20-pin SSOP

PIC16C620 20 512 80 TMR0 2 Yes 4 13 2.5-6.0 Yes 18-pin DIP, SOIC; 20-pin SSOP

PIC16C621 20 1K 80 TMR0 2 Yes 4 13 2.5-6.0 Yes 18-pin DIP, SOIC; 20-pin SSOP

PIC16C622 20 2K 128 TMR0 2 Yes 4 13 2.5-6.0 Yes 18-pin DIP, SOIC; 20-pin SSOP

PIC16C641 20 2K 128 TMR0 2 Yes 4 22 3.0-6.0 Yes 28-pin PDIP, SOIC

Windowed CDIP

PIC16C642 20 4K 176 TMR0 2 Yes 4 22 3.0-6.0 Yes 28-pin PDIP, SOIC

Windowed CDIP

PIC16C661 20 2K 128 TMR0 2 Yes 5 33 3.0-6.0 Yes 40-pin PDIP, Windowed CDIP;

44-pin PLCC, MQFP

PIC16C662 20 4K 176 TMR0 2 Yes 5 33 3.0-6.0 Yes 40-pin PDIP, Windowed CDIP;

44-pin PLCC, MQFP

All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O

current capability.

All PIC16C6XXX Family devices use serial programming with clock pin RB6 and data pin RB7.

Maximum Frequency of Operation (MHz)

EPROM

Data Memory (bytes)

Timer Module(s)

Comparator(s)

Internal Reference Voltage

I/O Pins

Voltage Range (Volts)

Brown-out Reset

Packages

Program Memory

Clock Memory Peripherals Features

(x14 words)

Interupt Source

PIC16C64X & PIC16C66X

DS30559A-page 120



1996 Microchip Technology Inc.

E.4 PIC16C6X Family of Devices

PIC16C62 20 2K — 128 TMR0,

TMR1, TMR2 1 SPI/I2C — 7 22 3.0-6.0 Yes — 28-pin SDIP, SOIC, SSOP

PIC16C62A(1) 20 2K — 128 TMR0,

TMR1, TMR2 1 SPI/I2C — 7 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC, SSOP

PIC16CR62(1) 20 — 2K 128 TMR0,

TMR1, TMR2 1 SPI/I2C — 7 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC, SSOP

PIC16C63 20 4K — 192 TMR0,

TMR1, TMR2 2 SPI/I2C,

USART — 10 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC

PIC16CR63(1) 20 — 4K 192 TMR0,

TMR1, TMR2 2 SPI/I2C,

USART — 10 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC

PIC16C64 20 2K — 128 TMR0,

TMR1, TMR2 1 SPI/I2C Yes 8 33 3.0-6.0 Yes — 40-pin DIP;

44-pin PLCC, MQFP

PIC16C64A(1) 20 2K — 128 TMR0,

TMR1, TMR2 1 SPI/I2C Yes 8 33 2.5-6.0 Yes Yes 40-pin DIP;

44-pin PLCC, MQFP, TQFP

PIC16CR64(1) 20 — 2K 128 TMR0,

TMR1, TMR2 1 SPI/I2C Yes 8 33 2.5-6.0 Yes Yes 40-pin DIP;

44-pin PLCC, MQFP, TQFP

PIC16C65 20 4K — 192 TMR0,

TMR1, TMR2 2 SPI/I2C,

USART Yes 11 33 3.0-6.0 Yes — 40-pin DIP;

44-pin PLCC, MQFP

PIC16C65A(1) 20 4K — 192 TMR0,

TMR1, TMR2 2 SPI/I2C,

USART Yes 11 33 2.5-6.0 Yes Yes 40-pin DIP;

44-pin PLCC, MQFP, TQFP

PIC16CR65(1) 20 — 4K 192 TMR0,

TMR1, TMR2 2 SPI/I2C,

USART Yes 11 33 2.5-6.0 Yes Yes 40-pin DIP;

44-pin PLCC, MQFP, TQFP

All PIC16/17 family devices have Power-on Reset, selectable W atchdog Timer, selectable code protect, and high I/O current capability.

All PIC16C6X family devices use serial programming with clock pin RB6 and data pin RB7.

Note 1: Please contact your local sales ofﬁce for availability of these devices.

Maximum Frequency of Operation (MHz)

EPROM

Data Memory (bytes)

Timer Module(s)

Capture/Compare/PWM Module(s)

Serial Port(s) (SPI/I

C, USART)

Parallel Slave Port

Interrupt Sources

I/O Pins

Voltage Range (Volts)

Brown-out Reset

Packages

Program Memory

Clock Memory Peripherals Features

ROM

In-Circuit Serial Programming

(x14 words)

PIC16C64X & PIC16C66X



1996 Microchip Technology Inc. DS30559A-page 121

E.5 PIC16C7X Family of Devices

PIC16C710 20 512 36 TMR0 — — — 4 4 13 2.5-6.0 Yes Yes 18-pin DIP, SOIC;

20-pin SSOP

PIC16C71 20 1K 36 TMR0 — — — 4 4 13 2.5-6.0 Yes — 18-pin DIP, SOIC

PIC16C711 20 1K 68 TMR0 — — — 4 4 13 2.5-6.0 Yes Yes 18-pin DIP, SOIC;

20-pin SSOP

PIC16C72 20 2K 128 TMR0,

TMR1, TMR2 1SPI/I2C— 5 8 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC, SSOP

PIC16C73 20 4K 192 TMR0,

TMR1, TMR2 2SPI/I2C,

USART — 5 11 22 2.5-6.0 Yes — 28-pin SDIP, SOIC

PIC16C73A 20 4K 192 TMR0,

TMR1, TMR2 2SPI/I2C,

USART — 5 11 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC

PIC16C74 20 4K 192 TMR0,

TMR1, TMR2 2SPI/I2C,

USART Yes 8 12 33 2.5-6.0 Yes — 40-pin DIP;

44-pin PLCC, MQFP

PIC16C74A 20 4K 192 TMR0,

TMR1, TMR2 2SPI/I2C,

USART Yes 8 12 33 2.5-6.0 Yes Yes 40-pin DIP;

44-pin PLCC, MQFP, TQFP

All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current

capability.

All PIC16C7X Family devices use serial programming with clock pin RB6 and data pin RB7.

Maximum Frequency of Operation (MHz)

EPROM Program Memory (x14 words)

Data Memory (bytes)

Timer Module(s)

Capture/Compare/PWM Module(s)

Serial Port(s) (SPI/I

C, USART)

Parallel Slave Port

A/D Converter (8-bit) Channels

Interrupt Sources

I/O Pins

Voltage Range (Volts)

Brown-out Reset

Packages

Clock Memory Peripherals Features

In-Circuit Serial Programming

PIC16C64X & PIC16C66X

DS30559A-page 122



1996 Microchip Technology Inc.

E.6 PIC16C8X Family of Devices

PIC16C84 10 — 1K — 36 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC

PIC16F84(1) 10 1K — — 68 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC

PIC16CR84(1) 10 — — 1K 68 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC

PIC16F83(1) 10 512 — — 36 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC

PIC16CR83(1) 10 — — 512 36 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC

All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and

high I/O current capability.

All PIC16C8X family devices use serial programming with clock pin RB6 and data pin RB7.

Note 1: Please contact your local sales ofﬁce for availability of these devices.

Maximum Frequency of Operation (MHz)

EEPROM

Data EEPROM (bytes)

Data Memory (bytes)

Timer Module(s)

Interrupt Sources

I/O Pins

Voltage Range (Volts)

Packages

Program Memory

Clock Memory Peripherals Features

ROM

Flash

PIC16C64X & PIC16C66X



1996 Microchip Technology Inc. DS30559A-page 123

E.7 PIC16C9XX Family Of Devices

PIC16C923 8 4K 176 TMR0,

TMR1, TMR2 1SPI/I2C— — 4 Com

32 Seg 8 25 27 3.0-6.0 Yes — 64-pin SDIP(1), TQFP,

68-pin PLCC, DIE

PIC16C924 8 4K 176 TMR0,

TMR1, TMR2 1SPI/I2C— 5 4 Com

32 Seg 9 25 27 3.0-6.0 Yes — 64-pin SDIP(1), TQFP,

68-pin PLCC, DIE

All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.

All PIC16CXX Family devices use serial programming with clock pin RB6 and data pin RB7.

Note 1: Please contact your local Microchip representative for availability of this package.

Maximum Frequency of Operation (MHz)

EPROM

Data Memory (bytes)

Timer Module(s)

Capture/Compare/PWM Module(s)

Serial Port(s) (SPI/I

C, USART)

Parallel Slave Port

A/D Converter (8-bit) Channels

Interrupt Sources

I/O Pins

Voltage Range (Volts)

Brown-out Reset

Packages

Program Memory

Clock Memory Peripherals Features

In-Circuit Serial Programming

Input Pins

LCD Module

PIC16C64X & PIC16C66X

DS30559A-page 124



1996 Microchip Technology Inc.

E.8 PIC17CXX Family of Devices

PIC17C42 25 2K — 232 TMR0,TMR1,

TMR2,TMR3 2 2 Yes — Yes 11 33 4.5-5.5 55 40-pin DIP;

44-pin PLCC, MQFP

PIC17C42A 25 2K — 232 TMR0,TMR1,

TMR2,TMR3 2 2 Yes Yes Yes 11 33 2.5-6.0 58 40-pin DIP;

44-pin PLCC, TQFP, MQFP

PIC17CR42 25 — 2K 232 TMR0,TMR1,

TMR2,TMR3 2 2 Yes Yes Yes 11 33 2.5-6.0 58 40-pin DIP;

44-pin PLCC, TQFP, MQFP

PIC17C43 25 4K — 454 TMR0,TMR1,

TMR2,TMR3 2 2 Yes Yes Yes 11 33 2.5-6.0 58 40-pin DIP;

44-pin PLCC, TQFP, MQFP

PIC17CR43 25 — 4K 454 TMR0,TMR1,

TMR2,TMR3 2 2 Yes Yes Yes 11 33 2.5-6.0 58 40-pin DIP;

44-pin PLCC, TQFP, MQFP

PIC17C44 25 8K 454 TMR0,TMR1,

TMR2,TMR3 2 2 Yes Yes Yes 11 33 2.5-6.0 58 40-pin DIP;

44-pin PLCC, TQFP, MQFP

All PIC16/17 Family devices have Power-on Reset, selectable W atchdog Timer, selectable code protect and high I/O current capability.

Maximum Frequency of Operation (MHz)

EPROM

RAM Data Memory (bytes)

Timer Module(s)

Captures

Serial Port(s) (USART)

External Interrupts

Interrupt Sources

I/O Pins

Voltage Range (Volts)

Number of Instructions

Packages

Clock Memory Peripherals Features

PWMs

Hardware Multiply

Program Memory (Words)

ROM



1996 Microchip Technology Inc. DS30559A-page 125

PIC16C64X & PIC16C66X

PIN COMPATIBILITY

Devices that have the same package type and V

and MCLR pin locations are said to be pin

compatible. This allows these different devices to

operate in the same socket. Compatible devices may

only requires minor software modiﬁcation to allow

proper operation in the application socket

(ex., PIC16C56 and PIC16C61 devices). Not all

devices in the same package size are pin compatible;

for example, the PIC16C62 is compatible with the

PIC16C63, but not the PIC16C55.

Pin compatibility does not mean that the devices offer

the same features. As an example, the PIC16C54 is

pin compatible with the PIC16C71, but does not have

an A/D converter, weak pull-ups on PORTB, or

interrupts.

TABLE E-1: PIN COMPATIBLE DEVICES

Pin Compatible Devices Package

PIC12C508, PIC12C509 8-pin

PIC16C54, PIC16C54A,

PIC16CR54A,

PIC16C56,

PIC16C58A, PIC16CR58A,

PIC16C61,

PIC16C554, PIC16C556, PIC16C558

PIC16C620, PIC16C621, PIC16C622,

PIC16C710, PIC16C71, PIC16C711,

PIC16F83, PIC16CR83,

PIC16C84, PIC16F84A, PIC16CR84

18-pin

20-pin

PIC16C55,

PIC16C57, PIC16CR57B 28-pin

PIC16C62, PIC16CR62, PIC16C62A, PIC16C63,

PIC16C72, PIC16C73, PIC16C73A 28-pin

PIC16C64, PIC16CR64, PIC16C64A,

PIC16C65, PIC16C65A,

PIC16C74, PIC16C74A

40-pin

PIC17C42, PIC17CR42, PIC17C42A,

PIC17C43, PIC17CR43, PIC17C44 40-pin

PIC16C923, PIC16C924 64/68-pin

PIC16C64X & PIC16C66X

DS30559A-page 126



1996 Microchip Technology Inc.

NOTES:



1996 Microchip Technology Inc.

Preliminary

DS30559A-page 127

PIC16C64X & PIC16C66X

INDEX

ADDLW Instruction

.........................................................76

ADDWF Instruction

........................................................76

ANDLW Instruction

.........................................................76

ANDWF Instruction

........................................................76

Architectural Overview

.....................................................9

Assembler

........................................................................88

BCF Instruction

............................................................... 77

Bit Manipulation

..............................................................74

Block Diagrams

...............................................................30

Comparator Analog Input Mode

..........................51

Comparator I/O Operating Modes

.......................48

Comparator Output

................................................50

Crystal Operation

...................................................57

External Brown-out Protection 1

..........................65

External Brown-out Protection 2

..........................65

External Clock Input Operation

............................57

External Parallel Cystal Oscillator

....................... 58

External Power-on Reset Circuit

.........................65

External Series Crystal Oscillator

........................58

In-circuit Serial Programming

...............................71

Interrupt Logic

......................................................... 66

On-chip Reset Circuit

............................................59

Parallel Slave Port, PORTD-PORTE

..................39

PIC16C641

.............................................................. 10

PIC16C642

.............................................................. 10

PIC16C661

.............................................................. 11

PIC16C662

.............................................................. 11

PORTC (In I/O Port Mode)

...................................34

PORTD (In I/O Port Mode)

...................................35

PORTE (In I/O Port Mode)

...................................37

RA1:RA0 pins

..........................................................29

RA3 pin

.....................................................................30

RA4 pin

.....................................................................31

RB3:RB0 pins

..........................................................32

RB7:RB4 pins

..........................................................32

RC Oscillator

........................................................... 58

Single Comparator

................................................. 49

Timer0

......................................................................41

Timer0/WDT Prescaler

..........................................44

Voltage Reference

.................................................53

Voltage Reference Output Buffer

........................ 54

Watchdog Timer

.....................................................69

Brown-out Reset (BOR)

................................................60

BSF Instruction

...............................................................77

BTFSC Instruction

..........................................................77

BTFSS Instruction

.......................................................... 78

C Compiler (MPLAB-C)

.................................................89

CALL Instruction

............................................................. 78

Clocking Scheme/Instruction Cycle

.............................15

CLRF Instruction

.............................................................78

CLRW Instruction

...........................................................78

CLRWDT Instruction

......................................................79

CMCON Register

............................................................47

Code Examples

Changing Prescaler (T0 to WDT)

........................ 45

Changing Prescaler (WDT to T0)

........................ 45

Indirect Addressing

................................................ 28

Initializing Comparator Module

............................ 49

Initializing PORTA

.................................................. 29

Initializing PORTC

.................................................. 34

Read-Modify-Write Instructions on an I/O Port

.38

Saving the STATUS and W Registers in RAM

.68

Voltage Reference Configuration

........................ 54

Code Protection

.............................................................. 71

COMF Instruction

........................................................... 79

Comparator Configuration

............................................ 48

Comparator Interrupt

..................................................... 51

Comparator Module

....................................................... 47

Comparator Operation

.................................................. 49

Comparator Reference

.................................................. 49

Configuration Bits

........................................................... 56

Configuring the Voltage Reference

............................. 54

Data Memory Organization

.......................................... 18

DECF Instruction

............................................................ 79

DECFSZ Instruction

....................................................... 79

Development Support

.................................................... 87

Development Tools

........................................................ 87

Device Drawings

28-Lead Ceramic CERDIP Dual In-line with Win-

dow (300 mil))

....................................... 107

28-Lead Ceramic Dual In-Line with Window (JW) -

(300 mil)

................................................. 107

28-Lead Plastic Small Outline (SO) - Wide, 300 mil

Body

....................................................... 106

28-Lead Skinny Plastic Dual In-Line (SP) -

300 mil

................................................... 105

40-Lead Ceramic Dual In-Line with Window

(JW) - (600 mil)

..................................... 108

40-Lead Plastic Dual In-Line (P) - 600 mil

....... 109

44-Lead Plastic Leaded Chip Carrier (L) -

Square

................................................... 110

44-Lead Plastic Quad Flatpack (PQ) - 10x10x2

mm Body 1.6/0.15 mm Lead Form

... 111

Family of Devices

PIC14XXX

............................................................. 117

PIC16C5X

............................................................. 118

PIC16C64X

................................................................6

PIC16C66X

................................................................6

PIC16C6X

............................................................. 120

PIC16C7X

............................................................. 121

PIC16C8X

............................................................. 122

PIC16C9XX

........................................................... 123

PIC16CXXX

.......................................................... 119

PIC17CXX

............................................................. 124

Fuzzy Logic Dev. System (

fuzzy

TECH



-MP)

.... 87, 89

General Purpose Register File

.................................... 18

GOTO Instruction

........................................................... 80

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 128

Preliminary



1996 Microchip Technology Inc.

I/O Ports

...........................................................................29

PORTA

..................................................................... 29

PORTB

..................................................................... 32

PORTC

.....................................................................34

PORTD

.....................................................................35

PORTE

..................................................................... 36

I/O Programming Considerations

................................38

ICEPIC In-Circuit Emulator

........................................... 87

ID Locations

.....................................................................71

INCF Instruction

.............................................................. 80

INCFSZ Instruction

.........................................................80

In-Circuit Serial Programming

...................................... 71

Indirect Addressing, INDF and FSR Registers

.........28

Instruction Flow/Pipelining

............................................ 15

Instruction Format

...........................................................73

Instruction Set

ADDLW

....................................................................76

ADDWF ....................................................................76

ANDLW ....................................................................76

ANDWF ....................................................................76

BCF ........................................................................... 77

BSF ...........................................................................77

BTFSC ......................................................................77

BTFSS ...................................................................... 78

CALL ......................................................................... 78

CLRF ........................................................................78

CLRW .......................................................................78

CLRWDT ..................................................................79

COMF .......................................................................79

DECF ........................................................................ 79

DECFSZ ...................................................................79

GOTO .......................................................................80

INCF ..........................................................................80

INCFSZ ....................................................................80

IORLW ......................................................................80

IORWF ......................................................................81

MOVF .......................................................................81

MOVLW ....................................................................81

MOVWF ....................................................................81

NOP ..........................................................................82

OPTION ....................................................................82

RETFIE .....................................................................82

RETLW .....................................................................82

RETURN ..................................................................83

RLF ...........................................................................83

RRF ...........................................................................83

SLEEP ...................................................................... 83

SUBLW .....................................................................84

SUBWF ....................................................................84

SWAPF .....................................................................85

TRIS ..........................................................................85

XORLW ....................................................................85

XORWF .................................................................... 85

Section ......................................................................73

Summary Table ......................................................75

INT Interrupt ....................................................................67

INTCON Register ...........................................................23

Interrupts .......................................................................... 66

Comparator ..............................................................51

PORTB Change ..................................................... 32

PSP Read-Write ..................................................... 39

RB0/INT ................................................................... 66

Section ..................................................................... 66

Timer0 ...................................................................... 41

Timer0, Timing ........................................................ 42

IORLW Instruction .......................................................... 80

IORWF Instruction ......................................................... 81

MOVF Instruction ........................................................... 81

MOVLW Instruction ........................................................ 81

MOVWF Instruction ....................................................... 81

MPASM Assembler .................................................. 87, 88

MPLAB-C C Compiler ................................................... 89

MPLAB-SIM Software Simulator ........................... 87, 89

NOP Instruction .............................................................. 82

One-Time-Programmable (OTP) Devices ................... 7

Opcode ............................................................................. 73

OPTION Instruction ....................................................... 82

OPTION Register ........................................................... 22

Oscillator Configurations ............................................... 57

Oscillator Start-up Timer (OST) ................................... 60

Package Marking Information ............................ 112, 113

Packaging Information ................................................. 105

Parallel Slave Port ......................................................... 35

Section ..................................................................... 39

Parity Error Reset (PER) ........................................ 60, 61

PCL ................................................................................... 74

PCL and PCLATH .......................................................... 27

PCON Register ......................................................... 26, 61

PICDEM-1 Low-Cost PIC16/17 Demo Board ..... 87, 88

PICDEM-2 Low-Cost PIC16CXX Demo Board ... 87, 88

PICDEM-3 Low-Cost PIC16C9XX Demo Board ...... 88

PICDEM-3 PIC16C9XX Low-Cost Demonstration

Board ................................................................ 87

PICMASTER High Performance

In-Circuit Emulator ......................................... 87

PICSTART Plus Entry Level Development

System ............................................................. 87

PICSTART Plus Entrvel Prototype

Programmer .................................................... 87

PIE1 Register .................................................................. 24

Pin Compatible Devices .............................................. 125

Pin Functions

RD7/PSP7:RD0/PSP0 .......................................... 14

RE0/RD .......................................................14, 39

RE1/WR ......................................................14, 39

RE2/CS .......................................................14, 39

PIR1 Register .................................................................. 25

Port RB Interrupt ............................................................ 67

PORTA ............................................................................. 29

PORTB ............................................................................. 32

PORTC Register ............................................................ 34

PORTD Register ............................................................ 35

 1996 Microchip Technology Inc. Preliminary DS30559A-page 129

PIC16C64X & PIC16C66X

PORTE Register .............................................................36

Ports

Parallel Slave Port ..................................................39

PORTA ..................................................................... 29

PORTB ..................................................................... 32

PORTC .....................................................................34

PORTD .....................................................................14

PORTE ..................................................................... 14

Power Control/Status Register (PCON) ..................... 61

Power-down Mode (SLEEP) ........................................70

Power-on Reset (POR) .................................................60

Power-up Timer (PWRT) ...............................................60

Prescaler ..........................................................................44

PRO MATE Universal Programmer ..........................87

Program Memory Organization ....................................17

PSPMODE bit ...........................................................35, 36

Quick-Turnaround-Production (QTP) Devices ............ 7

RA2 pin .............................................................................30

RC Oscillator ................................................................... 58

Reset ................................................................................59

RETFIE Instruction .........................................................82

RETLW Instruction ......................................................... 82

RETURN Instruction ......................................................83

RLF Instruction ................................................................83

RRF Instruction ...............................................................83

Serialized Quick-Turnaround-Production (SQTP)

Devices ..............................................................7

SFR ...................................................................................74

SFR As Source/Destination ..........................................74

SLEEP Instruction .......................................................... 83

Software Simulator (MPLAB-SIM) ...............................89

Special Features of the CPU ........................................55

Special Function Registers .....................................19, 74

Stack .................................................................................27

STATUS Register ...........................................................21

SUBLW Instruction .........................................................84

SUBWF Instruction .........................................................84

SWAPF Instruction .........................................................85

Switching Prescalers .....................................................45

Timer Modules

Timer0

Block Diagram .................................................41

Counter Mode ................................................. 41

External Clock .................................................43

Interrupt ............................................................41

Prescaler ..........................................................44

Section .............................................................41

Timer Mode .....................................................41

Timing Diagram ..............................................41

TMR0 register ................................................. 41

Timing Diagrams and Specifications ..........................98

TMR0 Interrupt ................................................................67

TRIS Instruction .............................................................. 85

TRISA ............................................................................... 29

TRISB ............................................................................... 32

TRISC Register .............................................................. 34

TRISD Register .............................................................. 35

TRISE Register ............................................................... 36

Voltage Reference Module ........................................... 53

VRCON Register ............................................................ 53

Watchdog Timer (WDT) ................................................ 69

XORLW Instruction ........................................................ 85

XORWF Instruction ........................................................ 85

LIST OF EXAMPLES

Example 3-1:Instruction Pipeline Flow ............................... 15

Example 4-1:Indirect Addressing........................................ 28

Example 5-1:Initializing PORTA ......................................... 29

Example 5-2:Initializing PORTC......................................... 34

Example 5-3:Read-Modify-Write Instructions on an

I/O Port.......................................................... 38

Example 6-1:Changing Prescaler (Timer0→WDT)............. 45

Example 6-2:Changing Prescaler (WDT→Timer0)............. 45

Example 7-1:Initializing Comparator Module...................... 49

Example 8-1:Voltage Reference Configuration.................. 54

Example 9-1:Saving the STATUS and W Registers in

RAM............................................................... 68

LIST OF FIGURES

Figure 3-1: PIC16C641/642 Block Diagram..................... 10

Figure 3-2: PIC16C661/662 Block Diagram..................... 11

Figure 3-3: Clock/Instruction Cycle.................................. 15

Figure 4-1: PIC16C641/661 Program Memory Map and

Stack.............................................................. 17

Figure 4-2: PIC16C642/662 Program Memory Map and

Stack.............................................................. 17

Figure 4-3: PIC16C641/661 Data Memory Map .............. 18

Figure 4-4: PIC16C642/662 Data Memory Map .............. 19

Figure 4-5: STATUS Register (Address 03h, 83h) .......... 21

Figure 4-6: OPTION Register (address 81h) ................... 22

Figure 4-7: INTCON Register (address 0Bh, 8Bh) .......... 23

Figure 4-8: PIE1 Register (address 8Ch)......................... 24

Figure 4-9: PIR1 Register (address 0Ch) ........................ 25

Figure 4-10: PCON Register (Address 8Eh)...................... 26

Figure 4-11: Loading Of PC In Different Situations............ 27

Figure 4-12: Direct/indirect Addressing.............................. 28

Figure 5-1: Block Diagram of RA1:RA0 Pins ................... 29

Figure 5-2: Block Diagram of RA2 Pin............................. 30

Figure 5-3: Block Diagram of RA3 Pin............................. 30

Figure 5-4: Block Diagram of RA4 Pin............................. 31

Figure 5-5: Block Diagram of RB7:RB4 Pins ................... 32

Figure 5-6: Block Diagram of RB3:RB0 Pins ................... 32

Figure 5-7: PORTC Block Diagram (in I/O port Mode) .... 34

Figure 5-8: PORTD Block Diagram (in I/O Port Mode).... 35

Figure 5-9: TRISE Register (Address 89h)...................... 36

Figure 5-10: PORTE Block Diagram (in I/O Port Mode).... 37

Figure 5-11: Successive I/O Operation.............................. 38

Figure 5-12: PORTD and PORTE as a Parallel Slave Port39

Figure 6-1: Timer0 Block Diagram................................... 41

Figure 6-2: Timer0 Timing: Internal Clock/No Prescaler.. 41

Figure 6-3: Timer0 Timing: Internal Clock/Prescale 1:2... 42

PIC16C64X & PIC16C66X

DS30559A-page 130 Preliminary  1996 Microchip Technology Inc.

Figure 6-4: Timer0 Interrupt Timing..................................42

Figure 6-5: Timer0 Timing With External Clock................43

Figure 6-6: Block Diagram of the Timer0/WDT Prescaler 44

Figure 7-1: CMCON Register (Address 1Fh) ...................47

Figure 7-2: Comparator I/O Operating Modes..................48

Figure 7-3: Single Comparator.........................................49

Figure 7-4: Comparator Output Block Diagram................50

Figure 7-5: Analog Input Model........................................51

Figure 8-1: VRCON Register(Address 9Fh).....................53

Figure 8-2: Voltage Reference Block Diagram.................53

Figure 8-3: Voltage Reference Output Buffer Example....54

Figure 9-1: Configuration Word........................................56

Figure 9-2: Crystal Operation

(or Ceramic Resonator)

(HS, XT or LP Osc Configuration)..................57

Figure 9-3: External Clock Input Operation

(HS, XT or LP Osc Configuration)..................57

Figure 9-4: External Parallel Resonant Crystal Oscillator

Circuit.............................................................58

Figure 9-5: External Series Resonant Crystal Oscillator

Circuit.............................................................58

Figure 9-6: RC Oscillator Mode........................................58

Figure 9-7: Simplified Block Diagram of On-chip Reset

Circuit.............................................................59

Figure 9-8: Brown-out Situations......................................60

Figure 9-9: Time-out Sequence on Power-up (MCLR not

tied to VDD): Case 1.......................................64

Figure 9-10: Time-out Sequence on Power-up (MCLR not

tied to VDD): Case 2.......................................64

Figure 9-11: Time-out Sequence on Power-up (MCLR tied to

VDD) ...............................................................64

Figure 9-12: External Power-on Reset Circuit (For Slow VDD

Power-up) ......................................................65

Figure 9-13: External Brown-out Protection Circuit 1.........65

Figure 9-14: External Brown-out Protection Circuit 2.........65

Figure 9-15: Interrupt Logic................................................66

Figure 9-16: RB0/INT Pin Interrupt Timing.........................67

Figure 9-17: Watchdog Timer Block Diagram ....................69

Figure 9-18: Summary of Watchdog Timer Registers........69

Figure 9-19: Wake-up from Sleep Through Interrupt .........70

Figure 9-20: Typical In-Circuit Serial Programming

Connection.....................................................71

Figure 10-1: General Format for Instructions .....................73

Figure 12-1: Load Conditions.............................................97

Figure 12-2: External Clock Timing....................................98

Figure 12-3: CLKOUT and I/O Timing................................99

Figure 12-4: Reset, Watchdog Timer, Oscillator Start-Up Tim-

er, and Power-Up Timer Timing...................100

Figure 12-5: Brown-out Reset Timing ..............................100

Figure 12-6: Timer0 Clock Timing....................................101

Figure 12-7: Parallel Slave Port Timing (PIC16C661 and

PIC16C662) .................................................102

LIST OF TABLES

Table 1-1: PIC16C64X & PIC16C66X Device Features ...6

Table 3-1: PIC16C641/642 Pinout Description ...............12

Table 3-2: PIC16C661/662 Pinout Description ...............13

Table 4-1: Special Function Registers ............................20

Table 5-1: PORTA Functions..........................................31

Table 5-2: Summary of Registers Associated With

PORTA...........................................................31

Table 5-3: PORTB Functions..........................................33

Table 5-4: Summary of Registers Associated with

PORTB...........................................................33

Table 5-5: PORTC Functions..........................................34

Table 5-6: Summary of Registers Associated with

PORTC.......................................................... 34

Table 5-7: PORTD Functions.......................................... 35

Table 5-8: Summary of Registers Associated with

PORTD.......................................................... 35

Table 5-9: PORTE Functions.......................................... 37

Table 5-10: Summary of Registers Associated with

PORTE .......................................................... 37

Table 5-11: Registers Associated with Parallel Slave Port39

Table 6-1: Registers Associated with Timer0 ................. 45

Table 7-1: Registers Associated with

Comparator Module....................................... 52

Table 8-1: Registers Associated with Voltage Reference54

Table 9-1: Capacitor Selection for Ceramic Resonators

(Preliminary) .................................................. 57

Table 9-2: Capacitor Selection for Crystal Oscillator

(Preliminary) .................................................. 57

Table 9-3: Time-out in Various Situations....................... 61

Table 9-4: Status Bits and Their Significance................. 62

Table 9-5: Initialization Condition for Special Registers.. 62

Table 9-6: Initialization Condition for Registers .............. 63

Table 10-1: Opcode Field Descriptions............................. 73

Table 10-2: Instruction Set................................................ 75

Table 11-1: Development Tools From Microchip.............. 90

Table 12-1: Cross Reference of Device Specs for Oscillator

Configurations and Frequencies of Operation

(Commercial Devices) ................................... 91

Table 12-2: Comparator Specifications............................. 96

Table 12-3: Voltage Reference Specifications.................. 96

Table 12-4: External Clock Timing Requirements ............ 98

Table 12-5: CLKOUT and I/O Timing Requirements........ 99

Table 12-6: Reset, Watchdog Timer, Oscillator Start-up Tim-

er, Power-up Timer, and Brown-out Reset Re-

quirements................................................... 100

Table 12-7: Timer0 Clock Requirements........................ 101

Table 12-8: Parallel Slave Port Requirements (PIC16C661

and PIC16C662).......................................... 102

Table E-1: Pin Compatible Devices............................... 125



1996 Microchip Technology Inc. DS30559A-page 131

PIC16C64X & PIC16C66X

ON-LINE SUPPORT

Microchip provides two methods of on-line support.

These are the Microchip BBS and the Microchip World

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Connecting to the Microchip Internet Web Site

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Connecting to the Microchip BBS

Connect worldwide to the Microchip BBS using either

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You can telnet or ftp to the Microchip BBS at the

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Trademarks:

The Microchip name, logo, PIC, PICSTART,

PICMASTER, and are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

Flex

ROM, MPLAB, PRO MATE, and

fuzzy

LAB, are trade-

marks and SQTP is a service mark of Microchip in the

U.S.A.

fuzzy

TECH is a registered trademark of Inform Software

Corporation. IBM, IBM PC-A T are registered trademarks of

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All other trademarks mentioned herein are the property of

their respective companies.

This document was created with FrameMaker404

PIC16C64X & PIC16C66X

DS30559A-page 132



1996 Microchip Technology Inc.

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3. Do you ﬁnd the organization of this data sheet easy to follow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deletions from the data sheet could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products?

To: Technical Publications Manager

RE: Reader Response Total Pages Sent

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS30559A

PIC16C64X &

PIC16C66X



1996 Microchip Technology Inc. DS30559A-page 133

PIC16C64X & PIC16C66X

NOTES:

PIC16C64X & PIC16C66X

DS30559A-page 134



1996 Microchip Technology Inc.

NOTES:



1996 Microchip Technology Inc. DS30559A-page 135

PIC16C64X & PIC16C66X

PIC16C64X & PIC16C66X PRODUCT IDENTIFICATION SYSTEM

Please contact your local sales ofﬁce for exact ordering procedures.

JW devices are UV erasable and can be programmed to any device conﬁguration. JW devices meet the electrical

requirements of each oscillator type (including LC devices).

Pattern: Special Requirements

Package: SO = SOIC

L = PLCC

P = PDIP

TQ = TQFP

SP = Skinny DIP

JW = Windowed DIP

Temperature

Range: -=0°C to +70°C

I = -40°C to +85°C

E = -40°C to +125°C

Frequency

Range: 04 = 4 MHz

10 = 10MHz

20 = 20 MHz

Device

PART NO. -XX X /XX XXX Examples

a) PIC16C662-04/P

Commercial Temp.,

PDIP Package, 4 MHz,

normal VDD limits

b) PIC16C662-04I/SO

Industrial Temp., SOIC

package, 4 MHz, normal

VDD limits

c) PIC16C662-04E/P

Automotive Temp.,

PDIP package, 4 MHz,

normal VDD limits

Sales and Support

Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

Your local Microchip sales ofﬁce (see below)

The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.

 2002 Microchip Technology Inc.

Information contained in this publication regarding device

applications and the like is intended through sug gestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microc hip Technology Inc orporated with respect

to the accuracy or use of such inf orm ation, or inf ringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’ s products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,

KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip Tech-

nology Incorporated in the U.S.A. and other countries.

dsPIC, ECONOMONITOR, FanSense, FlexRO M, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode

and Total Endurance are trademarks of Microchip Technology

Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorpora ted in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper .

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and T empe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.

Note the following details of the code protection feature on PICmicro® MCUs.

•The PICmicro family meets the specifications contained in the Microchip Data Sheet.

•Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,

when used in the intended manner and under normal conditions.

•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-

edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.

The person doing so may be engaged in theft of intellectual property.

•Microchip is willing to work with the customer who is concerned about the integrity of their code.

•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable”.

•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of

our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.

 2002 Microchip Technology Inc.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

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Tel: 480-792-7200 Fax: 480-792-7277

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Microchip Technology Inc.

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Toronto

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ASIA/PACIFIC

Australia

Microchip Technology Australia Pty Ltd

Suite 22, 41 Rawson S treet

Epping 212 1, NSW

Australia

Tel: 61-2-9868-6733 Fax: 61-2-9868-6755

China - Beijing

Microchip Technology Consulting (Shanghai)

Co., Ltd., Beijing Liaison Office

Unit 915

Bei Hai Wa n Tai Bldg.

No. 6 Chaoyangmen Beidajie

Beijing, 100027, No. China

Tel: 86-10-85282100 Fax: 86-10-85282104

China - Chengdu

Microchip Technology Consulting (Shanghai)

Co., Ltd., Chengdu Liaison Office

Rm. 2401, 24th Floor,

Ming Xing Financial Tower

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Cheng du 610 016 , Chi na

Tel: 86-28-6766200 Fax: 86-28-6766599

China - Fuzhou

Microchip Technology Consulting (Shanghai)

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Room 701, Bldg. B

Far East International Plaza

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Co., Ltd., Shenzhen Liaison Office

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Renminnan Lu

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Tel: 86-755-2350361 Fax: 86-755-2366086

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India

Microchip Technology Inc.

India Liaiso n Office

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1 Floor, Wing A (A3/A4 )

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Microc hip Tech nolo gy Ko rea

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Microchip Technology Singapore Pte Ltd.

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#07-02 Prime Centre

Singapore, 188980

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Microc hip Tech nolo gy Taiwan

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Tung Hua North Road

Taipei, 105, Taiwan

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPE

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Microc hip Tech nolo gy SARL

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Microc hip Tech nolo gy Gmb H

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Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

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Microc hip Tech nolo gy SRL

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01/18/02

WORLDWIDE SALES AND SERVICE